KR20080108867A - Input buffer circuit of semiconductor memory apparatus - Google Patents

Input buffer circuit of semiconductor memory apparatus Download PDF

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Publication number
KR20080108867A
KR20080108867A KR1020070056962A KR20070056962A KR20080108867A KR 20080108867 A KR20080108867 A KR 20080108867A KR 1020070056962 A KR1020070056962 A KR 1020070056962A KR 20070056962 A KR20070056962 A KR 20070056962A KR 20080108867 A KR20080108867 A KR 20080108867A
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South Korea
Prior art keywords
signal
level
node
enable
receives
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KR1020070056962A
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Korean (ko)
Inventor
김미혜
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주식회사 하이닉스반도체
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Priority to KR1020070056962A priority Critical patent/KR20080108867A/en
Publication of KR20080108867A publication Critical patent/KR20080108867A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Abstract

Disclosed is an input buffer circuit of a semiconductor memory device, comprising: a buffer controller configured to sequentially activate and output a plurality of enable signals in response to a test signal; And a buffer unit in which a sink current amount varies according to the plurality of enable signals, and an output level is determined according to a difference between a reference voltage and a potential level of an input signal.

Description

Input buffer circuit of semiconductor memory device

1 is a circuit diagram of an input buffer circuit according to the prior art;

2 is a block diagram of an input buffer circuit according to an embodiment of the present invention;

3 is a block diagram of a buffer enable signal generation unit shown in FIG. 2;

4 is a circuit diagram of a first counter unit shown in FIG. 3;

5 is a circuit diagram of a second counter unit shown in FIG. 3;

6 is a circuit diagram of a floating prevention signal generation unit shown in FIG. 2;

7 is a block diagram of the buffer unit shown in FIG. 2;

8 is a circuit diagram of a buffer unit shown in FIG. 7, and

9 is a timing diagram of an input buffer circuit according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: buffer control unit 110: buffer enable signal generation unit

120: floating prevention signal generation unit 200: buffer unit

The present invention relates to a semiconductor memory device, and more particularly to an input buffer circuit.

An input buffer circuit of a semiconductor memory device is a portion that buffers an applied signal and is input into a semiconductor device, and includes a CMOS static input buffer and a differential amplification input buffer. The CMOS static input buffer has an advantage in that its configuration is very simple, but has a weakness in noise immunity.

The differential amplification type input buffer circuit has a good margin depending on the level of the input signal Vin, and the amount of sink current greatly affects the performance of the input buffer circuit.

1 is a circuit diagram of an input buffer circuit according to the prior art.

Referring to FIG. 1, in the conventional input buffer circuit, NMOS transistors N15 and N16, which are sink transistors, receive a control signal en for sinking current, and receive a reference voltage Vref and an input signal voltage Vin. The differential amplifier type comparators N11 to N14 and P11 to P16 compare and output the comparison result as the output signal OUT through the drivers P17 and N17. In this case, when the control signal en is at the 'high' level, the input buffer circuit sets the output signal OUT to 'high' or 'in accordance with the difference between the reference voltage Vref and the input signal voltage Vin. Low level output. When the control signal en is at the 'low' level, the comparator is not driven and the PMOS transistors P11 and P12 are turned on to prevent the input buffer circuit from floating.

The input buffer circuit according to the prior art connects the sink transistor N16, which determines the amount of sink current, to a metal switch MS1. When the metal switch MS1 is opened, no current flows through the NMOS transistor N16. At this time, only the NMOS transistor N15 sinks current. Therefore, the total sink current amount is determined by the width of the NMOS transistor N15. When the metal switch MS1 is closed, the NMOS transistor N16 is connected to the second node Node12 to sink current. The amount of sink current is determined by the sum of the width of the NMOS transistor N15 and the width of the NMOS transistor N16.

As described above, in order to control the sink current amount, in order to adjust the metal switch MS1, a mask revision process has to be performed, which results in a long time and a high cost.

An input buffer circuit of a semiconductor memory device according to the present invention has an object to adjust the amount of sink current without performing mask revision.

An input buffer circuit of a semiconductor memory device according to the present invention includes a buffer controller for sequentially activating and outputting a plurality of enable signals for varying a sink current amount in response to a test signal; And a buffer unit in which a sink current amount varies according to the plurality of enable signals, and an output level is determined according to a difference between a reference voltage and a potential level of an input signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

2 is a block diagram of an input buffer circuit according to an embodiment of the present invention.

Referring to FIG. 2, the input buffer circuit receives a test signal TM and a reset signal RST, and includes a first enable signal en1 and a second enable signal for enabling the buffer unit 200. en2) and a buffer controller 100 for outputting the floating prevention signal FPS, and the first enable signal en1, the second enable signal en2, and the floating prevention signal FPS. And a buffer unit 200 for outputting an internal input signal by comparing the reference voltage Vref and the input signal voltage Vin.

The buffer controller 100 receives the test signal TM and the reset signal RST and receives the first enable signal en1 and the second enable signal for driving the buffer 200. A buffer enable signal generation unit 110 for outputting en2) and a floating prevention signal generation unit 120 for outputting a floating prevention signal FPS for preventing the buffer unit 200 from floating. The test signal TM maintains a 'low' level when not in the test mode and is input as a pulse when entering the test mode. The test signal TM generates one pulse every time a test signal is input. Here, the reset signal RST is a signal that maintains an initial value at a 'high' level and maintains a 'low' level when the semiconductor memory device operates.

3 is a block diagram of a buffer enable signal generator shown in FIG. 2.

Referring to FIG. 3, the buffer enable signal generator 110 receives a reset signal RST and a test signal TM and outputs the first enable signal en1 to the first counter unit 111. And a second counter unit 112 that receives the first enable signal en1 and the reset signal RST and outputs the second enable signal en2.

4 is a circuit diagram of the first counter unit illustrated in FIG. 3.

Referring to FIG. 4, the first counter 111 may include first to third inverters IV1, IV2, and IV3, first to third tree state inverters (Tri-State Inverters (TIV1, TIV2, TIV3)), A first NAND gate ND1, a first passgate TP1, and a first NOR gate NR1 are provided. The first inverter IV1 receives and outputs the test signal TM, and the second inverter IV2 receives and outputs a reset signal RST. The first tree state inverter TIV1 receives a signal of the fourth node S4 at an input terminal, a signal of the first inverter IV1 at a first control terminal, and the test signal at a second control terminal. It receives (TM) and applies an output signal to the first node (S1). The second tree state inverter TIV2 receives a signal of the second node S2 at an input terminal, receives the test signal TM at a first control terminal, and receives the first inverter IV1 at a second control terminal. ) Outputs the output signal to the first node S1. The first NAND gate ND1 receives a signal of the first node S1 and an output of the second inverter IV2 and applies an output signal to the second node S2. In the first passgate TP1, an input terminal receives a signal of the second node S2, a first control terminal receives an output signal of the first inverter IV1, and a second control terminal receives the test signal. The signal TM is received and applied to the third node S3. The first NOR gate NR1 receives the signal of the third node S3 and the reset signal RST and applies an output signal to the fourth node S4. The third tree state inverter TIV3 receives a signal of the fourth node S4 at an input terminal, a first control terminal receives a signal of the first inverter IV1, and a second control terminal receives the test signal. The signal TM is input and outputs an output signal to the third node S3. The third inverter IV3 receives the signal of the fourth node S4 and outputs a first enable signal en1.

When the test signal TM is at the 'low' level, the second tree state inverter TIV2 and the first passgate TP1 are turned on, and the first and third tree state inverters TIV1 and TIV3 are turned on. Is turned off.

When the test signal TM is at the 'high' level, the first tree state inverter TIV1 and the third tree state inverter TIV3 are turned on, and the second tree state inverter TIV2 and the first tree are turned on. Passgate TP1 is turned off.

When the test signal TM is at the 'low' level, the signal of the first node S1 and the signal of the second node S2 are latched as the second tree state inverter TIV2 is turned on. The first passgate TP1 applies a signal of the second node S2 to the third node S3. The signal of the third node S3 is ORed with the reset signal RST and output as the first enable signal en1.

When the reset signal RST is at the 'high' level, the first NAND gate ND1 applies an output signal having a 'high' level to the second node S2 regardless of the level of the input signal. The second tree state inverter TIV2 receives the signal of the second node S2 having the 'high' level and applies an output signal of the 'low' level to the first node S1. The signal of the first node S1 having the 'low' level and the signal of the second node S2 having the 'high' level are latched. The first passgate TP1 receives a signal of the second node S2 having the 'high' level and applies an output signal of the 'high' level to the third node S3. The first NOR gate NR1 receives the signal of the third node S3 having the 'high' level and the reset signal RST of the 'high' level, and outputs an output signal of the 'low' level to the fourth node. It is applied to (S4). The third inverter IV3 inverts the signal of the fourth node S4 having the 'low' level and outputs the first enable signal en1 having the 'high' level. At this time, the signal of the fourth node S4 is fed back to the first tree state inverter TIV1.

On the other hand, when the reset signal RST is at the 'low' level, the first NAND gate ND1 is the output signal of the second inverter IV2 having the 'high' level and the first node having the 'low' level. The signal of S1 is input and the second node S2 receives an output signal having a 'high' level. The signal of the second node S2 having the 'high' level is latched and input to the first passgate TP1. The first passgate TP1 receives a signal of the second node S2 having the 'high' level and applies an output signal of the 'high' level to the third node S3. The first NOR gate NR1 receives the signal of the third node S3 having the 'high' level and the reset signal RST of the 'low' level, and outputs an output signal of the 'low' level to the fourth node. It is applied to (S4). The third inverter IV3 receives the signal of the fourth node S4 having the 'low' level and outputs the first enable signal en1 having the 'high' level.

When the test signal TM transitions to the 'high' level, the first tree state inverter TIV1 receives the signal of the fourth node S4 having the 'low' level and outputs an output signal of the 'high' level. Is applied to the first node S1. The first NAND gate ND1 receives the signal of the first node S1 having the 'high' level and the output signal of the second inverter IV2 having the 'high' level and receives an output signal of the 'low' level. It applies to the second node S2. The second node S2 maintains a 'low' level signal as the first passgate TP1 is turned off. The third tree state inverter TIV3 receives the signal of the fourth node S4 of the 'low' level and applies a signal of the 'high' level to the third node S3. The third inverter IV3 receives the signal of the fourth node S4 having the 'low' level and outputs the first enable signal en1 having the 'high' level.

Subsequently, when the test signal TM transitions to the 'low' level, the second tree state inverter TIV2 receives the 'low' level signal and outputs an 'high' level output signal to the first node S1. ) Is applied. The first NAND gate ND1 receives an output signal of the second tree state inverter TIV2 having the 'high' level and an output signal of the second inverter IV2 having the 'high' level and receives a low level. The output signal is applied to the second node S2. As the first passgate TP1 is turned on, the first pass gate TP1 receives a signal of the second node S2 having the 'low' level, and applies an output signal having the 'low' level to the third node S3. The first NOR gate NR1 receives the signal of the third node S3 having the 'low' level and the reset signal RST of the 'low' level, and outputs an output signal of the 'high' level to the fourth node. It is applied to (S4). The third inverter IV3 receives the 'high' level signal and outputs the first enable signal en1 having the 'low' level.

As described above, when the test signal TM transitions to the 'low' level, the first enable signal en1 is toggled.

FIG. 5 is a circuit diagram of the second counter unit shown in FIG. 3.

Referring to FIG. 5, the second counter unit 112 may include fourth to sixth inverters IV4, IV5, and IV6, fourth to sixth tree state inverters TIV4, TIV5, and TIV6, and a second NOR gate NR2. ), A second pass gate TP2, and a second NAND gate ND2. The fourth inverter IV4 receives and outputs the first enable signal en1 and the fifth inverter IV5 receives and outputs the reset signal RST. The fourth tree state inverter TIV4 receives a signal of the eighth node S8 at an input terminal, a first control terminal receives an output signal of the fourth inverter IV4, and a second control terminal receives the first signal. The enable signal en1 is input to output the output signal to the fifth node S5. The fifth tree state inverter TIV5 receives a signal of the sixth node S6 at an input terminal, a first control terminal receives the first enable signal en1, and a second control terminal receives the fourth The output signal of the inverter IV4 is input and output to the fifth node S5. The second NOR gate NR2 receives the reset signal RST, receives the signal of the fifth node S5, and outputs an output signal to the sixth node S6. The second passgate TP2 receives a signal of the sixth node S6 at an input terminal, a first control terminal receives a signal of the fourth inverter IV4, and a second control terminal receives the first signal. The enable signal en2 is received and an output signal is applied to the seventh node S7. The second NAND gate ND2 receives the signal of the seventh node S7 and the output signal of the fifth inverter IV5 and outputs an output signal to the eighth node S8. The sixth tree state inverter TIV6 receives an output signal of the eighth node S8 at an input terminal, a first control terminal receives an output signal of the fourth inverter IV4, and a second control terminal The first enable signal en1 is received and an output signal is applied to the seventh node S7. The sixth inverter IV6 receives the signal of the eighth node S8 and outputs a second enable signal en2.

The second counter unit 112 operates on the same principle as the first counter unit 111. The first enable signal en1 has an initial value of 'high' level, but the second enable signal en2 has an initial value of 'low' level. Also, the first counter 111 receives the test signal TM as an input, but the second counter 112 receives the first enable signal en1 as an input.

When the first enable signal en1 is at the 'high' level and the reset signal is at the 'high' level, the fourth and sixth tree state inverters TIV4 and TIV6 are turned on and the fifth tree state inverter is turned on. TIV5 and second passgate TP2 are turned off. The second NAND gate ND2 receiving the inverted reset signal RST applies a 'high' level signal to the eighth node S8. The sixth inverter IV6 outputs the second enable signal en2 of the low level, which is an initial value.

When the first enable signal en1 is 'low' level and the reset signal is 'low' level, the fifth tree state inverter TIV5 and the second passgate TP2 are turned on, and the fourth And the sixth tree state inverters TIV4 and TIV5 are turned off. The fifth tree state inverter TIV5 receives a signal of the sixth node S6 having a 'low' level and applies an output signal having a 'low' level to the fifth node S5. The second passgate TP2 receives the signal of the sixth node S6 having the low level and applies an output signal of the low level to the seventh node S7. The second NAND gate ND2 receives the signal of the seventh node S7 of the 'low' level and the signal of the fifth inverter IV5 of the 'high' level and outputs an output signal of the 'low' level. Is applied to the eighth node S8. The sixth inverter IV6 receives the signal of the eighth node S8 having the 'low' level and outputs the second enable signal en2 having the 'high' level.

When the first enable signal en1 is at the 'high' level and the reset signal is at the 'low' level, the fourth and sixth tree state inverters TIV4 and TIV6 are turned on, and the fifth tree state inverter is turned on. TIV5 and second passgate TP2 are turned off. The fourth tree state inverter TIV4 receives the signal of the eighth node S8 having the 'low' level and applies an output signal of the 'high' level to the fifth node S5. The second NOR gate NR2 receives the signal of the fifth node S5 of the 'high' level and the reset signal RST of the 'low' level, and outputs an output signal of the 'low' level to the sixth. Is applied to node S6. The second NAND gate ND2 receives the signal of the seventh node S7 having the 'low' level and the signal of the fifth inverter IV5 having the 'high' level and outputs an output signal having the 'low' level. Is applied to the eighth node S8. The sixth inverter IV6 receives the signal of the eighth node S8 having the 'low' level and outputs the second enable signal en2 having the 'high' level.

If the first enable signal en1 is again at the low level and the reset signal RST is at the low level, the second enable signal en2 having the low level is output as described above. .

FIG. 6 is a circuit diagram of the floating prevention signal generator 120 shown in FIG. 2.

Referring to FIG. 6, the floating prevention signal generation unit 120 receives a third NOR gate NR3 that receives the first enable signal en1 and the second enable signal en2, and the third A seventh inverter IV7 receives the output of the noah gate NR3 and outputs the floating prevention signal FPS.

The floating prevention signal generation unit 120 outputs the floating prevention signal FPS having the 'high' level when at least one of the first and second enable signals en1 and en2 is 'high' level. When the first and second enable signals en1 and en2 are at the 'low' level, the floating prevention signal FPS having the 'low' level is output.

7 is a block diagram of the buffer unit illustrated in FIG. 2.

Referring to FIG. 7, the buffer unit 200 receives the floating prevention signal FPS, and is configured to prevent the floating of the node connected to the driving unit 250 and the reference voltage Vref. And a comparator 220 for comparing and outputting a potential level of the input signal voltage Vin, a first sink 230 receiving the first enable signal en1 to sink a current, and the second enable A second sink 240 for receiving a signal en2 and sinking a current, and a driver 250 for driving and outputting the output of the comparator 220.

FIG. 8 is a circuit diagram of the buffer unit shown in FIG. 7.

Referring to FIG. 8, the floating prevention unit 210 includes first and second PMOS transistors P1 and P2. The first PMOS transistor P1 includes a gate that receives the floating prevention signal FPS, a source connected to a power supply voltage VDD, and a drain. The second PMOS transistor P2 includes a gate for receiving the floating prevention signal FPS, a source connected to a power supply voltage VDD, and a drain.

In the floating prevention unit 210, when the floating prevention signal FPS is at a 'high' level, the first and second PMOS transistors P1 and P2 are turned off. That is, when any one of the first and second enable signals en1 and en2 is at a 'high' level, the first and second PMOS transistors P1 and P2 are turned off. When the floating prevention signal FPS is at the 'low' level, the first and second PMOS transistors P1 and P2 are turned on. That is, when the floating prevention signal FPS is at the 'low' level, the floating prevention signal FPS is enabled, and the first and second enable signals en1 and en2 are disabled. Here, when the first and second enable signals en1 and en2 are disabled, the buffer unit 200 does not operate and the input buffer circuit is floating. In order to prevent such floating, the floating prevention signal FPS is applied to the floating prevention unit 210 at a 'low' level, thereby fixing the first connection node Node1 to a 'high' level.

The comparison unit 220 includes third to sixth PMOS transistors P3 to P6 and first to fourth NMOS transistors N1 to N4. The third PMOS transistor P3 includes a gate that receives a reference voltage Vref, a source connected to a power supply voltage VDD, and a drain. The fourth PMOS transistor P4 includes a gate connected to a drain, a source connected to a power supply voltage VDD, and a drain connected to a drain of the third PMOS transistor P3. The fifth PMOS transistor P5 includes a gate connected to the gate of the fourth PMOS transistor P4, a source connected to the power supply voltage VDD, and a drain. The sixth PMOS transistor P6 includes a gate configured to receive an input signal voltage Vin, a source connected to a power supply voltage VDD, and a drain connected to a drain of the fifth PMOS transistor P5. The first NMOS transistor N1 includes a gate receiving the reference voltage Vref, a drain connected to the drain of the fourth PMOS transistor P4, and a source connected to the second connection node Node2. The second NMOS transistor N2 is connected to a drain, a gate commonly connected to the gate of the fourth PMOS transistor P4, a drain connected to the first NMOS transistor N1, and a second connection node Node2. Contains a source. The third NMOS transistor N3 may include a gate connected to the gate of the second NMOS transistor N2, a drain connected to the drain of the fifth PMOS transistor P5, and a source connected to the second connection node Node2. Include. The fourth NMOS transistor N4 includes a gate receiving the input signal voltage Vin, a drain connected to the drain of the third NMOS transistor N3, and a source connected to the second connection node Node2. .

Here, the same first current I1 always flows in the first NMOS transistor N1 receiving the reference voltage Vref. In the fourth NMOS transistor N4, the second current I2 determined by the potential level of the input signal voltage Vin flows. The comparison unit 200 determines the potential level of the first connection node Node1 by comparing the first current I1 and the second current I2.

For example, when any one of the first and second enable signals en1 and en2 is enabled, the comparator 200 operates. When the input signal voltage Vin is higher than the reference voltage Vref, the sixth PMOS transistor P6 is turned off and the fourth NMOS transistor N4 is turned on. The fourth NMOS transistor N4 has a low potential level and outputs a 'low' level signal to the first connection node Node1.

When the input signal voltage Vin is lower than the reference voltage Vref, the first NMOS transistor N1 is turned on and the third PMOS transistor P3 is turned off. The first NMOS transistor N1 has a lower potential level, and the fifth PMOS transistor P5 receiving the lower potential level is turned on. Since the fifth PMOS transistor P5 applies a power supply voltage VDD to the first connection node Node1, the first connection node Vode1 is at a low level.

The fifth sink 230 has a gate connected to the first enable signal en1, a source connected to a ground voltage VSS, and a drain connected to the second connection node Node2. NMOS transistor N5 is included.

The second sink 240 has a gate connected to the second enable signal en2, a source connected to a ground voltage VSS, and a drain connected to the second connection node Node2. NMOS transistor N6 is included.

The driver 250 includes a seventh PMOS transistor P7 having a gate connected to a signal of the first connection node Node1, a source connected to a power supply voltage VDD, and a drain connected to an output OUT. A gate includes a seventh NMOS transistor N7 connected to a signal of the first connection node Node1, a source connected to a ground voltage VSS terminal, and a drain connected to an output VSS terminal.

Here, when the signal of the first connection node Node1 of the 'high' level is applied, the seventh NMOS transistor N7 is turned on and outputs an output signal of the 'low' level to the output OUT. When the signal of the first connection node Node1 having the 'low' level is applied, the seventh PMOS transistor P7 is turned on and outputs an output signal having the 'high' level to the output OUT.

FIG. 9 is a timing diagram of the buffer control unit shown in FIG. 2.

Referring to FIG. 9, the first enable signal en1 toggles when the test signal TM transitions from the 'high' level to the 'low' level, and the second enable signal. en2 toggles when the first enable signal en1 transitions from the 'high' level to the 'low' level. The floating prevention signal FPS outputs a high level when any one of the first and second enable signals en1 and en2 reaches a high level.

In the conventional input buffer circuit, the metal switch MS1 is connected between the second node Node2 and the second sink 240 to mask the amount of current sink in the buffer 200. ).

However, the input buffer circuit according to the present invention connects the second connection node and the second sink 240 and adjusts the current sink amount as a test signal TM. For example, the width of the fifth NMOS transistor N5 of the first sink 230 is 10 and the width of the sixth NMOS transistor of the second sink 240 is 5. Assume

Before the test signal TM is input, the first enable signal en1 is at a 'high' level, the second enable signal en2 is at a 'low' level, and the floating prevention signal FPS is In the 'high' level, the total width of the fifth and sixth transistors N5 and N6 is 10.

When the pulse that is the test signal TM is applied once, the first enable signal en1 is at a low level, the second enable signal en2 is at a high level, and the floating prevention signal FPS is applied. Becomes the 'high' level, the sixth NMOS transistor N6 is turned on, so that the total width is five.

When the pulse, which is the test signal TM, is applied once again, the first enable signal en1 is at a high level, the second enable signal en2 is at a high level, and the floating prevention signal FPS. ) Becomes the 'high' level so that the fifth and sixth NMOS transistors N5 and N6 are turned on, so that the total width is 15.

When the pulse, which is the test signal TM, is applied once again, the first enable signal en1 is at a low level, the second enable signal en2 is at a low level, and the floating prevention signal FPS. ) Becomes the 'low' level, the fifth NMOS transistor N5 is turned on, so that the total width is zero.

The first and second enable signals en1 and en2 are embodiments for controlling sink transistors provided in the buffer unit 200. The number of enable signals may vary depending on the number of sink transistors. . For example, if there are three sink transistors, the buffer enable signal generator 100 may include three counters to output three enable signals.

The input buffer circuit according to the present invention can adjust the amount of sink current (that is, the width of the sink transistor) according to the number of inputs of the pulse of the test signal TM. Therefore, the input frequency of the pulse of the test signal TM may be adjusted so that the amount of sink current showing the desired response characteristic.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The input buffer circuit of the semiconductor memory device according to the present invention can easily and quickly adjust the response characteristic by using a test signal without mask revision.

Claims (6)

A buffer controller configured to sequentially activate and output the plurality of enable signals in response to the test signal; And And a buffer unit configured to vary a sink current according to the plurality of enable signals and determine an output level according to a difference between a reference voltage and a potential level of an input signal. The method of claim 1, The buffer control unit, A buffer enable signal generator for sequentially activating first and second enable signals for controlling the sink current amount of the buffer unit in response to a predetermined combination in response to the test signal and the reset signal; And a floating prevention signal generator configured to receive the first and second enable signals and generate a floating prevention signal for preventing the floating. The method of claim 2, The buffer enable signal generator, A first counter unit configured to output a first enable signal by performing a counter operation in response to the test signal and the reset signal, and And a second counter unit configured to generate the second enable signal by performing a counter operation in response to the reset signal and the first enable signal. The method of claim 2, The floating prevention signal generator, And the first and second enable signals are ORed together and output as a floating prevention signal. The method of claim 1, The buffer unit, A floating prevention unit for receiving a floating prevention signal and preventing floating of the buffer unit; A comparator comparing the reference voltage with the input signal and outputting a result; A plurality of sinks for sinking current in response to the plurality of enable signals, respectively; And a driving unit for driving and outputting the output signal of the comparing unit. The method of claim 5, wherein The plurality of sinks, And a plurality of switching elements connected between the comparison unit and a ground terminal.
KR1020070056962A 2007-06-11 2007-06-11 Input buffer circuit of semiconductor memory apparatus KR20080108867A (en)

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