KR20080105356A - Method for signal transmitting and apparatus for the same, method for signal receiving and apparatus for the same - Google Patents

Abstract

A method and an apparatus for transmitting and receiving a signal are provided to be easily converted into a suggested signal transceiving system by using an existing signal transceiving network and reduce costs. A bit stream distributing unit(131) distributes input bit data in at least one mapper. Mapping units(132,133) include at least one mapper which maps the distributed bit data on symbol data according to a corresponding mapping method and outputs the bit data. A symbol merging unit(135) arranges symbol data output from each mapper of the mapping unit to output one symbol data stream.

Description

Method for signal transmitting and apparatus for the same, Method for signal receiving and apparatus for the same

1 is a block diagram schematically showing an apparatus for transmitting a signal as an embodiment according to the present invention;

2 is a block diagram schematically showing a multi-mapper according to an embodiment of the present invention.

3 is a diagram illustrating a bit stream distribution scheme according to an embodiment of the present invention.

4 is a view schematically showing the position of an optimal constellation point as an embodiment according to the present invention.

5 is a flowchart illustrating a procedure of determining a point of an optical constellation according to an embodiment of the present invention.

6 is a view schematically showing an optical constellation having 16 points as an embodiment according to the present invention.

7 is a diagram schematically showing an optical constellation having 64 points as an embodiment according to the present invention.

8 is a diagram schematically showing an optical constellation having 256 points as an embodiment according to the present invention.

9 is a view schematically showing another optical constellation having 256 points as an embodiment according to the present invention.

10 is a block diagram schematically showing an apparatus for receiving a signal as an embodiment according to the present invention.

11 is a block diagram schematically illustrating a multiple demapper as an embodiment according to the present invention.

12 is a block diagram schematically illustrating a decision boundary of an optical constellation having 64 points;

FIG. 13A schematically illustrates a symbol demapper for demapping a received optical constellation symbol according to an embodiment of the present invention. FIG.

FIG. 13B is a diagram schematically illustrating another symbol demapper for demapping a received optical constellation symbol according to an embodiment of the present invention. FIG.

14 is a diagram schematically illustrating a process of demapping a received optical constellation symbol according to an embodiment of the present invention.

FIG. 15 is a diagram schematically illustrating a process of demapping a received optical constellation symbol in an edge region according to an embodiment of the present invention. FIG.

16 is a block diagram schematically illustrating an apparatus for transmitting a signal using multiple encodings according to an embodiment of the present invention.

17 is a block diagram schematically illustrating a multiple encoder as an embodiment according to the present invention.

18 is a block diagram schematically illustrating a signal receiving apparatus for receiving a multi-encoded signal according to an embodiment of the present invention.

19 is a block diagram schematically illustrating multiple decoders according to an embodiment of the present invention.

20 is a block diagram schematically illustrating an apparatus for transmitting a signal using multiple encoding and multiple mapping according to an embodiment of the present invention.

21 is a block diagram schematically illustrating a signal receiving apparatus for receiving a multi-encoded and multi-mapped signal according to an embodiment of the present invention.

FIG. 22 is a block diagram schematically illustrating another signal receiving apparatus for receiving multiple encodings and multiple mapped signals according to an embodiment of the present invention.

23 is a block diagram schematically illustrating a channel estimator in accordance with an embodiment of the present invention.

24 is a block diagram schematically illustrating an equalization unit according to an embodiment of the present invention.

25 is a block diagram schematically illustrating an apparatus for transmitting a signal according to a data symbol channel estimation method according to an embodiment of the present invention.

26 is a block diagram schematically illustrating an apparatus for receiving a signal according to a data symbol channel estimation method according to an embodiment of the present invention.

27 is a block diagram schematically showing another signal transmission apparatus of a data symbol channel estimation method according to an embodiment of the present invention.

28 is a block diagram schematically illustrating another signal receiving apparatus of a data symbol channel estimation method according to an embodiment of the present invention.

29 is a block diagram schematically showing another signal transmission apparatus according to an embodiment of the present invention.

30 is a block diagram schematically showing a forward error correction as an embodiment according to the present invention.

31 illustrates an interleaver for interleaving input data according to an embodiment of the present invention.

32 is a block diagram schematically showing a linear precoding unit according to an embodiment of the present invention.

33 (a) to 33 (c) illustrate a matrix of codes for distributing input data according to an embodiment of the present invention.

34 is a diagram illustrating a structure of a transmission frame according to an embodiment of the present invention.

35 is a block diagram schematically illustrating a case in which a signal transmission apparatus has a plurality of transmission paths according to an embodiment of the present invention.

36 (a) to 36 (e) illustrate an example of a 2x2 code matrix for distributing input symbols according to an embodiment of the present invention.

37 is a diagram illustrating an example of an interleaver according to an embodiment of the present invention.

38 is a diagram illustrating a specific example of the interleaver of FIG. 37 as an embodiment according to the present invention.

39 is a diagram illustrating an example of a multiple input / output encoding scheme according to an embodiment of the present invention.

40 (a) is a diagram showing the structure of a pilot symbol interval according to an embodiment of the present invention.

40 (b) illustrates another structure of a pilot symbol period according to an embodiment of the present invention.

41 is a block diagram schematically showing another signal receiving apparatus according to an embodiment of the present invention.

42 (a) is a block diagram schematically showing an example of a linear precoding decoder as an embodiment according to the present invention.

42 (b) is a block diagram schematically illustrating another example of a linear precoding decoder according to an embodiment of the present invention.

43 (a) to 43 (c) illustrate an example of a 2x2 code matrix for reconstructing distributed symbols according to an embodiment of the present invention.

44 is a block diagram schematically showing a forward error correction decoding unit according to an embodiment of the present invention.

45 is a block diagram schematically illustrating a case in which a signal receiving apparatus has a plurality of receiving paths according to an embodiment of the present invention.

46 illustrates an example of a multiple input / output decoding scheme according to an embodiment of the present invention.

47 is a view illustrating the specific example of FIG. 46 as an embodiment according to the present invention.

48 is a flowchart illustrating a signal transmission method according to an embodiment of the present invention.

49 is a flowchart illustrating a signal receiving method according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100: outer encoder 110: inner encoder

120: first interleaver 130: multiple mapper

140: linear precoding unit 150: second interleaver

160: frame forming unit 170: modulator

180: transmission unit

The present invention relates to a signal transmission and reception method and a signal transmission and reception apparatus, and more particularly, to a signal transmission and reception method and transmission and reception apparatus that can increase the data transmission rate.

The user has experienced superiority of HD (High Definition) video and digital sound due to the development of Digital Broadcasting technology, and improved environment in the future with the continuous development of compression algorithm and high performance of hardware. You will come across. The digital television (DTV) may receive the digital broadcast signal and provide various additional services in addition to video and audio to the user.

With the spread of digital broadcasting, demands for better services such as video and audio are increasing, and the size of data desired by the user and the number of broadcasting channels are gradually increasing.

However, it is difficult to cope with the increased data size and the number of broadcast channels using the conventional signal transmission and reception method. Therefore, there is an increasing demand for a signal transmission / reception technique that requires a higher bandwidth efficiency of a channel than a conventional signal transmission / reception scheme and requires less cost to construct a signal transmission / reception network.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a signal transmitting / receiving method and a transmitting / receiving apparatus capable of using an existing signal transmitting / receiving network network and increasing a data transmission rate.

A signal transmission apparatus according to the present invention for solving the above problems, the bit stream distribution unit for distributing the input bit data to at least one mapper, by mapping the distributed bit data to the symbol data according to the corresponding mapping scheme And a mapping unit including at least one mapper to output, and a symbol merging unit to align the symbol data output from each mapper of the mapping unit and output one symbol data string.

In another aspect, the apparatus for transmitting a signal includes a bit stream distribution unit for distributing input bit data to at least one encoder, and at least one encoder for encoding and outputting the distributed bit data according to a corresponding encoding method. And an data merging unit for arranging bit data output from each encoder and outputting one bit data string.

In another aspect, an apparatus for transmitting a signal according to the present invention includes a forward error correcting unit for encoding an input data so as to detect and correct an error, a first interleaver interleaving the error correction encoded data, and the interleaving unit. And a plurality of mappers configured to divide and distribute the divided data into symbol data according to at least one or more mapping methods, and to align the mapped symbol data to output a symbol data string.

In another aspect, an apparatus for transmitting a signal may include an outer encoder for encoding and outputting the input bit data so as to prevent a transmission error of the input bit data, and using the at least one encoding scheme. A multi-encoder for encoding and sorting the encoded bit data to output a bit data string, a first interleaver for interleaving the output bit data string, and mapping the interleaved data to symbol data Contains the symbol mapper to output.

In another aspect, an apparatus for transmitting a signal may include a forward error correcting unit configured to encode and detect an error on input data, a first interleaver interleaving the error correction encoded data, and the interleaving unit. A multi-mapper that maps the data to symbol data using at least one mapping method, aligns the mapped symbol data to output a symbol data string, and distributes the symbol data string in a frequency domain, And a fading coding unit for interleaving and outputting the data, and a frame forming unit for forming the fading coded symbol data output as frame data according to a transmission scheme.

The signal transmission method according to the present invention comprises the steps of: distributing input bit data to at least one mapper, mapping and outputting bit data distributed to each mapper to symbol data according to a corresponding mapping method, and the mapping And sorting each symbol data to output one symbol data string.

In another aspect, a signal transmission method according to the present invention includes distributing input bit data to at least one encoder, encoding and outputting bit data distributed to each encoder according to a corresponding encoding method, and outputting the output bit data. Sorting each bit data and outputting one bit data string.

In another aspect, a signal transmission method according to the present invention includes a forward error correction step of encoding an input data so that an error can be detected and corrected, interleaving the error correction encoded data, and the interleaved data. Mapping the symbol data to symbol data using at least one mapping scheme, and aligning the mapped symbol data to output a symbol data string.

In another aspect, the signal transmission method according to the present invention includes encoding and outputting the input bit data so as to prevent a transmission error of the input bit data, and encoding the output data using at least one encoding scheme. And arranging the encoded bit data to output a bit data string, interleaving the output bit data string, and mapping and outputting the interleaved data to symbol data. Include.

In another aspect, the signal transmission method according to the present invention includes encoding and outputting the input bit data so as to prevent a transmission error of the input bit data, and encoding the output data using at least one encoding scheme. And arranging the encoded bit data to output a bit data string, interleaving the output bit data string, and mapping the interleaved data to symbol data using at least one mapping method. (mapping) and sorting the mapped symbol data to output a symbol data string.

In another aspect, a signal transmission method according to the present invention includes a forward error correction step of encoding an input data so that an error can be detected and corrected, interleaving the error correction encoded data, and interleaving the interleaved data. Mapping at least one mapping method to symbol data, arranging the mapped symbol data to output a symbol data string, distributing the symbol data string in a frequency domain, and distributing the distributed data. Interleaving and outputting the result, and forming the faded coded symbol data into frame data according to a transmission scheme.

The apparatus for receiving a signal according to the present invention includes at least a symbol distribution unit for distributing input symbol data to at least one demapper, and a demapper for demapping and distributing the distributed symbol data into bit data according to a corresponding demapping scheme. And a bit stream recovery unit for outputting one bit data string by aligning bit data output from each demapper of the de-mapping unit.

In another aspect, the apparatus for receiving a signal includes a bit stream distributor for distributing input bit data to at least one decoder, and at least one decoder for decoding and outputting the distributed bit data according to a corresponding decoding scheme. And a bit stream reconstruction unit for arranging bit data output from each decoder and outputting one bit data string.

In another aspect, an apparatus for receiving a signal according to the present invention divides and distributes input symbol data to demap bit data according to at least one or more demapping schemes, and sorts the demapped bit data to output a bit data string. And a multiple demapper, a first deinterleaver for deinterleaving the output bit data stream to restore order, and a forward error correction decoding unit for detecting and correcting errors by decoding the deinterleaved data.

In another aspect, an apparatus for receiving a signal may include: a symbol demapper for demapping input symbol data into bit data and outputting the first signal; a first deinterleaver for deinterleaving the output bit data string and restoring an order; A multiple decoder for distributing and decoding deinterleaved data to at least one decoding scheme, aligning the decoded bit data to output a bit data string, and re-decoding the bit data output from the multiple decoder according to a corresponding decoding scheme An outer decoder for outputting.

In another aspect, an apparatus for receiving a signal may include: a frame parser configured to extract symbol data and a pilot included in a pilot insertion position of received frame data, and restore symbol data included in the frame data; A channel is estimated using the pilot extracted at the pilot insertion position, and the channel is estimated using the equalized value of the symbol data extracted at the pilot insertion position and the determined value of the symbol data extracted at the pilot insertion position. An estimator, an equalizer for equalizing the reconstructed symbol data using the channel information estimated by the channel estimator, and dividing and equalizing the equalized symbol data to determine a symbol value according to at least one demapping scheme, The bit data corresponding to each of the determined values is calculated to generate one bit data string. Contains multiple demappers for output.

In another aspect, an apparatus for receiving a signal may include a frame parsing unit for parsing received frame data, restoring and outputting symbol data, and using an equalized value of the symbol data and a determined value of the symbol data. A channel estimator for estimating a channel, an equalizer for equalizing the reconstructed symbol data using the channel information estimated by the channel estimator, and a symbol value of the equalized symbol data according to a corresponding demapping scheme And a symbol demapper for calculating and outputting bit data corresponding to each of the determined values.

In accordance with another aspect of the present invention, there is provided a signal receiving method comprising: distributing input symbol data to at least one demapper, demapping the distributed symbol data into bit data according to a corresponding demapping scheme, and outputting each of the de-maps. And sorting the mapped bit data to output one bit data string.

In another aspect, a signal receiving method according to the present invention includes distributing input bit data to at least one or more decoders, decoding and outputting the distributed bit data according to a corresponding decoding scheme, and outputting each of the decoded and output signals. And sorting the bit data to output one bit data string.

In another aspect, the signal receiving method according to the present invention divides and divides input symbol data into bit data according to at least one or more demapping schemes, and arranges one bit data string by aligning the demapped bit data. Outputting, deinterleaving the output bit data sequence to restore order, and decoding the deinterleaved data to detect and correct errors.

In another aspect, a signal receiving method according to the present invention includes: demapping input symbol data into bit data and outputting the data, deinterleaving the output bit data string to restore an order, and dividing the deinterleaved data. Distributing and decoding according to at least one decoding scheme, arranging the decoded bit data to output one bit data string, and decoding and outputting the output bit data string again according to a corresponding decoding scheme. Include.

In another aspect, the method for receiving a signal according to the present invention includes extracting symbol data and pilot included in a pilot insertion position of received frame data, restoring symbol data included in the frame data, generated pilot and the pilot Estimating a channel using the pilot extracted at the insertion position and estimating the channel using the equalized value of the symbol data extracted at the pilot insertion position and a determined value of the symbol data extracted at the pilot insertion position, Equalizing the reconstructed symbol data by using estimated channel information, and dividing and distributing the equalized symbol data to determine a symbol value according to at least one demapping scheme, and bit data corresponding to each of the determined values Calculating and outputting one bit data string.

In another aspect, a signal receiving method according to the present invention includes parsing received frame data, restoring and outputting symbol data, and using a channel value by using an equalized value of the symbol data and a determined value of the symbol data. Estimating a symbol, equalizing the reconstructed symbol data using the channel information estimated by the channel estimator, and determining a symbol value of the equalized symbol data according to a corresponding demapping scheme, and determining the determined values. Computing and outputting the bit data corresponding to the.

In another aspect, a signal receiving method according to the present invention includes parsing received frame data, restoring and outputting symbol data, and transmitting each subcarrier using an equalized value of the symbol data. Estimating a channel state for a channel, estimating a channel using an equalized value of symbol data received as a channel having a good channel state among the channels estimated in the channel state estimating step and a determination value of the symbol data; Equalizing the reconstructed symbol data using the channel information estimated by the channel estimator, and determining a symbol value of the equalized symbol data according to a corresponding demapping scheme, and bit data corresponding to each determined value. Comprising the step of outputting.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

In addition, the terms used in the present invention was selected as a general term widely used as possible now, but in certain cases, the term is arbitrarily selected by the applicant, in which case the meaning is described in detail in the corresponding description of the invention, It is to be clear that the present invention is to be understood as the meaning of terms rather than names.

Operation of the signal transmission and reception method and the signal transmission and reception device according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically showing a signal transmission apparatus according to an embodiment according to the present invention. The signal transmission apparatus of FIG. 1 may be a signal transmission system for transmitting video data such as a broadcast signal. For example, it may be a signal transmission system according to a digital video broadcasting (DVB) system. An embodiment of a signal transmission system according to the present invention will be described with reference to FIG. 1.

1 illustrates an outer encoder 100, an inner encoder 110, a first interleaver 120, a multiple mapper 130, and a linear precoding unit ( 140, a second interleaver 150, a frame builder 160, a modulator 170, and a transmitter 180.

The outer encoder 100 and the inner encoder 110 encode and output the input signal, respectively, so that an error occurring in the transmitted data can be detected by the receiver and the error can be corrected. That is, the outer encoder 100 and the inner encoder 110 may be regarded as forward error correcting (FEC).

The outer encoder 100 encodes input data so as to prevent a transmission error on an input signal, that is, to improve transmission performance, and the inner encoder 110 transmits a signal to be transmitted in preparation for an error in the transmission signal. Encode again. The type of each encoder may vary according to a coding scheme used in a corresponding signal transmission system.

The first interleaver 120 distributes the data sequence to a random position so as to be robust to a burst error that may occur when the signal output from the inner encoder 110 is transmitted. For example, a block interleaving method or a convolution interleaving method may be used for the first interleaver 120. The type of the first interleaver 120 may vary depending on the method used in the corresponding signal transmission system.

The multiple mapper 130 maps the data interleaved in the first interleaver 120 into symbols according to a transmission scheme. The multiple mapper 130 mixes a plurality of mapping schemes to map the input data into symbol data. Quadrature Amplitude Modulation (QAM), Quadrature Phase Shift Keying (QPSK), Amplitude Phase Shift Keying (APSK), Pulse Amplitude Modulation (PAM), and Optimal Constellation may be used as the mapping scheme.

Using the multiple mapping scheme as described above, a signal to noise ratio (SNR) gain can be obtained from a method of mapping to a small constellation size, and a rate gain ( capacity gain) can be obtained. Therefore, the gain between the SNR and the data rate can be adjusted by adjusting the mixing ratio of the mapping scheme, and the transmission efficiency can be improved.

2 is a block diagram schematically illustrating a multiple mapper according to an embodiment of the present invention. The multiple mapper 130 may include a bit stream distributor 131, a first mapper 132, a second mapper 133,. , An N-th mapper 134, and a symbol interleaver 135.

The bit stream distributor 131 distributes the input bit data to a plurality of mappers. The bit stream distributor 131 distributes the required number of bit data to map to a symbol according to the mapping method of each mapper.

3 is a diagram illustrating a bit stream distribution scheme according to an embodiment of the present invention. That is, the bit stream distribution method represents an example of a method of distributing a bit stream in the bit stream distribution unit 131.

In the bit stream distribution method of FIG. 3, the input bit data is stored in a matrix-type storage space in a predetermined pattern, and the data is read and output in a pattern different from the storage pattern. In this case, the effect of a kind of virtual interleaver can be obtained.

For convenience of explanation, it is assumed that the number of mappers for distributing input bit data is two. For example, when the length of one block input to the bit stream distribution unit 131 is M × N bits, the blocks are divided into M equal parts and filled in the storage space from one row to one row. Data is stored starting from row 1 of column 1 up to row M, and when the column 1 is filled up, data is stored starting from row 1 of the next column (column 2) up to row M. Data can be stored up to M rows of N columns in the above order. In this case, the MSB (Most Significant Bit) position of the storage space is at the top left, and the LSB (Least Significant Bit) position is at the bottom right.

In the two mappers, when the bit ratio of the symbols of the first and second mappers is M-R: M, the data stored in the storage space is divided into M-R rows and R rows, respectively. The divided bit data is output in a row manner. In other words, starting from the data of 1 row and 1 column, reading the data of the row up to 1 row N column, and reading all the data of the row, starting from the 1 column of the next lower row (row 2) to the right direction Read and output the data. In the same order as above, data is read to M-R line and output to the first mapper. The data of the remaining R rows is also read in the row direction and output to the second mapper.

In the above embodiment, the size of the block, the storage pattern, the read pattern, and the like are one embodiment, which may vary depending on the embodiment. For example, it is also possible to distribute the input bit data to each mapper in the input order.

The bit data distributed by the bit stream distributor 131 is output to each mapper (first mapper 132 to N-th mapper 134). The first mapper 132 to the N-th mapper 134 may be viewed as a mapping unit that maps the input bit data into symbol data. Each mapper maps the input bit data into symbol data according to a corresponding mapping scheme. QAM, QPSK, APSK, PAM, optimal constellation, etc. may be used as the mapping scheme.

Each of the mappers (the first mapper 132 to the N-th mapper 134) may use the same type of mapping scheme, and may vary the number of bit data included in one symbol, and different types of mapping for each mapper. You can also use the method. For example, while the first mapper 132 to the N-th mapper 134 all use the QAM method, the first mapper 132 is 16QAM, the second mapper 133 is 64QAM, and the N-th mapper 134 is 256QAM. Symbol mapping. Alternatively, the first mapper 132 may map in a QAM manner, and the N-th mapper 134 may map in an optical constellation manner. The example may vary depending on the embodiment.

For convenience of description, each of the mappers (first mapper 132 to N-th mapper 134) uses an optimal constellation method while varying the number of bit data included in one symbol. It is assumed to be described. For example, the first mapper 132 may use a 16-point optical constellation, the second mapper 133 may use a 64-point optical constellation, and the N-th mapper 134 may use a 256-point optical constellation.

4 is a diagram schematically showing the position of an optimal constellation point according to an embodiment of the present invention. The point can be used for optical constellation mapping. The number of constellation points represents power.

의 정수배가 될 수 있다.The x-axis value of the optical constellation points may be odd (1, 3, 5, ...) or even (2, 4, 6, ...), the y-axis value

It can be an integer multiple of.

,

,

의 값을 가지며, 파워는 각각 3, 27, 75, … 이다. 파워가 13인 포인트의 경우, x축 값은 1이고, y축 값은

이다. 파워가 7인 포인트의 경우, x축 값은 2이고, y축 값은

이다. For example, for points located on the x-axis, 1, 3, 5,... Power values are 1, 9, 25,... to be. for points on the y axis

,

,

And the powers are 3, 27, 75,... to be. For points with a power of 13, the x-axis value is 1 and the y-axis value is

to be. For points with power of 7, the x-axis value is 2 and the y-axis value is

to be.

As described above, by placing the point as close to the circle as possible and as far as possible from the DC position, the transmission power can be used efficiently.

In addition to the positions of the points shown in FIG. 4, a position obtained by symmetrical with respect to the x-axis, y-axis, or origin may be used. Alternatively, the positions obtained by rotating the positions of the points at arbitrary angles about the origin may be used. This may vary depending on implementation.

5 is a flowchart illustrating a procedure of determining an optical constellation point according to an embodiment of the present invention. The required number of optical constellation points is obtained among the constellation points as shown in FIG. 4.

First, a constellation point having the smallest power among constellation points as shown in FIG. 4 is selected (S500). In operation S510, the number of the selected constellation points and the number of necessary constellation points are compared. If the selected number of constellation points is smaller, step S500 is performed again to select constellation points having the smallest power among the unselected points. If the number of the selected constellation points is larger, the constellation points are removed in order of increasing power by the number of points exceeded (S520). Through the above process, a desired number of constellation points can be obtained, and the input data can be mapped to symbol data using the obtained constellation points.

6 to 9 are schematic diagrams showing an optical constellation having a point selected according to the above-described exemplary embodiment according to the present invention. That is, FIGS. 6 to 9 schematically show an optical constellation having 16 points, 64 points, 256 points, and 256 points, respectively. However, FIG. 8 is a case of another embodiment having a position different from that of the constellation point described with reference to FIG. 4, and has a constellation point close to the DC position.

As described above, in addition to the positions of the points of FIGS. 6 to 9, a position obtained by symmetry of the points with respect to the x-axis, the y-axis, or the origin may be used. Alternatively, the positions obtained by rotating the positions of the points at arbitrary angles about the origin may be used. This may vary depending on implementation.

Each mapper (the first mapper 132 to the N-th mapper 134) performs symbol symbol mapping on the input data according to the optical constellation mapping method having a predetermined number of points as described above.

The symbol interleaver 135 interleaves the symbol data output from the respective mappers, sorts them into one symbol string, and outputs the result. Bit-reversed addressing, in which the block interleaving method, the convolutional interleaving method, or the symbols are designated as one block, and then the addresses corresponding to the order of the blocks are output in the order of bit inversion. ) May be used for interleaving. Alternatively, the symbol data output from the respective mappers may be simply arranged in a predetermined order and output without interleaving the symbols. This may vary depending on implementation.

The linear precoding unit 140 distributes the input symbol data to a plurality of output symbol data, thereby reducing the probability that all information is lost due to fading when undergoing a frequency selective fading channel.

The second interleaver 150 interleaves the symbol data output from the linear precoding unit 140 again so that the symbol data does not experience the same frequency selective fading. A block interleaving method or a convolutional interleaving method may be used for the second interleaver 150.

The frame forming unit 160 forms a frame by inserting a pilot signal in a data section so that the interleaved signal can be modulated by an orthogonal frequency division multiplex (OFDM) scheme.

The modulator 170 inserts and modulates a guard interval so that the data output from the frame former 160 can be carried on subcarriers of OFDM. The transmitter 180 converts a digital signal having a guard period and a data period output from the modulator 170 into an analog signal and transmits the signal.

10 is a block diagram schematically illustrating an apparatus for receiving a signal according to an embodiment of the present invention. The embodiment of FIG. 10 may be included in a DVB receiving apparatus.

10, the receiver 1000, the synchronizer 1010, the demodulator 1020, the frame parsing unit 1030, the first deinterleaver 1040, and the linear free unit are illustrated in FIG. 10. A coding decoder 1050, a multiple demapper 1060, a second deinterleaver 1070, an inner decoder 1080, and an outer decoder 1090 are included.

The receiver 1000 down-converts the frequency band of the received RF signal and converts the frequency band into a digital signal. The synchronizer 1010 obtains and outputs a synchronization between a frequency domain and a time domain of the received signal output from the receiver 1000. The synchronization unit 1010 may use an offset result of the frequency domain of the data output by the demodulator 1020 to obtain synchronization of the frequency domain signal.

The demodulator 1020 demodulates the received data output from the synchronizer 1010 and removes a guard interval. To this end, the demodulator 1020 converts the received data into the frequency domain, and decodes the data values distributed in the subcarriers into values assigned to each subcarrier. The frame parser 1030 may output symbol data of a data symbol period excluding a pilot symbol according to the frame structure of the signal demodulated by the demodulator 1020.

The first deinterleaver 1040 performs de-interleaving on the data string output from the frame parser 1030 to restore the data in the order before interleaving. The first deinterleaver 1040 is deinterleaved according to a method corresponding to the method interleaved by the second interleaver 150 of FIG. 1 to restore the order of data columns.

The linear precoding decoder 1050 performs a reverse process of distributing the data in the signal transmission apparatus, and restores original data dispersed in the data input to the linear precoding decoder 1050.

The multiple demapper 1060 may reconstruct the symbol data reconstructed by the linear precoding decoder 1050 into a bit string. The demapping scheme of the multiple demapper 1060 uses a scheme corresponding to the mapping scheme used by the multiple mapper 130 of the transmitting apparatus as shown in FIG. 1. As described above, it is assumed that the multiple mapper 130 of FIG. 1 performs multiple mapping to symbol data having a different number of bits according to the optical constellation mapping scheme.

11 is a block diagram schematically illustrating a multiple demapper according to an embodiment of the present invention. The multiple demapper 1060 includes a symbol deinterleaver 161, a first demapper 162, a second demapper 163,. , N-th demapper 164, and bit stream reconstruction unit 165.

The symbol deinterleaver 161 deinterleaves the input symbol data to restore the original symbol data order. The deinterleaving method of the deinterleaver 161 uses a method corresponding to a method in which the symbol interleaver 135 interleaves in the multiple mapper 130 of FIG. 2. The symbol deinterleaver 161 transmits the deinterleaved symbol data to a demapper corresponding to the mapped scheme.

Each demapper (first demapper 162 through N-th demapper 164) converts the received symbol data into bit data according to a corresponding demapping scheme. The first demapper 162 to N-th demapper 164 may be regarded as a demapping unit for demapping input symbol data into bit data. The demapping schemes of the first demapper 162 to the Nth demapper 164 correspond to the mapping methods of the first mapper 132 to the N-th mapper 134 of FIG. 2, respectively.

12 is a block diagram schematically illustrating a decision boundary of an optical constellation having 64 points. When one of the mappers (first mapper 132 to N-th mapper 134) of FIG. 2 is symbol-mapped according to a 64-point optimal constellation scheme, the mapper of the receiving side corresponding to the mapper The demapper demaps the received symbol data using the decision boundary shown in FIG. 12. In the case of the optical constellation mapping scheme, the constellation has a honeycomb constellation in order to efficiently use transmission power, and the demapper has a hexagonal crystal boundary for each symbol as shown in FIG. However, the symbol corresponding to the point located at the edge has a crystal boundary of one side that is not hexagonal.

If it is determined that the input symbol data is located within a specific hexagon among the decision boundaries as shown in FIG. 12, the demapper demaps the input symbol data into a symbol of a point corresponding to the specific hexagon.

FIG. 13A is a diagram schematically illustrating a symbol demapper for demapping a received optical constellation symbol according to an embodiment of the present invention, and FIG. 13B is a diagram illustrating a received optical constellation symbol as an embodiment according to the present invention. FIG. Is a diagram schematically illustrating another symbol demapper to be mapped.

The demapper may perform symbol demapping using the entire crystal boundary of the optical property as shown in FIG. 12 at once, or may perform symbol demapping using a rectangular crystal boundary as in the demappers of FIGS. 13A and 13B. have.

The demapper of FIG. 13A includes a first determining part 3000, a second determining part 1302, a first rotating part 1304, a third determining part 1306, a fourth determining part 1308, and a second rotating part ( 1310, a fifth decision unit 1312, a sixth decision unit 1314, and a bit converter 1316.

When the symbol data is input to the demapper, the first determination unit 1300 determines that the input symbol data has the rectangular shape by using the rectangular crystal boundary area using two faces facing each of the hexagonal crystal boundary areas. Determine if it is located in the boundary area. The second determination unit 1302 determines whether the input symbol data is located in a constellation edge region, that is, an edge region that does not form a shape at the entire crystal boundary as shown in FIG. 12. The second determination unit 1302 determines whether the second determination unit 1302 is located in a crystal boundary region divided by a solid line among the edge regions. The first determination unit 1300 and the second determination unit 1302 are determination units that determine the position of the input symbol data by using a non-rotating decision boundary.

The first rotating unit 1304 rotates the entire crystal boundary used by the first determining unit 1300 and the second determining unit 1302 by 60 degrees. Data output from the first rotating unit 1304 is input to the third determining unit 1306. The third crystal part 1306 uses the rectangular crystal boundary region using two faces facing each of the hexagonal crystal boundary regions among the entire crystal boundary regions rotated by 60 degrees. Determine if it is located in the boundary area of the decision. The fourth decision unit 1308 determines whether the input symbol data is located in the constellation edge region. The fourth determination unit 1308 determines whether the fourth determination unit 1308 is located in a crystal boundary region divided by a dashed-dotted line among the edge regions. The third determination unit 1306 and the fourth determination unit 1308 are determination units that determine the position of the input symbol data by using the determination boundary rotated once, that is, rotated by 60 degrees.

The second rotating unit 1310 rotates the entire crystal boundary used by the third determining unit 1306 and the fourth determining unit 1308 again by 60 degrees. Data output from the second rotating unit 1310 is input to the fifth determining unit 1312. The fifth crystal part 1312 uses a rectangular crystal boundary using two faces facing each other of the hexagonal crystal boundary regions among the entire crystal boundary regions rotated by 60 degrees again, so that the input symbol data has a rectangular shape. Determine if you are on the decision boundary. The sixth decision unit 1314 determines whether the input symbol data is located in the constellation edge region. The sixth decision unit 1314 determines whether the sixth decision unit 1314 is located in a crystal boundary region divided by a dotted line among the edge regions. The fifth determination unit 1312 and the sixth determination unit 1314 are determination units that determine the position of the input symbol data by using the determination boundary rotated twice, that is, rotated 120 degrees compared with the original determination boundary. .

When the second determination unit 1302, the fourth determination unit 1308, and the sixth determination unit 1314 determine the constellation edge region, the determination of the position parallel to the x-axis and the y-axis is performed by saturation ( saturation) technique, and the determination of the position of the oblique form is determined by using the linear equation corresponding to the oblique line.

The bit converter 1316 converts the information determined by the determination units, that is, the input symbol data into the bit data corresponding to the determined symbol value by using the value determined as the symbol of the corresponding point.

As described above, both the two rotations and the six decision processes may be performed. If a symbol of a point corresponding to the received symbol data is determined by a specific decision among the six determinations, no further rotation or determination is performed. The decision information may be directly output to the bit converter 1016 and converted into bit data. This may vary depending on implementation.

FIG. 13B is a diagram schematically illustrating another symbol demapper for demapping a received optical constellation symbol according to an embodiment of the present invention. The symbol demapper of FIG. 13B is an embodiment of a recursive decoding method using feedback.

The symbol demapper of FIG. 13B includes a buffer 1320, a selector 1322, a first determiner 1324, a second determiner 1326, a rotater 1328, and a bit converter 1330. .

The buffer 1320 temporarily stores and outputs the input symbol data. The selector 1322 receives the symbol data output from the buffer 1320 and the symbol data output from the rotation unit 1328, and outputs one symbol data. The selector 1322 outputs symbol data fed back from the rotating unit 1328 when iterative decoding is performed, and outputs symbol data input from the buffer 1320 when a decision process is performed on new symbol data. do.

The first determination unit 1324 determines whether the input symbol data is located in the rectangular crystal boundary region by using a rectangular crystal boundary region using two faces facing each other in the hexagonal crystal boundary region. The second determination unit 1326 determines whether the input symbol data is located in a constellation edge region, that is, an edge region that does not form a shape at the entire crystal boundary as shown in FIG. 12. The second determination unit 1326 determines whether the second determination unit 1326 is located in a crystal boundary region divided by a solid line (0 rotation), a dashed chain (1 rotation), and a dotted line (2 rotation), respectively. The rotating unit 1328 rotates the entire crystal boundary used by the first and second determination units 1324 and 1326 by 60 degrees.

The bit converter 1330 converts the information determined by the determiner, that is, the input symbol data into the bit data corresponding to the determined symbol value by using a value determined as a symbol of a corresponding point.

The symbol demapper of 13b may perform both two rotations and six determinations. The symbol demapper of 13b corresponds to the input symbol data in the first determination unit 1324 and the second determination unit 1326 during the iterative decoding process. When the symbol of the point to be determined is determined, the determination information may be immediately output to the bit converter 1330 and converted into bit data. This may vary depending on implementation.

FIG. 14 is a diagram schematically illustrating a process of demapping a received optical constellation symbol according to an embodiment of the present invention, and FIG. 15 is a diagram illustrating received optical of an edge region as an embodiment according to the present invention. A diagram schematically illustrating a process of demapping constellation symbols.

14 is a view showing four hexagonal crystal boundary regions among the entire crystal boundaries. The figure determines whether symbol data is located in the rectangular crystal boundary region using the rectangular crystal boundary region using two surfaces facing each other in the hexagonal crystal boundary region among the crystal portions of FIG. 13A or 13B. The decision process of the decision part is shown.

First, in the first non-rotating crystal boundary form, the input symbol data is positioned in the rectangular crystal boundary region using a rectangular crystal boundary region using two opposite sides of the hexagonal crystal boundary region. Determine. After the determination is completed, the entire crystal boundary is rotated by 60 degrees, and the input symbol data is converted into the rectangular crystal boundary by using a rectangular crystal boundary region using two opposite sides of each hexagonal crystal boundary region. Determine if it is included in the zone. Then, the entire crystal boundary is rotated by 60 degrees again to determine whether the input symbol data is included in the rectangular crystal boundary region by using the rectangular crystal boundary using two opposite sides of the hexagonal crystal boundary region. do. In FIG. 14, the second crystal boundary shape and the third crystal boundary shape superimpose the regions undergoing the crystallization process while the rotation is performed.

Through two rotations as described above, the rectangular crystal boundary region may cover all regions inside the hexagon. Therefore, for each of the hexagonal crystal boundary regions, it is possible to demap to a symbol corresponding to a point having the hexagonal crystal boundary region.

According to an embodiment, if it is recognized that the input symbol data is located in the crystal boundary region of the rectangular shape, the determination process may be completed without performing the remaining rotation and determination. In the above description, although a rectangular crystal boundary region using two opposite sides of a hexagon is used, an area using two opposite sides other than the left and right sides, for example, an obliquely inclined rectangular boundary region, is used. Can also be used.

15 is a diagram illustrating an entire decision boundary of the 64-point optical constellation mapping method. FIG. 15 illustrates a determination process of a decision unit for making a determination as to whether the symbol data input among the determination units of FIGS. 13A and 13B is located in a constellation edge region, that is, an edge region that does not form a figure.

First, in the first non-rotating decision boundary form, it is determined whether the input symbol data is located in a region separated by a solid line among the constellation boundary regions. After the determination is completed, the entire crystal boundary is rotated by 60 degrees to determine whether it is located in a region separated by a dashed line among constellation boundary regions. Then, the entire crystal boundary is rotated 60 degrees again to determine whether it is located in the area divided by a dotted line.

According to an embodiment, the order of the area divided by the solid line, the area divided by the dashed-dotted line, and the area divided by the dotted line may be changed. For example, after the determination of the area divided by the dotted line in the first crystal boundary form of FIG. 15, the area divided by the solid line (one rotation) and the dashed-dotted line (two rotation) may be determined according to the rotation. have.

The second deinterleaver 1070 performs an inverse process of interleaving on the bit data string demapped by the multiple demapper 1060. The second deinterleaver 1070 performs deinterleaving corresponding to the first interleaver 120 of FIG. 1. An inner decoder 1080 may correct the error included in the data by decoding the deinterleaved data. The outer decoder 1090 performs an error correction decoding process on the bit data decoded by the inner decoder 1080 and outputs the same. The inner decoder 1080 and the outer decoder 1090 decode data according to decoding methods corresponding to the inner encoder 110 and the outer encoder 100 of FIG. 1, respectively.

16 is a block diagram schematically illustrating an apparatus for transmitting a signal using multiple encodings according to an embodiment of the present invention. The embodiment of FIG. 16 includes an outer encoder 1600, a multiple encoder 1610, a first interleaver 1620, a trellis code modulator 1630, a linear precoding unit 1640, The second interleaver 1650, a frame builder 1660, a modulator 1670, and a transmitter 1680 are included.

The outer encoder 1600 and the multiple encoder 1610 encode and output input signals, respectively, so that an error occurring in the transmitted data can be detected by the receiver and the error can be corrected. That is, the outer encoder 1600 and the multiple encoder 1610 may be regarded as forward error correcting (FEC).

The outer encoder 1600 encodes input data to improve transmission performance for the input signal. The type of encoder may vary depending on the coding scheme used in the corresponding signal transmission system.

The multiple encoder 1610 re-encodes the data encoded by the outer encoder 1600 in preparation for an error that may occur in the transmission process. The multiple encoder 1610 encodes the input data by mixing a plurality of encoding schemes. For example, convolutional coding, Reed-Solomon (RS) coding, low density parity check (LDPC) coding, turbo coding, and the like may be used as the encoding scheme.

By using the multiple encoding scheme as described above, a signal to noise ratio (SNR) gain can be obtained from an encoding scheme having a low code rate, and a transmission rate can be obtained from an encoding scheme having a high code rate. Gain can be obtained. Therefore, by adjusting the mixing ratio of the encoding scheme, it is possible to adjust the gain between the SNR and the transmission rate, and increase the transmission efficiency.

17 is a block diagram schematically illustrating a multiple encoder according to an embodiment of the present invention. The multiple encoder 1610 includes a bit stream distribution unit 1611, a first encoder 1612, a second encoder 1613,... And an N-th encoder 1614 and a bit stream recovery unit 1615.

The bit stream distributor 1611 distributes the input bit data to a plurality of encoders. The bit stream distributor 1611 distributes the required number of bit data according to the encoding scheme of each encoder. The bit stream distribution unit 1611 may distribute the input bit data according to the bit stream distribution scheme as shown in FIG. 3, or may distribute the input bit data to each mapper in the order in which the input bit data is input. Such a distribution scheme may vary depending on implementation.

The bit data distributed by the bit stream distribution unit 1611 is output to each encoder (the first encoder 1612 to the Nth encoder 1614). The first encoder 1612 to the Nth encoder 1614 may be regarded as an encoding unit that encodes and outputs the input bit data. Each encoder encodes input bit data according to the corresponding encoding scheme. For example, convolutional coding, Reed-Solomon (RS) coding, low density parity check (LDPC) coding, turbo coding, and the like may be used as the encoding scheme.

Each of the encoders (the first encoder 1612 to the Nth encoder 1614) may use the same type of encoding scheme, and may have a different code rate, or may use a different type of encoding scheme for each encoder. For example, while the first encoder 1612 to the Nth encoder 1614 use the LDPC method, the code rate of each mapper can be changed. Alternatively, the first encoder 1612 may encode the LDPC method, and the N-th mapper 1614 may encode the turbo coding method. The example may vary depending on the embodiment.

The bit stream recovery unit 1615 receives the bit data output from each of the encoders and recovers the bit data into one bit data string. The bit stream recovery unit 1615 may restore the inverse of the distribution method of the bit stream distribution unit 1615, or may restore the data to one bit data string according to another predetermined rule. This may vary depending on implementations, and a virtual interleaving effect may be obtained according to the restoration scheme.

The first interleaver 1620 distributes the data sequence to a random position so as to be robust to a burst error that may occur when a signal output from the multiple encoder 1610 is transmitted. For example, a block interleaving method or a convolution interleaving method may be used for the first interleaver 1620. The type of the first interleaver 1620 may vary depending on the method used in the corresponding signal transmission system.

The trellis code modulator 1630 maps the bit data received from the first interleaver 1620 into coded symbol data. In the case of using a general symbol mapper instead of the trellis code modulator 1630, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), amplitude phase shift keying (APSK), pulse amplitude modulation (PAM), and the like. You can use the same mapping to map bit data into symbols.

The linear precoding unit 1640 distributes the input symbol data into a plurality of output symbol data to reduce the probability that all information is lost due to fading when subjected to a frequency selective fading channel.

The second interleaver 1650 interleaves the symbol data output from the linear precoding unit 1640 again so that the symbol data does not experience the same frequency selective fading. The second interleaver 1650 may use a block interleaving method or a convolutional interleaving method.

The frame forming unit 1660 forms a frame by inserting a pilot in a data section so that the interleaved signal can be modulated by an orthogonal frequency division multiplex (OFDM) scheme.

The modulator 1670 inserts and modulates a guard interval so that the data output from the frame forming unit 1660 can be carried on subcarriers of OFDM. The transmitter 1680 converts a digital signal having a guard interval and a data interval output from the modulator 1670 into an analog signal and transmits the signal.

18 is a block diagram schematically illustrating a signal receiving apparatus for receiving a multi-encoded signal according to an embodiment of the present invention. The embodiment of FIG. 18 may be included in a DVB receiving apparatus.

An embodiment according to the present invention of FIG. 18 includes a receiver 1800, a synchronizer 1810, a demodulator 1820, a frame parsing unit 1830, a first deinterleaver 1840, and a linear free. A coding decoder 1850, a trellis code decoder 1860, a second deinterleaver 1870, a multiple decoder 1880, and an outer decoder 1890 are included.

18 is the same as the receiver described with reference to FIG. 10. Hereinafter, different parts from FIG. 10 will be described.

The trellis code decoder 1860 may restore the symbol data recovered by the linear precoding decoder 1850 into a bit string. The trellis code decoder 1860 demaps symbol data using a method corresponding to the method mapped by the trellis code modulator 1630 of FIG. 16.

The multiple decoder 1880 receives the deinterleaved bit data from the second deinterleaver 1870 and decodes the bits according to a method encoded by the transmitter.

19 is a block diagram schematically illustrating multiple decoders according to an embodiment of the present invention. The multiple decoder 1880 includes a bit stream distributor 1188, a first decoder 1882, a second decoder 1883,. , An N-th decoder 1884, and a bit stream reconstruction unit 185.

The bit stream distributor 188 distributes the input bit data to a plurality of decoders. The bit stream distributor 188 distributes bit data according to a method corresponding to a method in which the bit stream recovery unit 1615 merges into one bit data string in the multiple encoder of FIG. 17. That is, the bit stream recovery unit 1615 of the multiple encoder receives the bit data and distributes the bit data as opposed to the method of forming the bit data string.

The bit data distributed by the bit stream distributor 188 is output to each decoder (first decoder 1882 to Nth decoder 1884). The first decoder 1882 to the Nth decoder 1884 may be viewed as a decoding unit for decoding and outputting input bit data. Each decoder encodes the input bit data according to the corresponding decoding scheme. The decoding method uses a method corresponding to the method encoded by the multiple encoder of FIG. 17.

The bit stream recovery unit 1885 receives the bit data output from the respective decoders, and recovers the bit data into one bit data string. The bit stream recovery unit 1885 restores the order in the reverse of the manner in which the bit data distribution unit 1611 distributes the bit data.

The outer decoder 1890 performs an error correction decoding process on the bit data decoded by the multiple decoder 1880 and outputs the same. That is, the multiple decoder 1880 and the outer decoder 1890 decode data according to decoding methods corresponding to the multiple encoder 1610 and the outer encoder 1600 of FIG. 16, respectively.

20 is a block diagram schematically illustrating an apparatus for transmitting a signal using multiple encoding and multiple mapping according to an embodiment of the present invention. As shown in FIG. 20, a signal transmission apparatus may be implemented using both the multiple encoding scheme and the multiple mapping scheme described with reference to FIGS. 16 and 18.

The signal transmission apparatus includes an outer encoder 2000, a multiple encoder 2010, a first interleaver 2020, a multiple mapper 2030, a linear precoding unit 2040, a second interleaver 2050, and a frame forming unit ( 2060, a modulator 2070, and a transmitter 2080, and the description of each block is the same as described above with reference to FIGS. 1 and 16, respectively.

21 is a block diagram schematically illustrating a signal receiving apparatus for receiving multiple encoding and multiple mapped signals according to an embodiment of the present invention. The signal receiving apparatus of FIG. 21 corresponds to the signal transmitting apparatus of FIG. 20, and includes a receiver 2100, a synchronizer 2110, a demodulator 2120, a frame parsing unit 2130, and a first device. An interleaver 2140, a linear precoding decoder 2150, a multiple demapper 2160, a second deinterleaver 2170, a multiple decoder 2180, and an outer decoder 2190. Likewise, the description of each block of the signal receiving apparatus is the same as described with reference to FIGS. 10 and 18.

FIG. 22 is a block diagram schematically illustrating another signal receiving apparatus for receiving multiple encoding and multiple mapped signals according to an embodiment of the present invention. The signal receiver includes a receiver 2200, a synchronizer 2210, a demodulator 2220, a frame parsing unit 2230, a first deinterleaver 2240, and an equalizer 2250. ), A linear precoding decoder 2260, a multiple demapper 2270, a channel estimator 2280, a second deinterleaver 2290, a multiple decoder 2292 and an outer decoder 2294. .

In a system to which a multiple mapping scheme is applied, a symbol having a small constellation size has a relatively low minimum required SNR compared to a symbol having a large constellation size. Therefore, in order to further increase the capacity, a symbol having a small constellation size may be used as a pilot symbol. That is, by not using a separate pilot or by performing a function of some pilots using a symbol having a small constellation size, the transmission rate is increased by the number of pilots reduced. In the case of using the symbol having the small constellation size, the channel is estimated based on the value determined by receiving the symbol.

The minimum required SNR of the symbol with the large constellation size is higher than the minimum required SNR of the symbol with the relatively small constellation size. Therefore, in an SNR section in which a symbol having a large constellation size is decoded, reliability of a symbol having a small constellation size is relatively high and thus can be used as a pilot symbol.

The division of the symbol having the small constellation size and the symbol having the large constellation size may vary depending on the implementation of the implementer. For example, in the case where a specific constellation point or more is divided into a large constellation size, the number of reference points may vary according to implementation.

When multiple mapping is performed on the symbol data having a small constellation size and the symbol data having a large constellation size as described above, the signal transmission apparatus may insert and transmit a pilot to the multi-mapped symbol data. As described above, when symbol data having a small constellation size is used as a pilot symbol, the signal transmission apparatus may insert and transmit the symbol data having the small constellation size instead of a pilot at an insertion position of the pilot.

When the symbol data having the small constellation size is inserted into a pilot insertion position, symbol data having the small constellation size may be inserted into all of the pilot insertion positions, and symbol data having the small constellation size may be inserted only at a part of the positions. You can also insert the pilot in the rest position.

For example, in the signal transmission apparatus as shown in FIG. 20, the frame forming unit 2060 may form a frame by inserting symbol data having a small constellation size for all pilot insertion positions. Alternatively, the frame forming unit 2060 may form a frame by inserting symbol data having a small constellation size only in a part of the position and inserting a pilot in the remaining position. In consideration of the channel situation, the transmission and reception system, etc., an appropriate method may be selected and implemented.

In the case of FIG. 20, a multiple encoding scheme is also used, but it is also applicable to a case of encoding with a general inner encoding scheme instead of the multiple encoding scheme.

22 is a diagram illustrating an apparatus for receiving and processing a signal when a signal is transmitted using a symbol data having a small size as a pilot symbol in the apparatus for transmitting a signal as shown in FIG. 20.

For convenience of description, the following description will be given based on portions of the block of FIG. 22 that do not overlap with the block of FIG. 21.

The frame parser 2230 parses the frame data demodulated by the demodulator 2220. When the frame is formed by inserting the symbol data having a small constellation size for all pilot insertion positions in the signal transmission apparatus as described above, the frame parsing unit 2230 extracts the symbol data inserted at the pilot positions to extract the remaining symbols. Restore with the data. If, in the signal transmission apparatus, symbol data having a small constellation size is inserted only at a part of pilot insertion positions, and a pilot is inserted at the remaining positions, the frame parsing unit 2230 may perform the small constellation size. The pilot data is extracted together with the symbol data having a to recover the symbol data.

For convenience of explanation, the following description will focus on a case in which symbol data having a small constellation size is inserted in only some of the pilot insertion positions and a pilot is inserted in the remaining positions.

The channel estimator 2280 estimates a transmission channel using the pilot output from the frame parser 2230 and input / output information of the multiple demapper 2270. When estimating a channel using the pilot output from the frame parsing unit 2230, a pilot received on a k-th carrier is referred to as P _r (k) and a promised pilot known by the receiver is referred to as P _{r. In the case of t} (k), a channel transfer function (CTF) is represented by Equation 1 below.

H _p (k) refers to a channel transfer function estimated using a pilot.

In addition, when estimating a channel using symbol data having a small constellation size inserted at a pilot insertion position, the received symbol data, that is, symbol data input to the multiple demapper 2270 is referred to as Y _r (k). When the determined symbol data, that is, symbol data output from the multiple demapper 2270 is Y _t (k), the channel transfer function is expressed by Equation 2 below.

The H _d (k) refers to a channel transfer function estimated using symbol data having a small constellation size. The division operation may be performed by directly designing a divider, or may be performed by calculating the inverse of the denominator or multiplying by a numerator. Alternatively, the multiplication may be performed by referring to a ROM table that stores the reciprocal value of the denominator. Alternatively, the reciprocal value of the denominator multiplied by the complex conjugate of the denominator and the numerator complex number are multiplied, respectively, to obtain a reciprocal value of the denominator multiplied by the complex complex number. It can also be done by multiplying by. This may vary depending on implementation.

When no pilot symbol is used in the signal transmission apparatus, only a channel transfer function using symbol data having a small constellation size can be obtained as shown in Equation 2 above.

The channel transfer function estimated in Equation 1 or 2 may be used for channel equalization. The receiver may equalize a channel by selecting one value among the estimated values, or equalize by interpolating the two estimated values. For example, the selection method may vary depending on the implementation, such as selecting one value in consideration of channel conditions, or selecting and using a different estimated value when a specific estimated value changes abruptly. Alternatively, the estimated two values may be equalized to values obtained by interpolation through linear interpolation or the like.

23 is a block diagram schematically illustrating a channel estimator according to an embodiment of the present invention. The channel estimator includes a determiner 2300, a first operator 2310, a first multiplier 2320, a second multiplier 2330, a second calculator 2340, a pilot generator 2350, and a third calculator. 2360, a third multiplication unit 2370, a fourth multiplication unit 2380, and a fourth operation unit 2390. If the pilot symbol is not inserted, the pilot generator 2350, the third operator 2360, the third multiplier 2370, the fourth multiplier 2380, and the fourth operator (2390) shall not be used.

The channel estimator of FIG. 23 multiplies the denominator and the numerator by the complex conjugate value of the denominator to obtain the inverse value of the denominator multiplied by the conjugate complex number, and the numerator and the reciprocal value of the denominator complex multiplied by the denominator. This is an example of obtaining a channel transfer function by multiplying by.

First, pilot symbol data (symbol data having a small constellation size in this example) input to the symbol demapper 2270 and pilot symbol data output from the symbol demapper 2270 are input to the determination unit 2300. . The determiner 2300 outputs the symbol data output from the symbol demapper 2270 to the first operator 2310 and the first multiplier 2320.

The first operator 2310 obtains a complex conjugate value of the input symbol data and outputs the complex conjugate value to the first multiplier 2320 and the second multiplier 2330. The first multiplier 2320 multiplies the symbol data output from the determiner 2300 and the conjugate complex value output from the first operator 2310 and outputs the multiplied complex value to the second operator 2340. The second multiplier 2330 may multiply the symbol data input to the symbol demapper 2270 and the conjugate complex value output from the first operator 2310 among the symbol data input to the determiner 2300 to perform a second operation. 2340).

The second calculator 2340 obtains an inverse value corresponding to the value output from the first multiplier 2320, and multiplies the inverse value by the value output from the second multiplier 2330.

When estimating a channel transfer function using the pilot symbols, the pilot symbols extracted by the frame parser 2230 are used. The pilot generator 2350 generates a pilot symbol previously promised with the transmitting side. The generated pilot symbols are output to the third operator 2360 and the third multiplier 2370.

The third operation unit 2360 obtains a complex conjugate value of the input pilot symbol and outputs the complex conjugate value to the third multiplier 2370 and the fourth multiplier 2380. The third multiplier 2370 multiplies the pilot symbol output from the pilot generator 2350 by the conjugate complex value output from the third operator 2360 and outputs the multiplied complex value to the fourth operator 2390. The fourth multiplier 2380 multiplies the pilot symbol extracted by the frame parser 2230 and the conjugate complex value output from the third operator 2360 and outputs the multiplied complex value to the fourth operator 2390.

The fourth calculator 2390 obtains an inverse value corresponding to the value output from the third multiplier 2370, and multiplies the inverse value by the value output from the fourth multiplier 2380.

The first deinterleaver 2240 deinterleaves the symbol data output from the frame parser 2230 to restore the order. The deinterleaved data is output to the equalizer 2250. The equalizer 2250 compensates the distortion due to the transmission channel for the symbol data whose order is reconstructed by using a channel transfer function for the channel estimated by the channel estimator 2280.

For example, the equalizer 2250 may use a zero forcing equalization scheme to compensate for the channel distortion. Since the received symbol can be represented as a product of the transmission symbol and the channel transmission function, dividing the received symbol by the estimated channel transmission function can restore the transmission symbol data value. That is, if the received symbol data value is Yr (k) and the estimated channel transfer function is H (k), the recovered symbol data value Y _eq (k) is expressed by Equation 3 below.

24 is a block diagram schematically illustrating an equalizer according to an embodiment of the present invention. The equalizer 2250 includes an interpolator 2400, a fifth operator 2410, a fifth multiplier 2420, a sixth multiplier 2430, and a sixth operator 2440. The equalizer of FIG. 24 is an example of implementing the zero forcing equalization scheme as described above.

There are various methods for performing the division operation in FIG. 6 as described above. However, the equalizer of FIG. 24 uses the same process as the division operation in FIG.

The interpolator 2400 interpolates the input channel transfer function value to a value of full bandwidth. The channel transfer function values interpolated by the interpolator 2400 are output to the fifth operator 2410 and the fifth multiplier 2420. The fifth operator 2410 calculates and outputs a complex conjugate value of the channel transfer function output from the interpolator 2400.

The fifth multiplier 2420 multiplies the channel transfer function value output from the interpolator 2400 and the conjugate complex value of the channel transfer function output from the fifth operator 2410 to the sixth operator 2440. Output The sixth multiplier 2430 multiplies the conjugate complex value output from the fifth operator 2410 by the received symbol data and outputs the result to the sixth operator 2440.

The sixth operator 2440 obtains an inverse value corresponding to the value output from the fifth multiplier 2420, and multiplies the inverse value by the value output from the sixth multiplier 2430.

The symbol data equalized by the equalizer 2250 is output to the linear precoding decoder 2250. The linear precoding decoder 2250 reconstructs and outputs distributed symbol data, and the reconstructed symbol data is input to the multiple demapper 2270 and the channel estimator 2280.

The multiple demapper 2270 demaps the received symbol data using each demapper and outputs corresponding bit data. The multiple demapper 2270 transmits the symbol data value determined for the symbol data having a small constellation size to the channel estimator 2280. Alternatively, the demapped bit data of the symbol data having the small constellation size may be output to the channel estimator 2280. Since channel estimation is performed in the unit of symbol data, when outputting de-mapped bit data for symbol data having a small constellation size to the channel estimating unit 2280, the determination unit 2300 of FIG. The symbol data corresponding to the received bit data must be determined again.

The second deinterleaver 2290 deinterleaves the bit data received by the multiple demapper 2270 to restore the order. The multiple decoder 2292 multiplexes and outputs the reconstructed bit data according to a multiple encoded scheme. If a signal transmission apparatus does not use multiple encoding schemes but uses one encoding scheme, multiple decoders are not used and one decoding scheme corresponding to the encoding scheme is used.

25 is a block diagram schematically illustrating an apparatus for transmitting a signal of a data symbol channel estimation method according to an embodiment of the present invention. The signal transmitter includes an outer encoder 2500, an inner encoder 2510, a first interleaver 2520, a trellis code modulator 2530, a linear precoding unit 2540, a second interleaver 2550, and a frame. A forming unit 2560, a modulator 2570, and a transmitter 2580 are included.

As described above, when the symbol data having the small constellation size is inserted in all the insertion positions of the pilot, or the symbol data having the small constellation size is inserted in only a partial position, and the pilot is inserted in the remaining positions, the pilot insertion is performed. The symbol data inserted at the position may be determined, and a channel may be estimated based on the determined symbol data. In the case of the above scheme, channel estimation performance can be increased, and the entire system can be increased by not using pilot symbols or using only a part of the pilot symbols.

However, if a decision error occurs in a low SNR environment, an error may occur in the channel estimation, and an error of data compensated with the channel estimation value having the error may become larger, resulting in error propagation. Symptoms may occur.

In order to prevent the error spreading phenomenon, the channel is estimated using only a decision value having high reliability among decision values for the received symbol data.

For example, it is assumed that the symbol data having the small constellation size is inserted into all of the pilot insertion positions in the signal transmission apparatus as shown in FIG. Each block of the apparatus for transmitting signals of FIG. 25 and the apparatus for transmitting signals of FIG. 20 is the same, except that the trellis code modulation method is used instead of the multiple mapping method. The trellis code modulation scheme is also an example and QAM. Other symbol mapping schemes such as QPSK, optical constellation schemes may be used. The description of the signal transmission device of FIG. 25 is the same as that of FIG. 20.

However, since the frame forming unit 2560 of FIG. 25 inserts the symbol data having the small constellation size at the pilot insertion position without inserting the pilot, the symbol data inserted at the pilot insertion position is extracted to extract the remaining symbol data. Restore with

FIG. 26 is a block diagram schematically illustrating a signal receiving apparatus of a data symbol channel estimation method according to an embodiment of the present invention. The signal receiver includes a receiver 2600, a synchronizer 2602, a demodulator 2604, a frame parsing unit 2608, a first deinterleaver 2610, an equalizer 2612. ), Linear precoding decoder 2614, trellis code decoder 2616, channel state estimator 2618, channel estimator 2620, second deinterleaver 2622 , An inner decoder 2624 and an outer decoder 2626. The signal receiving apparatus of FIG. 26 receives and processes a signal transmitted from the signal transmitting apparatus as shown in FIG.

The signal receiving apparatus of FIG. 26 corresponds to the signal receiving apparatus of FIG. 22, and for convenience of description, the following description will be made based on differences.

Since the pilot is not inserted into the received frame data, and symbol data having the small constellation size is inserted at the pilot insertion position, the frame parsing unit 2608 of FIG. 26 stores the symbol data inserted at the pilot insertion position. Extract and restore with the rest of the symbol data.

The channel state estimator 2618 estimates the state of the transmission channel for each symbol data position, that is, each subcarrier. In order to estimate the channel state, a Log-Likelihood Ratio (LLR) value used for symbol data determination or an SNR of a channel may be used. The subcarrier estimating the channel state may be a subcarrier file for transmitting symbol data inserted at the pilot insertion position or a subcarrier file for transmitting other symbol data included in a frame.

The channel estimator 2620 determines a channel having a good state by using the state of each channel estimated by the channel state estimator 2618, and estimates a channel by using symbol data received from the channel having a good state. . For example, the good channel may be a case in which the SNR of the channel is high or the LLR value is high. In addition, if a high reliability is applied to a channel that receives symbol data having a small constellation size or symbol data coded at a low code rate in addition to the above information, the channel estimation error can be further reduced.

The channel estimator 2620 may obtain a channel estimation function by using the received symbol data for the good channel and the symbol data determined by the trellis code decoder 2616. The equalizer 2612 compensates for the channel distortion of the received symbol data by using the channel estimation function output from the channel estimator 2620.

In addition to the method of estimating the channel using the determined symbol data described above, a multiple encoding scheme or a multiple mapping scheme may be used. That is, the multiple encoding scheme and the multiple mapping scheme may be separately used together or may be applied to the scheme of estimating the channel using the determined symbol data.

27 is a block diagram schematically illustrating another signal transmission apparatus of a data symbol channel estimation method according to an embodiment of the present invention, and FIG. 28 is another signal of the data symbol channel estimation method according to an embodiment of the present invention. A block diagram schematically showing a receiving device.

The signal transmission apparatus of FIG. 27 includes an outer encoder 2700, a multiple encoder 2710, a first interleaver 2720, a multiple mapper 2730, a linear precoding unit 2740, a second interleaver 2750, and frame formation. And a signal receiver 2760, a modulator 2770, and a transmitter 2780. The signal receiver of FIG. 28 includes a receiver 2800, a synchronizer 2802, a demodulator 2804, A frame parsing unit 2806, a first deinterleaver 2808, an equalizer 2810, a linear precoding decoder 2812, a multiple demapper 2814, a channel state ) Includes an estimator 2816, a channel estimator 2818, a second deinterleaver 2820, a multiple decoder 2822, and an outer decoder 2824.

27 and 28 are examples of using both a multiple encoding scheme and a multiple mapping scheme in a method of estimating a channel using the determined symbol data, and the description of each block is the same as described in the above embodiments.

Each embodiment described above may be used in combination with a multi-input multi-output (MIMO) technology. For convenience of explanation, only the example in which multiple input / output technologies are combined with respect to the signal transmission apparatus of FIG. 1 will be described.

29 is a block diagram schematically illustrating another signal transmission apparatus according to an embodiment of the present invention. The transmission and reception system may use MIMO (Multi Input Multi Output) for multiple input and output. The transmitter of FIG. 29 is a case where a multiple input / output method is applied to the transmitter of FIG. Hereinafter, an embodiment of a signal transmission system according to the present invention will be described with reference to FIG. 29.

The embodiment of FIG. 29 includes a forward error correction (FEC) encoder 2900, a first interleaver 2910, a symbol mapper 2920, and a linear precoding unit 2930. , A second interleaver 2940, a multiple input / output encoder 2950, a frame builder 2960, a modulator 2970, and a transmitter 2980. 29 illustrates a process of processing a signal in the signal transmission system.

The forward error correcting unit 2900 encodes and outputs an input signal, thereby allowing the receiver to detect an error in the transmitted data and correct the error. The forward error correcting unit 2900 corresponds to the outer encoder 100 and the inner encoder 110 of FIG. 1.

30 is a block diagram schematically illustrating a forward error correction as an embodiment according to the present invention. The forward error correction of FIG. 30 may be used in the transmission system of FIG. 29. The forward error correcting unit includes a BCH (Bose-Chaudhuri-Hocquenghem) encoder 2902 and a Low Density Parity Check (LDPC) encoder 2904 as an outer encoder and an inner encoder.

The LDPC code is a type of error correcting code that can reduce the probability of data loss as much as possible. The LDPC encoder 2904 can increase the length of the block so that the transmission data can be robust to transmission errors. In addition, in order to prevent an increase in hardware complexity due to an increase in the block size, the complexity of the decoder may be reduced by decreasing the density of parity bits.

In order to prevent an error floor from occurring in the output data of the receiver, a BCH encoder 2902 is concatenated with the LDPC encoder 2904 using an additional outer encoder. If the LDPC encoder 2904 is large enough to ignore the error floor, the BCH encoder 2902 may not be used. Alternatively, an encoder other than the BCH encoder may be used as the outer encoder.

Forward error correction encoded data is output to the first interleaver 2910 through the BCH encoder 2902 and the LDPC encoder 2904.

The first interleaver 2910 mixes and distributes the data strings output from the forward error correction unit 2900 to a random position so as to be robust to a burst error occurring during transmission. A convolution interleaver, a block interleaver, or the like may be used for the first interleaver 2910, which may vary depending on a transmission system.

FIG. 31 illustrates an interleaver for interleaving input data according to an embodiment of the present invention. The interleaver of FIG. 31 is an example of an interleaver that may be used for the first interleaver 2910 as a block interleaver.

The interleaver of FIG. 31 stores data input to a matrix-type storage space in a predetermined pattern, and reads and outputs data in a pattern different from the storage pattern. For example, the interleaver of FIG. 31 has a storage space (Nr × Nc) consisting of a row of Nr and a column of Nc, and data input to the interleaver is filled from the position of one column, one row of the storage space. Data is stored starting from row 1 of column 1 up to row Nr of column 1, and when the column 1 is filled up, data is stored starting from row 1 of the next column (column 2) up to row Nr. Data can be stored up to Nr rows of Nc columns in the above order.

When reading the data stored in the storage space, the data of the row is read and output from the data of the first row to the first column of the storage space up to the first row Nc column. If all the data of the row is read, starting from the first column of the next lower row (row 2), the data of the row is read and output in the right direction. Data can be read and output up to Nc columns of Nr rows in the same order as described above. At this time, the MSB (Most Significant Bit) position of the data block is at the top left, and the LSB (Least Significant Bit) position is at the bottom right.

A size, a storage pattern, a read pattern, and the like of the storage block of the interleaver are one embodiment, which may vary depending on the implementation.

The interleaved data in the first interleaver 2910 is input to the symbol mapper 2920. The symbol mapper 2920 may use the above-described optimal constellation mapping scheme.

The linear precoding unit 2930 distributes the input symbol data into a plurality of output symbol data, thereby reducing the probability that all information is lost due to fading when experiencing a frequency selective fading channel.

32 is a block diagram schematically illustrating a linear precoding unit according to an embodiment of the present invention. The precoding unit 2930 includes a serial / parallel conversion unit 2932, an encoding unit 2934, and a parallel / serial conversion unit 2936.

The serial / parallel converter 2932 converts the input data into parallel data. The encoding unit 2934 distributes the parallel data into a plurality of data through encoding matrixing.

The encoding matrix is designed to compare an output symbol with an input symbol so that Pairwise Error Probability (PEP), which is a probability that the two symbols are wrong, is minimized. Designed to minimize PEP, the diversity gain and coding gain obtained through linear precoding can be maximized.

In addition, when the minimum Euclidean distance of a linear precoded symbol is maximized through the encoding matrix, an error probability may be minimized when the receiver uses a maximum likelihood (ML) decoder.

33 (a) is a diagram illustrating a matrix of codes for distributing input data according to an embodiment of the present invention. 33 (a) is called a vanderMonde matrix as an example of an encoding matrix for distributing the input data into a plurality of output data. The input data may be arranged in parallel in the length (L) of the output data.

Θ of the matrix may be expressed by the following equation, and may be defined in other ways. The vanderMonde matrix can adjust the matrix component by Equation 4.

The matrix rotates each input data by the phase of the corresponding Equation 4 to reflect the input data. Therefore, the input values may be distributed among at least two output values according to the characteristics of the matrix.

In Equation 4, L represents the number of output data. Assuming that the input data group input to the encoding unit 2934 of FIG. 32 is x and the data group coded and output from the encoding unit 2934 by the matrix is y, y is represented by Equation 5 below.

33 (b) is a diagram illustrating another code matrix for distributing input data according to an embodiment of the present invention. 33 (b) is called an Hadamard matrix as an example of an encoding matrix for distributing the input data into a plurality of output data. The matrix of FIG. 33 (b) is a general form extended to an arbitrary size of L = ^2k , and 'L' represents the number of output symbols to distribute each input symbol.

The output symbols of the matrix can be obtained by the sum and difference of the L input symbols. In other words, each input symbol can be spread over L output symbols.

In the case of the matrix of FIG. 33B, the input data group input to the encoding unit 2934 of FIG. 32 is x, and the data group coded and output from the encoding unit 2934 by the matrix is y. Y is the product of the matrix and x.

33 (c) is a diagram illustrating another code matrix for distributing input data according to an embodiment of the present invention. 33 (c) is called Golden code as an example of an encoding matrix for distributing the input data into a plurality of output data. The golden code is a special type of 4x4 matrix, and can be interpreted as two different 2x2 matrices alternately used.

C of FIG. 33C shows a code matrix of a golden code, and x1, x2, x3, and x4 in the code matrix represent symbol data input to the encoding unit 2934. . Each constant in the code matrix determines a characteristic of the code matrix. The values of the rows and columns calculated from the respective constants and input symbol data of the code matrix represent output symbol data. A rule may be defined in the output order of the symbol data according to the implementation example.

The parallel / serial converter 2936 converts the data received by the encoder 2934 back to serial data and outputs the serial data.

The second interleaver 2940 interleaves the symbol data output from the linear precoding unit 2930 again. That is, interleaving is performed in the second interleaver 2940 so that symbol data dispersed in data output from the linear precoding unit 2930 does not experience the same frequency selective fading. A convolution interleaver, a block interleaver, or the like may be used for the second interleaver 2940.

The linear precoding unit 2930 and the second interleaver 2940 process the data to be transmitted to be robust to the frequency selective fading of the channel, and may be viewed as a frequency selective fading coding unit.

The multiple input / output encoder 2950 encodes the data interleaved by the second interleaver 2940 to be carried on a plurality of transmission antennas. There are two types of multiple input / output encoding methods, spatial multiplexing and spatial diversity. Spatial multiplexing is a method in which multiple antennas are transmitted to a transmitter and a receiver to transmit different data at the same time, thereby transmitting data at higher speed without further increasing the bandwidth of the system. Spatial diversity is a method of obtaining transmit diversity by transmitting data of the same information from multiple transmit antennas.

In this case, a space diversity time input / output encoder 2950 may use a space-time block code (STBC), a space-frequency block code (SFBC), a space-time trellis code (STTC), or the like. The spatial multiplex multiple input / output encoder 2950 simply transmits data streams by separating the number of transmit antennas, full-diversity full-rate (FDFR) code, linear dispersion code (LDC), and V-BLAST. (Vertical-Bell Lab. Layered space-time) and D-BLAST (diagonal-BLAST) can be used.

The frame forming unit 2960 forms a frame by inserting a pilot signal to modulate the precoded signal in an orthogonal frequency division multiplex (OFDM) scheme.

34 is a diagram illustrating a structure of a transmission frame according to an embodiment of the present invention. The transmission frame is composed of a pilot symbol period including pilot carrier information and a data symbol period including only data information.

In FIG. 34, one frame includes M intervals, and is divided into M-1 data symbol intervals and one pilot symbol interval used as a preamble. The frame having the above structure is repeated.

Each symbol period includes carrier information as many as the number of subcarriers of an Orthogonal Frequency Division Multiplex (OFDM) scheme. The pilot carrier information of the pilot symbol interval is composed of random data in order to lower the peak to average power ratio (PAPR). The pilot carrier information has a form in which auto-correlation is an impulse in the frequency domain.

Pilot carrier information is not included in the data symbol interval, and thus data capacity can be increased. For example, in the case of DVB, since the ratio of pilot carriers to total effective carriers is about 10%, the rate of increase of data capacity is expressed by the following equation.

In Equation 6, Δ represents an increase rate, and M is the number of sections included in one frame.

The modulator 2970 inserts a guard interval to modulate the data output from the frame forming unit 2960 on subcarriers of OFDM. The transmitter 2980 converts a digital signal having a guard period and a data period output from the modulator 2970 into an analog signal and transmits the signal.

35 is a block diagram schematically illustrating a case in which a signal transmission apparatus has a plurality of transmission paths according to an embodiment of the present invention. For convenience of explanation, the following description will be given by using two transmission paths as an example.

The embodiment of FIG. 35 includes a forward error corrector 3500, a first interleaver 3510, a symbol mapper 3520, a linear precoding unit 3530, a second interleaver 3540, and multiplexing. I / O encoder 3550, first frame builder 3560, second frame former 3565, first modulator 3570, second modulator 3575, first transmitter 3580 ) And a second transmitter 3585.

Signal processing from the forward error correction 3500 to the multiple input / output encoder 3550 is the same as described with reference to FIG. 29.

The forward error correcting unit 3500 includes a BCH encoder and an LDPC encoder, and outputs an error correction coded input data. The output data is interleaved in the first interleaver 3510 to mix the data sequence. A convolution interleaver, a block interleaver, and the like may be used for the first interleaver 3510.

The symbol mapper 3520 maps the received data into symbol data according to the above-described optical constellation mapping method.

The linear precoding unit 3530 includes a serial / parallel converter, an encoder, and a parallel / serial converter.

36 (a) to 36 (e) illustrate an example of a 2x2 code matrix for distributing input symbols according to an embodiment of the present invention. The code matrixes of FIGS. 36 (a) to 36 (e) may be applied to a transmission apparatus as shown in FIG. 35, and two data input to the encoding unit of the linear precoding unit 3530 are distributed to two output data. Let's do it.

The matrix of FIG. 36A is an embodiment of the vanderMonde matrix described with reference to FIG. 33A.

) 회전된 두번째 입력 데이터를 더하여 첫번째 출력 데이터로 출력하며, 첫번째 입력 데이터와 위상이 225도(

) 회전된 두번째 입력 데이터를 더하여 두번째 출력 데이터로 출력한다. 그리고 상기 각 출력 데이터는

로 나누어 스케일링(scaling)한다.The matrix of FIG. 36 (a) is 45 degrees out of phase with the first of the two input data.

) Adds the second rotated input data and outputs it as the first output data. The phase is 225 degrees with the first input data.

) Add the rotated second input data and output it as the second output data. And each output data

Scaling by dividing by.

The matrix of FIG. 36 (b) is an embodiment of the Hadamard matrix described in FIG. 33 (b).

로 나누어 스케일링(scaling)한다.The matrix of FIG. 36 (b) adds the first input data and the second input data among the two input data and outputs the first output data. The second input data is subtracted from the first input data and output as the second output data. And each output data

Scaling by dividing by.

36 (c) illustrates another example of a code matrix for distributing input symbols applicable to FIG. 35 according to an embodiment of the present invention. The matrix of FIG. 36C is an embodiment of another code other than the matrix described with reference to FIGS. 33A, 33B, and 33C.

) 회 전된 첫번째 입력 데이터와 위상이 -45도(

) 회전된 두번째 입력 데이터를 더하여 첫번째 출력 데이터로 출력하며, 위상이 45도 회전된 첫번째 입력 데이터에서 위상이 -45도 회전된 두번째 입력 데이터를 빼서 두번째 출력 데이터로 출력한다. 그리고 상기 각 출력 데이터는

로 나누어 스케일링한다.The matrix of FIG. 36 (c) has a phase of 45 degrees between two input data.

) The first input data rotated and the phase is -45 degrees (

The second input data rotated is added to the first output data, and the second input data rotated by -45 degrees is subtracted from the first input data rotated by 45 degrees to output the second output data. And each output data

Divide by to scale.

36 (d) illustrates another example of a code matrix for distributing input symbols applicable to FIG. 35 according to an embodiment of the present invention. The matrix of FIG. 36 (d) is another embodiment of the code other than the matrix described with reference to FIGS. 33A, 33B, and 33C.

로 나누어 스케일링한다.The matrix of FIG. 36 (d) adds the first input data multiplied by 0.5 to the second input data and outputs the first output data, and subtracts the second input data multiplied by 0.5 from the first input data and outputs the second output data. And each output data

Divide by to scale.

FIG. 36 (e) is a diagram illustrating another example of a code matrix for distributing an input symbol applicable to FIG. 35 according to an embodiment of the present invention. The matrix of FIG. 36 (e) is another embodiment of code other than the matrix described with reference to FIGS. 33A, 33B, and 33C. '*' In FIG. 36 (e) indicates a complex conjugate with respect to input data.

) 회전된 첫번째 입력 데이터와 두번째 입력 데이터를 더하여 첫번째 출력 데이터로 출력하며, 첫번째 입력 데이터의 켤레 복소수와 위상이 -90(

)도 회전된 두번째 입력 데이터의 켤레 복소수를 더하여 두번째 출력 데이터로 출력한다. 그리고 상기 각 출력 데이터는

로 나누어 스케일링한다.36 (e), the phase of the two input data is 90 degrees (

) The first input data and the second input data rotated are added to output the first output data. The complex number and phase of the first input data are -90 (

) Also outputs the second output data by adding the complex conjugate of the rotated second input data. And each output data

Divide by to scale.

The second interleaver 3540 interleaves the symbol data output from the linear precoding unit 3530 again. A convolution interleaver, a block interleaver, or the like may be used for the second interleaver 3540. Since the second interleaver 3540 mixes symbol data dispersed in the data output from the linear precoding unit 3530 so as not to experience the same frequency selective fading, the type of the second interleaver 3540 is an implementation example of a transmission / reception system. It may vary.

In the case of using the block interleaver, the length of the interleaver may vary depending on implementation. If the length of the interleaver is less than or equal to the OFDM symbol length, interleaving is performed only in an area within one OFDM symbol, and if the length of the interleaver is longer than the OFDM symbol length, interleaving may be performed over several symbols.

37 is a diagram illustrating an example of an interleaver according to an embodiment of the present invention. The interleaver of FIG. 37 may be used in the second interleaver 3540 of the transmitting apparatus as shown in FIG. 35 as an embodiment of the interleaver for the OFDM system having the symbol length N.

N represents the length of the interleaver, i has a value equal to the length of the interleaver, that is, an integer value from 0 to N-1. n has the number of effective transport carriers in the transmission system. ∏ (i) denotes a permutation of modulo-N operations, and d _n has values of ∏ (i) in the effective transport carrier region in order except N / 2 values. k represents the index value of the actual transport carrier, so that d / 2 is subtracted from d _n so that the center of the transmission bandwidth is DC. P is a permutation constant and may vary depending on the embodiment.

38 is a diagram illustrating a specific example of the interleaver of FIG. 37 according to an embodiment of the present invention. In the example of FIG. 38, the length of an OFDM symbol and the length N of an interleaver are set to 2048, and the number of effective transmission carriers is set to 1536 (1792-256).

Therefore, i is an integer of 0-2047, n is an integer of 0-1535. ∏ (i) is a permutation of modulo-2048 operations, and d _n has a value of ∏ (i) in order except 1024 (N / 2) for a value of 256 ≦ ∏ (i) ≦ 1792. k is a value obtained by subtracting 1024 from d _n . P has 13.

Since the data k corresponding to the input data i is output using the interleaver as described above, the data of the length N of the interleaver can be mixed and transmitted.

The interleaved data is output to the multiple input / output encoder 3550, and the multiple input / output encoder 3550 encodes and outputs the input symbol data to be carried on the plurality of transmission antennas. For example, when there are two transmission paths, the multiple input / output encoder 3550 outputs precoded data to the first frame forming unit 3560 or the second frame forming unit 3565.

In the case of the spatial diversity method, data of the same information is output to the first frame forming unit 3560 and the second frame forming unit 3565, respectively, and the first frame forming unit ( Different data is output to the 3560 and the second frame forming unit 3565, respectively.

39 is a diagram illustrating an example of a multiple input / output encoding scheme according to an embodiment of the present invention. The embodiment of FIG. 39 is STBC, which is one of multiple input / output encoding schemes, and may be used in a transmitting apparatus as shown in FIG. The encoding scheme is one example, and the application of other multiple input / output encoding schemes is not excluded.

In the example of the STBC encoder, T denotes a symbol transmission period, s denotes an input symbol to be transmitted, and y denotes an output symbol. * Denotes a complex conjugate, and Tx # 1 and Tx # 2 denote transmission antennas 1 and 2, respectively.

According to the above example, at time t Tx # 1 transmits s ₀ , Tx # 2 transmits s ₁ , and at time t + T Tx # 1 transmits -s ₁ ^* and Tx # 2 transmits s ₀ ^* do. Each transmitting antenna transmits data of the same information of s ₀ and s ₁ within a transmission period. Accordingly, it can be seen that the encoding scheme is one of spatial diversity schemes.

The first frame forming unit 3560 and the second frame forming unit 3565 form a frame into which a pilot signal is inserted so as to modulate each of the received signals in an orthogonal frequency division multiplex (OFDM) scheme.

The frame includes one pilot symbol period and M-1 data symbol periods. When the transmission system of FIG. 35 performs multiple input / output encoding using a plurality of antennas, a structure of a pilot symbol should be determined so that each transmission path can be distinguished from a receiving side.

40 (a) is a diagram showing the structure of a pilot symbol interval according to an embodiment of the present invention. The structure of the pilot symbol interval of FIG. 40 (a) may be used when multiple input / output encoding is performed to have two transmission paths as shown in FIG.

In case of FIG. 40A, pilot carrier information is interleaved and divided into even and odd pilots in order to distinguish two transmission paths. For example, frame data including even pilot carrier information in a pilot symbol period is transmitted through antenna 0, and frame data including odd pilot carrier information in a pilot symbol period is transmitted through antenna 1. do. Accordingly, the receiving side can distinguish each transmission path using the corresponding carrier index of the pilot symbol interval.

In the above embodiment, a channel corresponding to half of subcarriers may be estimated in one symbol. Therefore, high channel estimation performance can be obtained even for a transmission channel having a short coherence time.

40 (b) illustrates another structure of a pilot symbol section according to an embodiment of the present invention. 40 (b) may also be used when multiple input / output encoding is performed to have two transmission paths as shown in FIG. 39.

40 (b) shows an embodiment of a Hadamard type pilot symbol interval. In the above embodiment, Hadamard transformation is performed in units of symbol intervals to distinguish two transmission paths. Accordingly, the even symbol interval includes the sum of two pilot carrier information for each transmission path, and the odd symbol interval includes the difference between two pilot carrier information.

For example, the even symbol interval includes a pilot value of a carrier (a) to be transmitted through antenna 0 and a pilot value of pilot carrier information (b) to be transmitted through antenna 1 (a + b). And a difference value ab of pilot carrier information a to be transmitted through the first antenna and pilot carrier information b to be transmitted through the first antenna. If the receiving side knows the sum / difference of the two pilot carrier information through the received pilot index, each transmission path can be distinguished.

In the above embodiment, since channels corresponding to all subcarriers can be estimated, delay spread of a channel that can be processed for each transmission path can be extended by a symbol length.

40 (b) is a diagram for easily distinguishing the two pilot carrier information, and shows both the pilot carrier information in the frequency domain. In the case of the even symbol interval and the odd symbol interval diagram, impulses of two pilot carrier information are located at the same frequency point. In the case of the even-symbol interval diagram, the positions of the pilot carrier information to be transmitted through the antenna 0 and the pilot carrier information to be transmitted through the antenna 1 are shown to be different for ease of division, and the pilot carrier information is located at the same frequency point. Located.

40 (a) and 40 (b) are examples of two transmission paths, and when the transmission path is longer, pilot carrier information may be distinguished by the number of transmission paths, not odd or even. You can divide or perform Hadamard transformation on a symbol interval basis.

The first modulator 3570 and the second modulator 3575 carry data output from the first frame former 3560 and the second frame former 3565 on subcarriers of OFDM, respectively. Modulate for transmission.

The first transmitter 3580 and the second transmitter 3585 respectively convert a digital signal having a guard interval and a data interval output from the first modulator 3570 and the second modulator 3575 into analog signals. Convert, and transmit the converted analog signal.

41 is a block diagram schematically illustrating another signal receiving apparatus according to an embodiment of the present invention. 41 illustrates a receiver for receiving a signal transmitted according to a multiple input / output scheme. The receiving device of FIG. 41 is a case where a multiple input / output method is applied to the receiving device of FIG.

41, the receiver 4100, the synchronizer 4110, the demodulator 4120, the frame parsing unit 4130, the multiple input / output decoder 4140, and the first deinterleaver a deinterleaver 4150, a linear precoding decoder 4160, a symbol demapper 4170, a second deinterleaver 4180, and a forward error correction decoder 4190. 41 illustrates a process of processing a signal in the signal receiving system, and the number of receiving paths is not determined.

The receiver 4100 down-converts the frequency band of the received RF signal and converts the frequency band into a digital signal. The synchronizer 4110 obtains and outputs a synchronization between a frequency domain and a time domain of the received signal output from the receiver 4100. The synchronization unit 4110 may use an offset result of the frequency domain of data output by the demodulator 4120 to obtain synchronization of the frequency domain signal.

The demodulator 4120 demodulates the received data output from the synchronizer 4110 and removes the guard interval. To this end, the demodulator 4120 converts the received data into the frequency domain, and decodes the data values distributed in the subcarriers into values assigned to each subcarrier.

The frame parser 4130 may output symbol data of a data symbol period excluding pilot symbols according to the frame structure of the signal demodulated by the demodulator 4120.

The multiple input / output decoder 4140 receives and decodes the data output from the frame parser 4130 and outputs one data string. The multiple input / output decoder 4140 outputs one data string by decoding according to a scheme corresponding to a scheme encoded by the multiple input / output encoder 2950 of FIG. 29 so as to be carried on a plurality of transmission antennas.

The first deinterleaver 4150 performs de-interleaving on the data string output from the multiple input / output decoder 4140 to restore the data in the order before interleaving. The first deinterleaver 4150 is deinterleaved according to a method corresponding to the method interleaved by the second interleaver 2940 of FIG. 29 to restore the order of data columns.

The linear precoding decoder 4160 restores data by performing an inverse process of distributing data in the signal transmission apparatus.

42 (a) is a block diagram schematically illustrating an example of a linear precoding decoder as an embodiment according to the present invention. The linear precoding decoder 4160 includes a serial / parallel converter 4162, a first decoder 4164, and a parallel / serial converter 4166.

The serial / parallel conversion unit 4422 converts the input data into parallel data. The first decoding unit 4164 recovers the original data from data distributed through decoding matrixing of the parallel data. The decoding matrix performing the decoding becomes an inverse matrix of the encoding matrix of the signal transmission apparatus. For example, when the signal transmission apparatus encodes using a vanderMonde matrix, a Hadamard matrix, a Golden code, or the like as shown in FIGS. 33A, 33B, 33C, and the like, the first decoding unit 4164 is used. ) Respectively restore the distributed data to the original data using the inverse matrix of the matrices.

The parallel / serial converter 4166 converts the parallel data received by the first decoder 4164 back to serial data and outputs the serial data.

42 (b) is a block diagram schematically illustrating another example of a linear precoding decoder according to an embodiment of the present invention. The linear precoding decoder 4160 includes a serial / parallel converter 4141, a second decoder 4416, and a parallel / serial converter 4165.

The serial / parallel converter 4141 converts the input data into parallel data, and the parallel / serial converter 4165 serializes the parallel data received by the second decoder 4416 again. Convert it to data and output it. The second decoder 4403 recovers original data distributed in parallel data output from the serial / parallel converter 4411 using maximum likelihood (ML) decoding.

The second decoder 4403 is an ML decoder considering a transmission scheme in a transmitter. The second decoding unit 4403 restores original data distributed in the parallel data by ML decoding the received symbol data to correspond to the transmission scheme. That is, the ML decoder decodes the received symbol data in consideration of an encoding rule at the transmitting end.

43 (a) to 43 (c) illustrate an example of a 2x2 code matrix for reconstructing distributed symbols according to an embodiment of the present invention. The code matrix of FIGS. 43 (a) to 43 (c) is not the encoding matrix of FIGS. 33 (a) to 33 (c), but the encoding matrix of the 2 × 2 form of FIGS. 36 (c) to 36 (e). Is the inverse matrix corresponding to. The matrix reconstructs and outputs data dispersed in two data input to the decoding unit of the linear precoding decoder 4160.

43 (a) is a diagram illustrating an example of a 2x2 code matrix according to an embodiment of the present invention. The matrix of FIG. 43 (a) is a decoding matrix corresponding to the encoding matrix of FIG. 36 (c).

) 회전된 첫번째 입력 데이터와 위상이 -45도(

) 회전된 두번째 입력 데이터를 더하여 첫번째 출력 데이터로 출력하며, 위상이 45도 회전된 첫번째 입력 데이터에서 위상이 45도 회전된 두번째 입력 데이터를 빼서 두번째 출력 데이터로 출력한다. 그리고 상기 각 출력 데이터는

로 나누어 스케일링한다.The matrix of FIG. 43 (a) has a phase of -45 degrees between two input data.

) The first input data rotated and the phase is -45 degrees (

The second input data rotated is added to the first output data, and the second input data rotated by 45 degrees is subtracted from the first input data rotated by 45 degrees to output the second output data. And each output data

Divide by to scale.

FIG. 43 (b) illustrates another example of a 2 × 2 code matrix according to an embodiment of the present invention. FIG. The matrix of FIG. 43 (b) is a decoding matrix corresponding to the encoding matrix of FIG. 36 (d).

로 나누어 스케일링한다.The matrix of FIG. 43 (b) adds first input data multiplied by 0.5 to second input data and outputs the first output data. Subtracts second input data multiplied by 0.5 from the first input data and outputs the second input data. And each output data

Divide by to scale.

FIG. 43 (c) is a diagram illustrating another example of a 2 × 2 code matrix according to an embodiment of the present invention. FIG. The matrix of FIG. 43 (c) is a decoding matrix corresponding to the encoding matrix of FIG. 36 (e). '*' In FIG. 43 (c) means a complex conjugate with respect to input data.

) 회전된 첫번째 입력 데이터와 두번째 입력 데이터의 켤레 복소수를 더하여 첫번째 출력 데이터로 출력하며, 첫번째 입력 데이터와 위상이 -90도(

) 회전된 두번째 입력 데이터의 켤레 복소수를 더하여 두번째 출력 데이터로 출력한다. 그리고 상기 각 출력 데이터는

로 나누어 스케일링한다.The matrix of FIG. 43 (c) has a phase of −90 degrees (

The first input data is rotated and the complex of the second input data is added to output the first output data. The first input data and the phase are -90 degrees (

) Adds the complex conjugate of the rotated second input data and outputs it as the second output data. And each output data

Divide by to scale.

The symbol demapper 4170 may restore the symbol data decoded by the linear precoding decoder 4160 into a bit string. The symbol demapper 4170 restores a bit string using the demapping method of the optical constellation method described above.

 The second deinterleaver 4180 performs de-interleaving on the data string output from the symbol demapper 4170 to restore the data in the order before interleaving. The second deinterleaver 4180 deinterleaves the data sequence by deinterleaving according to a method corresponding to the interleaving method of the first interleaver 2910 of FIG. 29.

The forward error correction decoder 4190 may forward error correct and decode the data whose order has been restored, detect an error occurring in the received data, and correct the error.

44 is a block diagram schematically showing a forward error correction decoding unit according to an embodiment of the present invention. The forward error correction decoding unit 4190 corresponds to the forward error correction unit 2900 of FIG. 29, and replaces the LDPC decoder 4192 and the BCH decoder 4194 as an inner decoder and an outer decoder. Include.

The LDPC decoder 4192 corrects an error by detecting a transmission error occurring in a channel, and the BCH decoder 4194 corrects a residual error of data decoded by the LDPC decoder 4192 to remove an error floor. .

45 is a block diagram schematically illustrating a case in which a signal receiving apparatus has a plurality of receiving paths according to an embodiment of the present invention. For convenience of explanation, the following description will be given by using two reception paths as an example.

45 illustrates a first receiver 4500, a second receiver 4505, a first synchronizer 4510, a second synchronizer 4515, a first demodulator 4520, and a second demodulator 4525. ), A first frame parser 4530, a second frame parser 4535, a multiple input / output decoder 4540, a third deinterleaver 4550, a linear precoding decoder 4560, a symbol demapper 4570, A fourth deinterleaver 4580 and a forward error correction decoder 4490 are included.

The first receiver 4500 and the second receiver 4505 each receive an RF signal, downconvert the frequency band, and convert the digital signal into a digital signal. The first synchronizer 4510 and the second synchronizer 4515 acquire and output the synchronization of the frequency domain and the time domain of the received signal output from the first receiver 4500 and the second receiver 4505, respectively. The first synchronization unit 4510 and the second synchronization unit 4515 may turn off the frequency domain of the data output by the first demodulator 4520 and the second demodulator 4525, respectively, in order to obtain synchronization of the frequency domain signal. Offset results are available.

The first demodulator 4520 demodulates the received data output from the first synchronizer 4510. To this end, the first demodulator 4520 converts the received data into the frequency domain, and decodes the data values distributed in the subcarriers into values assigned to each subcarrier. The second demodulator 4525 demodulates the received data output from the second synchronizer 4515.

The first frame parser 4530 and the second frame parser 4535 distinguish pilot paths according to the frame structures of the signals demodulated by the first demodulator 4520 and the second demodulator 4525, respectively. The symbol data of the data symbol section excluding the symbol may be output.

The multiple input / output decoder 4540 receives and decodes the data output from the first frame parser 4530 and the second frame parser 4535, respectively, and outputs one data string.

46 is a diagram illustrating an example of a multiple input / output decoding scheme according to an embodiment of the present invention. 46 shows a corresponding decoding example at the reception side when the transmitter transmits data by multiple input / output encoding using the STBC scheme, and the transmitter uses two transmit antennas. This is an example and the application of other multiple input / output methods is not excluded.

R (k), h (k), s (k), and n (k) in the above equations represent symbols received at the receiver, channel response, symbol values transmitted at the transmitter, and channel noise, respectively. Subscripts s, i, 0, and 1 denote an sth transmission symbol, an ith reception antenna, a 0th transmission antenna, and a 1st transmission antenna, respectively. '*' Represents a complex conjugate. For example, h _{s , 1, i} (k) indicates a response of the channel experienced by the transmitted symbol when the s-th transmitted symbol is received by the i-th reception antenna. r _{s + 1, i} (k) represents the s + 1 th received symbol received at the i th receive antenna.

According to the equation of FIG. 46, r _{s , i} (k) _, which is the s-th reception symbol received at the i-th reception antenna, is the s-th symbol value transmitted through the channel from the 0th transmission antenna to the i-th reception antenna, and the 1st In the transmitting antenna, the i-th receiving antenna is the sum of the s-th symbol value transmitted through the channel and the sum of the channel noise of each channel (n _s (k)).

In addition, r _{s + 1, i} (k), which is the s + 1 th received symbol received at the i th receive antenna, is the s + 1 th symbol value transmitted through the channel from the 0 th transmit antenna to the i th receive antenna, and the first transmit It is the sum of the s + 1th symbol value transmitted through the channel and the sum of the channel noise of each channel (n _s (k)).

47 is a diagram illustrating a specific example of FIG. 46 as an embodiment according to the present invention. 47 is an example of decoding when a transmitter transmits data by multiple input / output encoding using the STBC method, and the transmitter transmits data using two transmit antennas and receives through one antenna at the receiver. to be. That is, this is a case of receiving data transmitted by using one receiving antenna.

When two transmitting antennas are used at the transmitting side and one antenna is used at the receiving side, there may be two transmission channels.

H ₀ and s ₀ in the above equations represent the transmission channel response from the transmitting antenna 0 to the receiving antenna and the symbols transmitted from the transmitting antenna 0, respectively, and h ₁ and s ₁ are received from the transmitting antenna 1 respectively. The transmission channel response to the antenna and the symbol transmitted by the first antenna at the transmitting side are shown. '*' Represents a complex conjugate, and s ₀ 'and s ₁ ' in the following formulas represent a restored symbol.

And r ₀ and r ₁ represent symbols received at the receiving antenna at t time and symbols received at the receiving antenna at t + T time after the transmission period T, respectively, and n ₀ and n ₁ are the respective reception times. Denotes the sum of channel noise of each transmission path.

As shown in Equation 47 of FIG. 47, the signal received by the receiving antenna may be expressed as a value obtained by adding a value through which the signal transmitted from each transmitting antenna has experienced each transmission channel. The recovered symbol is calculated using the received value and each channel response value.

Hereinafter, the signal processing from the multiple input / output decoder 4540 to the forward error correction decoder 4490 is the same as described with reference to FIG. 41.

48 is a flowchart illustrating a signal transmission method according to an embodiment of the present invention. The flowchart is an example of using a multiple mapping method among the embodiments, and for the convenience of description, the description of the remaining embodiments will be omitted.

Forward error correction encoding is performed on the input data so that the receiving side can detect and correct a transmission error (S4800). For example, LDPC encoding may be used as an inner encoder for the forward error correction encoding, and BCH encoding may be used as an outer encoder for preventing an error floor.

Interleaving is performed on the encoded data so as to be robust to burst errors in the transmission channel, and the interleaved data is converted into symbol data according to multiple mappings (S4810). The multiple mapping scheme may be used by mixing various mapping schemes.

In order to make the symbol data robust to frequency selective fading of a channel, precoding is performed such that the mapped symbol data is distributed to a plurality of output symbols in a frequency domain (S4820). The symbol data are interleaved (S4830) and output.

Thus, reducing the likelihood that all information is lost to fading when undergoing a frequency selective fading channel, ensures that the distributed symbol data does not experience the same frequency selective fading. The interleaving may use a convolution interleaver, a block interleaver, etc., which may be selected according to an implementation example.

The interleaved data is converted into a transmission frame, modulated, and then transmitted (S4840). For example, in the case of a method of estimating a channel using the determined symbol data, frame data may not be inserted in the frame conversion step, or pilot symbols may be inserted only for symbol data having a large constellation size to form frame data. have.

If the signal transmission / reception system is applied to a signal transmission / reception system instead of a single input / output method, the interleaved symbol data may be converted into a transmission frame after multiple input / output encoding so as to be transmitted through a plurality of antennas. The number of antennas can be the number of possible data transmission paths. In the case of the spatial diversity method, data of the same information is transmitted in each path, and in the case of the spatial multiplexing method, different data is transmitted in each path.

49 is a flowchart illustrating a signal receiving method according to an embodiment of the present invention. The flowchart is an example of a reception method corresponding to the signal transmission method of 48.

The signal receiving apparatus receives and synchronizes a signal transmitted from the transmitting apparatus, and demodulates the frame data (S4900).

After parsing the demodulated frame data, the parsed data is deinterleaved in the reverse of the interleaved method in the signal transmission apparatus (S4910). In the case of estimating a channel using the determined symbol data, a pilot symbol may not be inserted in the frame data, or only symbol data having a large constellation size may be inserted. In this case, the pilot symbol may not be extracted from the frame data, or the pilot symbol may be extracted only for symbol data having a large constellation size. The channel may be estimated using the received symbol data and the determined symbol data, and an equalization process may be performed to compensate for channel distortion.

The data sequence of which the order is restored by the deinterleaving is decoded in the inverse of the precoding scheme, thereby restoring original symbol data dispersed in a plurality of symbol data in the frequency domain (S4920).

The decompressed symbol data is demultiplexed to decode the corresponding bit data by multiple demapping and deinterleaved the bit data to restore the original bit data (S4930).

Then, forward error correction decoding is performed on the data whose order is restored, thereby detecting a transmission error and correcting the error (S4940). For example, LDPC decoding may be used for the forward error correction decoding, and BCH decoding may be used as an outer decoder for preventing an error floor.

If the signal transmission / reception system is applied to a multiple input / output system instead of a single input / output method, the parsed frame data is demultiplexed and then deinterleaved. In this case, the transmission path of the received data is divided to perform multiple input / output decoding.

The signal transceiving method and the signal transceiving apparatus are not limited to the above examples, and may be applied to all signal transceiving systems such as broadcasting or communication.

The present invention is not limited to the above-described embodiments, and as can be seen in the appended claims, modifications can be made by those skilled in the art to which the invention pertains, and such modifications are within the scope of the present invention.

As described above, according to the signal transmission / reception method and the signal transmission / reception apparatus of the present invention, it is easy to switch to the proposed signal transmission / reception system using an existing signal transmission / reception network network, and it is possible to reduce the cost.

In addition, the data rate can be improved based on the SNR gain, and channel estimation can be performed for a transmission channel having a long delay spread, thereby increasing the signal transmission distance. Therefore, there is an effect that can increase the signal transmission and reception performance of the overall transmission and reception system.

In addition, when using a multiple mapping scheme or a multiple coding scheme, there is an effect that the transmission efficiency can be increased by adjusting the relationship between the required SNR and the transmission rate.

Claims (60)

A bit stream distributor distributing input bit data to at least one mapper; A mapping unit including at least one mapper for mapping and distributing the distributed bit data into symbol data according to a corresponding mapping scheme; And And a symbol merging unit for arranging symbol data output from each mapper of the mapping unit and outputting one symbol data string. The method of claim 1, Each mapper of the mapping unit maps the input bit data into symbol data according to a different mapping scheme, and outputs the signal. The method of claim 1, The symbol merging unit, And interleaving the symbol data output from the respective mappers and outputting one symbol data string. A bit stream distributor distributing input bit data to at least one encoder; An encoding unit including at least one encoder for encoding and distributing the distributed bit data according to a corresponding encoding method; And And a data merger for outputting one bit data string by aligning bit data output from each encoder of the encoder. The method of claim 4, wherein Each encoder of the encoding unit encodes and outputs the input bit data according to a different encoding scheme. The method of claim 4, wherein The data merging unit, And an interleaving bit data output from each encoder to output one bit data string. A forward error correcting unit for encoding an input data so as to detect and correct an error; A first interleaver for interleaving the error correction encoded data; And And a multi-mapper which divides and distributes the interleaved data to map the symbol data according to at least one mapping scheme, and aligns the mapped symbol data to output a symbol data string. The method of claim 7, wherein The multi-mapper, A bit stream distributor distributing input bit data to at least one mapper; A mapping unit including at least one mapper for mapping and distributing the distributed bit data into symbol data according to a corresponding mapping scheme; And And a symbol merging unit for arranging symbol data output from each mapper of the mapping unit and outputting one symbol data string. The method of claim 7, wherein The forward error correction unit, An outer encoder for encoding and outputting the input bit data so as to prevent a transmission error of the input bit data; And And an inner encoder for re-encoding and outputting the encoded and output data according to a corresponding encoding scheme. The method of claim 9, The inner encoder, A bit stream distributor distributing input bit data to at least one encoder; An encoding unit including at least one encoder for encoding and distributing the distributed bit data according to a corresponding encoding method; And And a data merger for outputting one bit data string by aligning bit data output from each encoder of the encoder. An outer encoder for encoding and outputting the input bit data so as to prevent a transmission error of the input bit data; A multiple encoder for encoding the output data by using at least one encoding scheme and sorting the encoded bit data to output a bit data string; A first interleaver for interleaving the output bit data stream; And And a symbol mapper which maps the interleaved data to symbol data and outputs the symbol mapper. The method of claim 11, The multiple encoder, A bit stream distributor distributing input bit data to at least one encoder; An encoding unit including at least one encoder for encoding and distributing the distributed bit data according to a corresponding encoding method; And And a data merger for outputting one bit data string by aligning bit data output from each encoder of the encoder. A forward error correcting unit for encoding an input data so as to detect and correct an error; A first interleaver for interleaving the error correction encoded data; A multi-mapper which maps the interleaved data into symbol data using at least one or more mapping schemes, aligns the mapped symbol data, and outputs a symbol data string; A fading coding unit for distributing the symbol data stream in a frequency domain and interleaving the distributed data to output the interleaved data; And And a frame forming unit configured to form the faded coded symbol data as frame data according to a transmission method. The method of claim 13, The frame forming unit, A signal transmission device for forming frame data by inserting symbol data to be used as pilot symbols among symbol data to be transmitted at a pilot insertion position. The method of claim 13, The frame forming unit, A signal transmission apparatus for forming frame data by inserting symbol data to be used as pilot symbols among symbol data to be transmitted only in a part of pilot insertion positions. The method of claim 13, The forward error correction unit, An outer encoder for encoding and outputting the input bit data so as to prevent a transmission error of the input bit data; And And an inner encoder for re-encoding and outputting the encoded and output data according to a corresponding encoding scheme. The method of claim 16, The inner encoder, A bit stream distributor distributing input bit data to at least one encoder; An encoding unit including at least one encoder for encoding and distributing the distributed bit data according to a corresponding encoding method; And And a data merger for outputting one bit data string by aligning bit data output from each encoder of the encoder. Distributing the input bit data to at least one mapper; Mapping bit data distributed to each mapper to symbol data according to a corresponding mapping method and outputting the mapped bit data; And And sorting the mapped symbol data to output one symbol data string. Distributing the input bit data to at least one encoder; Encoding and outputting bit data distributed to each encoder according to a corresponding encoding scheme; And And outputting one bit data string by aligning each of the output bit data. A forward error correction step of encoding the input data so that an error can be detected and corrected; Interleaving the error correction encoded data; And Mapping the interleaved data to symbol data using at least one mapping scheme, and aligning the mapped symbol data to output a symbol data string. Encoding and outputting the input bit data to prevent a transmission error of the input bit data; Encoding the output data using at least one encoding scheme and sorting the encoded bit data to output a bit data string; Interleaving the output bit data stream; And And mapping and outputting the interleaved data to symbol data. Encoding and outputting the input bit data to prevent a transmission error of the input bit data; Encoding the output data using at least one encoding scheme and sorting the encoded bit data to output a bit data string; Interleaving the output bit data stream; And Mapping the interleaved data to symbol data using at least one mapping scheme, and aligning the mapped symbol data to output a symbol data string. A forward error correction step of encoding the input data so that an error can be detected and corrected; Interleaving the error correction encoded data; Mapping the interleaved data into symbol data using at least one mapping scheme, and sorting the mapped symbol data to output a symbol data string; Distributing the symbol data stream in a frequency domain, interleaving the distributed data, and outputting the interleaved data; And And forming the fading coded symbol data into frame data according to a transmission scheme. The method of claim 23, The frame forming step, A signal transmission method for forming frame data by inserting symbol data to be used as pilot symbols among symbol data to be transmitted at a pilot insertion position. The method of claim 23, The frame forming step, A signal transmission method for forming frame data by inserting symbol data to be used as pilot symbols among symbol data to be transmitted only in a part of pilot insertion positions. The method of claim 23, The forward error correction step, And encoding the input data using at least one encoding scheme, and sorting the encoded bit data to output a bit data string. A symbol distributor distributing input symbol data to at least one demapper; A demapping unit including at least one demapper for demapping and distributing the distributed symbol data into bit data according to a corresponding demapping scheme; And And a bit stream recovery unit for outputting one bit data string by aligning bit data output from each demapper of the demapping unit. The method of claim 27, Each demapper of the demapping unit demaps input symbol data into bit data according to a different demapping scheme and outputs the demapper. The method of claim 27, The symbol distribution unit, And deinterleaving the input symbol data to distribute symbol data whose order is restored. A bit stream distributor distributing input bit data to at least one decoder; A decoder comprising at least one decoder for decoding and outputting the distributed bit data according to a corresponding decoding scheme; And And a bit stream recovery unit for outputting one bit data string by aligning bit data output from each decoder of the decoding unit. The method of claim 30, Each decoder of the decoding unit decodes the input bit data according to a different decoding scheme and outputs the signal. The method of claim 30, The bit stream distribution unit, And deinterleaving the input bit data to distribute bit data whose order is restored. A multiple demapper for dividing and distributing input symbol data to demap bit data according to at least one or more demapping schemes, and aligning the demapped bit data to output a bit data string; A first deinterleaver to deinterleave the output bit data stream to restore order; And And a forward error correction decoder configured to detect and correct an error by decoding the deinterleaved data. The method of claim 33, wherein The multiple demapper, A symbol distributor distributing input symbol data to at least one demapper; A demapping unit including at least one demapper for demapping and distributing the distributed symbol data into bit data according to a corresponding demapping scheme; And And a bit stream recovery unit for outputting one bit data string by aligning bit data output from each demapper of the demapping unit. The method of claim 33, wherein The forward error correction decoder, An inner decoder that decodes the deinterleaved data to detect and correct errors; And And an outer decoder for decoding and outputting the bit data output from the inner decoder again according to a corresponding decoding scheme. 36. The method of claim 35 wherein The inner decoder, A bit stream distributor distributing input bit data to at least one decoder; A decoder comprising at least one decoder for decoding and outputting the distributed bit data according to a corresponding decoding scheme; And And a bit stream recovery unit for outputting one bit data string by aligning bit data output from each decoder of the decoding unit. A symbol demapper for demapping input symbol data into bit data and outputting the bit data; A first deinterleaver for restoring an order by deinterleaving the output bit data stream; A multiple decoder configured to distribute and decode the deinterleaved data to at least one decoding scheme, and to align the decoded bit data to output a bit data string; And And an outer decoder to decode and output bit data output from the multiple decoder according to a corresponding decoding scheme. The method of claim 37, wherein The multiple decoder, A bit stream distributor distributing input bit data to at least one decoder; A decoder comprising at least one decoder for decoding and outputting the distributed bit data according to a corresponding decoding scheme; And And a bit stream recovery unit for outputting one bit data string by aligning bit data output from each decoder of the decoding unit. A frame parsing unit for extracting symbol data and pilot included in a pilot insertion position of the received frame data and restoring symbol data included in the frame data; The channel is estimated using the generated pilot and the pilot extracted from the pilot insertion position, and the channel is determined using the equalized value of the symbol data extracted from the pilot insertion position and the determined value of the symbol data extracted from the pilot insertion position. A channel estimator for estimating a value; An equalizer for equalizing the reconstructed symbol data using the channel information estimated by the channel estimator; And A signal including a multiple demapper that divides and equalizes the equalized symbol data to determine a symbol value according to at least one or more demapping schemes, calculates bit data corresponding to each of the determined values, and outputs one bit data string Receiving device. The method of claim 39, The channel estimator, A first channel estimator for estimating a channel using an equalized value of the symbol data extracted at the pilot insertion position and a determined value of the symbol data extracted at the pilot insertion position; And And a second channel estimator for estimating a channel using the generated pilot and the pilot extracted from the pilot insertion position. The method of claim 40, The first channel estimator, A determination unit for outputting a determination value of the symbol data extracted at the pilot insertion position; A first operation unit calculating a complex conjugate value of the determination value; A first multiplier configured to multiply and output a value output from the determination unit and a value output from the first operation unit; A second multiplier configured to multiply the value output from the first operator by an equalized value of symbol data extracted at a pilot insertion position; And And a second operator configured to multiply and output an inverse value of the value output from the first multiplier and a value output from the second multiplier. The method of claim 40, The second channel estimator, A pilot generator for generating and outputting a pilot; A third calculation unit calculating a complex conjugate value of the generated pilot; A third multiplier configured to multiply a value output from the pilot generator by a value output from the third calculator; A fourth multiplier configured to multiply a value output from the third operator by a pilot extracted at a pilot insertion position and output the multiplied result; And And a fourth operator configured to multiply and output an inverse value of the value output from the third multiplier and a value output from the fourth multiplier. The method of claim 39, The equalizing unit, And receiving one of the estimated channel information to equalize the channel. The method of claim 39, The equalizing unit, And a signal equalizer using the estimated interpolation value of the channel information. The method of claim 39, The equalizing unit, An interpolator for interpolating and outputting the input channel transfer function value to a value of a full bandwidth; A fifth operator calculating a conjugate complex value of the channel transfer function output from the interpolator; A fifth multiplier configured to multiply and output a value output from the interpolator and a value output from the fifth operator; A sixth multiplier configured to multiply and output the value output from the fifth operation unit and the input symbol data; And And a sixth operator configured to multiply and output an inverse value of the value output from the fifth multiplier and a value output from the sixth multiplier. A frame parsing unit for parsing the received frame data and restoring and outputting symbol data; A channel estimator estimating a channel using the equalized value of the symbol data and the determined value of the symbol data; An equalizer for equalizing the reconstructed symbol data using the channel information estimated by the channel estimator; And And a symbol demapper configured to determine a symbol value of the equalized symbol data according to a corresponding demapping scheme, and to calculate and output bit data corresponding to the determined value. The method of claim 46, The channel estimator, A determination unit which outputs a determination value of the input symbol data; A first operation unit calculating a complex conjugate value of the determination value; A first multiplier configured to multiply and output a value output from the determination unit and a value output from the first operation unit; A second multiplier configured to multiply and output an equalized value of the symbol data by a value output from the first operator; And And a second operator configured to multiply and output an inverse value of the value output from the first multiplier and a value output from the second multiplier. The method of claim 46, The equalizing unit, An interpolator for interpolating and outputting the input channel transfer function value to a value of a full bandwidth; A fifth operator calculating a conjugate complex value of the channel transfer function output from the interpolator; A fifth multiplier configured to multiply and output a value output from the interpolator and a value output from the fifth operator; A sixth multiplier configured to multiply and output the value output from the fifth operation unit and the input symbol data; And And a sixth operator configured to multiply and output an inverse value of the value output from the fifth multiplier and a value output from the sixth multiplier. The method of claim 46, And a channel state estimator for estimating a channel state of a transmission channel of each subcarrier using the equalized value of the symbol data. The method of claim 49, The channel state estimator, A signal receiving device for estimating that a channel state is good if the SNR gain of a channel is high. The method of claim 49, The channel state estimator, Signal receiver that estimates that the channel status is good when the LLR (Log-Likelihood Ratio) value of the channel is high. The method of claim 46, The channel estimator, And a channel state estimator receiving information on a channel having a good channel state, and estimating a channel using an equalized value of the symbol data received through the channel and a determined value of the symbol data. The method of claim 46, The symbol demapper is And dividing and dividing the input symbol data into bit data according to at least one demapping scheme, and outputting a bit data string by aligning the demapped bit data. Distributing the input symbol data to at least one demapper; Demapping and distributing the distributed symbol data into bit data according to a corresponding demapping scheme; And And arranging the de-mapped and output bit data to output one bit data string. Distributing the input bit data to at least one decoder; Decoding and outputting the distributed bit data according to a corresponding decoding scheme; And And arranging the decoded and output bit data to output one bit data string. Dividing and dividing the input symbol data into bit data according to at least one demapping scheme, and aligning the demapped bit data to output one bit data string; Restoring an order by deinterleaving the output bit data stream; And And a forward error correction step of detecting and correcting errors by decoding the deinterleaved data. Demapping the input symbol data into bit data and outputting the bit data; Restoring an order by deinterleaving the output bit data stream; Dividing and distributing the deinterleaved data to decode according to at least one decoding scheme, and sorting the decoded bit data to output one bit data string; And And decoding and outputting the output bit data string again according to a corresponding decoding scheme. Extracting the symbol data and the pilot included in the pilot insertion position of the received frame data and restoring the symbol data included in the frame data; The channel is estimated using the generated pilot and the pilot extracted at the pilot insertion position, and the channel is determined using the equalized value of the symbol data extracted at the pilot insertion position and the determined value of the symbol data extracted at the pilot insertion position. Estimating; Equalizing the reconstructed symbol data using the estimated channel information; And Dividing and equalizing the equalized symbol data to determine a symbol value according to at least one demapping scheme, calculating bit data corresponding to each of the determined values, and outputting one bit data string; . Parsing the received frame data, restoring and outputting symbol data; Estimating a channel using the equalized value of the symbol data and the determined value of the symbol data; Equalizing the reconstructed symbol data using the channel information estimated by the channel estimator; And Determining a symbol value according to a corresponding demapping scheme, and calculating and outputting bit data corresponding to each of the determined values. Parsing the received frame data, restoring and outputting symbol data; Estimating a channel state of a transmission channel of each subcarrier using the equalized value of the symbol data; Estimating a channel using an equalized value of symbol data received as a channel having a good channel state among the channels estimated in the channel state estimating step and a determination value of the symbol data; Equalizing the reconstructed symbol data using the channel information estimated by the channel estimator; And Determining a symbol value according to a corresponding demapping scheme, and calculating and outputting bit data corresponding to each of the determined values.

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