KR20080102536A

KR20080102536A - Method for alinging wafer in semiconductor fabricating equpiment

Info

Publication number: KR20080102536A
Application number: KR1020070049129A
Authority: KR
Inventors: 형용주
Original assignee: 삼성전자주식회사
Priority date: 2007-05-21
Filing date: 2007-05-21
Publication date: 2008-11-26

Abstract

The wafer alignment method in the semiconductor manufacturing facility of the present invention comprises the steps of aligning the loaded wafer; Determining whether an alignment failure occurs during the alignment of the wafer using the designated alignment mark; If it is determined that a misalignment does not occur, performing an exposure process; If a misalignment occurs as a result of the determination, aligning the wafers by using the alignment marks of the N-th preceding process previously input to the process program; And judging whether a misalignment occurs while aligning the wafer using the alignment mark of the Nth preceding process. If the misalignment does not occur as a result of the determination, the exposure process is performed. And unloading the defective wafer and then performing the exposure process on the remaining wafers. According to the present invention, even if an alignment defect occurs due to damage of the alignment mark of the process, by using a plurality of alignment marks already formed while performing the preceding process as replaceable alignment marks, an operator can analyze the error log, rework, Since there is no need to perform process program modifications, there is an effect of effectively preventing process delays and increasing productivity.

Description

Method for alinging wafer in semiconductor fabricating equpiment

1 is a wafer alignment method in a conventional semiconductor manufacturing facility

2 is a conceptual diagram of a semiconductor manufacturing facility

3 is a look-up table formed in the storage unit of FIG.

4 is a flowchart illustrating a wafer alignment method in a semiconductor manufacturing facility according to the present invention.

* Description of main parts

100: exposure unit

200: aligner

300: operation / display unit

400: storage unit

500: central processing unit

600: data bus

700: control bus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer alignment method in a semiconductor manufacturing facility, and more particularly, when an exposure process is performed on a wafer in a state in which a plurality of alignment mark coordinates formed on the wafer are previously stored in a process program during the preceding process. The present invention relates to a wafer alignment method in a semiconductor manufacturing facility in which a wafer alignment is performed using alignment marks of a previously stored prior process when a wafer alignment failure occurs due to a poor formation of the alignment mark formed in the last preceding process.

In recent years, semiconductor products, which have been rapidly developed, have been developed in the direction of increasing the number of data that can be processed per unit time by storing more data in a unit area, and thus, various industries such as electricity, electronics, It acts as a vehicle to promote the industrial development of computer, information and communication.

In order to produce a semiconductor product that plays such a role, a very complicated and precise semiconductor manufacturing process, for example, a semiconductor thin film forming process such as a photolithography process, a deposition process, an etching process, an ion implantation process, and the like must be performed.

These semiconductor manufacturing processes all have a subsequent process relationship with the preceding process, that is, the patterns of the semiconductor thin film formed in the subsequent process are all related to the semiconductor thin film pattern formed in the preceding process.

This means that the alignment of the preceding semiconductor thin film pattern and the subsequent semiconductor thin film pattern is important. Particular attention should be paid to the alignment of the wafer in the exposure apparatus mainly belonging to the preceding process for forming the thin film pattern.

In order to prevent the misalignment of the pattern by aligning the wafer at a predetermined position in the exposure apparatus, a scribe line formed between the semiconductor chip and the semiconductor chip of the wafer and prepared to singulate the semiconductor chip is a thin film formed as a subsequent process proceeds. Align marks are formed to align the pattern with the thin film pattern formed in the previous process.

In the prior art, when a plurality of semiconductor thin film processes have been performed, that is, a plurality of alignment marks are formed, the last alignment mark formed is damaged due to various reasons or fails to function as an alignment mark. The wafer of Align Fail is unloaded from the process progress position.

FIG. 1 illustrates a wafer alignment method in a conventional semiconductor manufacturing facility. As illustrated in FIG. 1, conventionally, an error log is analyzed when a misalignment occurs, a rework sheet comment is created, and a wafer rework is illustrated. Re-run the alignment process, with operator call response, MC or job remediation. In this case, it takes too much time to rework the misaligned wafer and start the process again, which leads to a problem that the productivity is lowered.

Accordingly, the present invention has been made in view of such a conventional problem, and an object of the present invention is to accurately process a wafer while minimizing process down time when the alignment mark formed in the preceding process, which is essential for the subsequent process, is damaged by various causes. To allow alignment to be performed.

Other objects of the present invention will become more apparent from the following detailed description of the invention.

Such a wafer alignment method in a semiconductor manufacturing facility for realizing the object of the present invention comprises the steps of aligning the loaded wafer; Determining whether misalignment occurs while aligning the wafer using the designated alignment mark; If it is determined that a misalignment does not occur, performing an exposure process; If a misalignment occurs as a result of the determination, aligning the wafers by using the alignment marks of the N-th preceding process previously input to the process program; And judging whether a misalignment occurs while aligning the wafer using the alignment mark of the Nth preceding process. If the misalignment does not occur as a result of the determination, the exposure process is performed. And unloading (or rejecting) the defective wafer and then performing the exposure process on the remaining wafers.

Hereinafter, a wafer alignment method in a semiconductor manufacturing apparatus according to the present invention will be described with reference to the accompanying drawings.

2 is a conceptual diagram of a semiconductor manufacturing facility, FIG. 3 is a look-up table formed in the storage unit of FIG. 2, and FIG. 4 is a flowchart illustrating a wafer alignment method in the semiconductor manufacturing facility according to the present invention.

First, prior to explaining the wafer alignment method in the semiconductor manufacturing equipment according to the present invention will be described with reference to Figures 2 and 3 attached to the semiconductor manufacturing equipment according to the present invention. In the present invention, an exposure apparatus will be described as a preferred embodiment of the semiconductor manufacturing apparatus.

The exposure apparatus according to the present invention generally includes an exposure unit 100 that performs exposure to a wafer, and an aligner that performs alignment of the wafer loaded on the exposure unit 100 before the exposure unit 100 performs exposure. 200 and coordinate information of the alignment mark and information on the number of the alignment marks necessary for the aligner 200 to perform wafer alignment, and the aligner 200 is configured by the process information of the plurality of alignment marks. A storage unit 300 in which a program for selecting alignment marks required for performing alignment is stored, and an operation / display unit 400 and an exposure facility 100 for allowing an operator to manipulate the alignment process and monitor the results. Consists of a central processing unit 500 to control the. Reference numeral 600 denotes a data bus for controlling the flow of data signals, and 700 is a control bus for controlling the flow of control signals.

3, a look up table 310 of data stored in the storage unit 400 is illustrated.

In one embodiment, the look-up table 310 stores process type data and alignment mark coordinate data.

In one embodiment, the process progress data is input and stored in the first column. In the address where the process progress data is input and stored, 11-16 processes have already been performed and 17 processes are currently in progress.

In the first column of the look-up table 310, coordinate data of each unique alignment mark is input. The alignment mark coordinates in step 11 are (X ₁ , Y ₁ ), and the alignment marks in step 12 The coordinate is (X ₂ , Y ₂ ), the alignment mark coordinates in step 13 are (X ₃ , Y ₃ ), the alignment mark coordinates in step 14 is (X ₄ , Y ₄ ), and in step 15 coordinates of the alignment mark is a (X _5, Y _5), and the coordinates of the alignment mark 16 in the process (X _6, Y _6).

In the present 17 process, the alignment mark coordinates in the 16 process are aligned using (X ₆ , Y ₆ ).

When the exposure process is performed by the exposure apparatus having such a configuration, a method of performing wafer alignment will be described with reference to FIGS. 3 and 4.

First, in order to perform the exposure process by the exposure facility, when the wafer to be subjected to the exposure process is loaded in the exposure unit 100 (S110), the alignment of the wafer is performed by the aligner 200 (S120). In this case, the aligner 200 performs alignment by referring to alignment mark coordinate data of the look-up table 310 illustrated in FIG. 3.

For example, when the current process is a 17 process, the alignment is an alignment mark formed during the process 16, which is a preceding process immediately before the 17 process, becomes a reference alignment mark, so that the aligner 200 is not. After selecting the alignment mark with reference to the in mark coordinate (X ₅ , Y ₅ ), the alignment is performed.

At this time, the aligner determines whether the designated alignment mark coordinates (X ₅ , Y ₅ ) are damaged and an alignment failure of the wafer occurs (S130).

As a result of determination, when no alignment defect occurs, the exposure process is performed (S140). On the other hand, when misalignment occurs as a result of the determination, the wafer is aligned using the alignment mark coordinates (X ₅ , Y ₅ ) of the first preceding process previously input to the process program (S150).

At this time, it is determined whether an alignment failure of the wafer occurs (S160).

As a result of determination, when no alignment defect occurs, the exposure process is performed (S140). On the other hand, when misalignment occurs as a result of the determination, the wafer is aligned using the alignment mark coordinates (X ₅ , Y ₅ ) of the second, third, and Nth preceding processes sequentially input to the process program. do. At this time, if the misalignment of the N-th preceding process does not occur, the process ends through the exposure process (S170).

If misalignment occurs in the Nth preceding process, the unaligned wafer is unloaded and the misaligned wafer is sent to a reject carrier (not shown). Can be.

As described in detail above, when the alignment of the wafer is performed, even if an alignment defect occurs due to damage of the corresponding alignment mark for performing the alignment, a plurality of alignment marks already formed while performing the preceding process may be replaced. By using it as an alignment mark, the operator does not need to perform error log analysis, reworking, and process program modification. Therefore, the process delay can be effectively prevented to increase productivity.

Claims

Aligning the loaded wafer;

Determining whether misalignment occurs while aligning the wafer using the designated alignment mark;

If it is determined that a misalignment does not occur, performing an exposure process;

If a misalignment occurs as a result of the determination, aligning the wafers by using the alignment marks of the N-th preceding process previously input to the process program;

The alignment mark of the Nth preceding process is used to determine whether misalignment occurs during the alignment of the wafer. If the misalignment does not occur as a result of the determination, the exposure process is performed. If the misalignment occurs, the misalignment occurs. And unloading the wafer and then performing the exposure process on the remaining wafers.

The method of claim 1,

Determining whether misalignment occurs while aligning wafers using the alignment mark of the Nth preceding process, unloading the misalignment wafer and sending the misalignment wafer to the reject carrier. Wafer alignment method in a semiconductor manufacturing facility characterized by the above-mentioned.