KR20080100110A - Method for manufacturing metal option of semiconductor device and layout method thereof - Google Patents

Method for manufacturing metal option of semiconductor device and layout method thereof Download PDF

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Publication number
KR20080100110A
KR20080100110A KR1020070046256A KR20070046256A KR20080100110A KR 20080100110 A KR20080100110 A KR 20080100110A KR 1020070046256 A KR1020070046256 A KR 1020070046256A KR 20070046256 A KR20070046256 A KR 20070046256A KR 20080100110 A KR20080100110 A KR 20080100110A
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KR
South Korea
Prior art keywords
metal
line
lines
option
layer
Prior art date
Application number
KR1020070046256A
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Korean (ko)
Inventor
허은호
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070046256A priority Critical patent/KR20080100110A/en
Publication of KR20080100110A publication Critical patent/KR20080100110A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The metal option is formed on the contact region connecting metal lines. The arrangement area according to the connection of the metal lines is reduced. Moreover, the wirings is arranged in the space in which is formed according to shrink arrangement area. The method of forming metal option in the semiconductor device is provided. The first step is for arranging a plurality of first metal lines(20~22) parallelly formed in the first layer. The step is for arranging metal options for contact of the first metal lines and the second metal line the orthogonal direction to the first metal lines. The step is for arranging the second metal line which commonly is contacted with metal options in the second layer of the metal option.

Description

Method for manufacturing metal option of semiconductor device and layout method thereof

1A and 1B are cross-sectional views illustrating the formation of metal options according to the prior art.

2 is a cross-sectional view showing the placement of a metal option according to a prior art embodiment.

3 is a cross-sectional view showing the placement of a metal option according to another embodiment of the prior art.

4 is a cross-sectional view illustrating the placement of a metal option in accordance with an embodiment of the present invention.

5 is a cross-sectional view showing the placement of a metal option in accordance with another embodiment of the present invention.

The present invention relates to a semiconductor device, and more particularly, to a method of forming a metal option of a semiconductor device and a layout method thereof.

In general, a semiconductor device controls a connection state of wirings by using focused ion beam (FIB) equipment.

This is to sputter a specific part of the metal line used as a wiring to form a metal option layer (Metal Option layer) to operate the specific part as a switch.

FIG. 1 illustrates metal lines in which such metal options are formed, and FIG. 1A illustrates metal lines 12 overlapping orthogonal to these metal lines 10 separately disposed on the same layer. The metal line 12 is formed with a metal option 16 that becomes a switch in an open state.

In FIG. 1B, metal lines 12 are formed to overlap each other so as to be orthogonal to them on different metal lines 10 separated on the same layer. In the metal line 12, a metal option 18, which is a switch in a closed state, is formed.

That is, FIG. 1B is as shown in FIG. 1A by removing the metal option by FIB.

On the other hand, Figure 2 (a) shows an embodiment in which the metal option is arranged in accordance with the connection of the conventional metal lines.

First, different metal lines 20 to 22 are arranged in parallel, and the metal lines 22 are arranged up and down on a straight line, respectively, in a state where the metal lines 22 are broken in a space spaced by a predetermined distance between the metal lines 20 and 21. do.

Meanwhile, the metal lines 20 to 22 formed as described above are the lowest layers formed of the M0 layer, and the metal lines 23 of the M1 layer are formed on the metal lines 20 and 21. It is formed to overlap at right angles to the direction. In addition, the metal line 23 overlaps both ends of the metal line 22 which is broken, and has a region extending by a predetermined length in the longitudinal direction of the metal line 22.

Here, the metal line 23 is connected to the metal lines 20 and 21 by forming a contact in an area overlapping the metal lines 20 and 21. In addition, a contact is formed in the region overlapping the metal line 22 and connected to each other.

Meanwhile, the metal line 23 includes metal options 25 and 26 between a region overlapping the metal line 22 and an integral portion formed orthogonal to the metal lines 20 and 21.

The broken upper line of the metal line 22 is connected to the metal line 23 by forming a switch closed by the metal option 25, and the broken lower line of the metal line 22 is connected by the metal option 26. A switch in an open state is formed to have a state of being disconnected from the metal line 23.

On the other hand, Figure 2 (b) is a circuit diagram showing whether the metal lines of (a) are connected by a metal option, the metal line 20 and the metal line 21 is connected by a metal line 23, The upper line of the metal line 22 is connected to the metal line 23 by the switch SW1, and the lower line of the metal line 22 is disconnected from the metal line 23 by the switch SW2. .

Figure 3 (a) shows another embodiment in which the metal option is arranged in accordance with the connection of the conventional metal lines.

First, the metal lines 30 and 31 extending in parallel in the longitudinal direction are formed to be spaced apart by a predetermined distance, and the metal lines 32 and 33 overlap the metal lines 30 and 31 so as to overlap. .

Here, the metal lines 30 and 31 are metal lines of the lowest layer of M0, and the metal lines 32 and 33 are upper layers that can be formed adjacent to and connected to the metal lines 30 and 31 layer.

The metal lines 32 and 33 are formed by dividing into two metal lines 32 and 33 spaced by a predetermined distance to be connected to the metal lines 30 and 31, and between the metal lines 32 and 33. The metal option 36 is an area for connecting the metal line 33 and the metal line 31 to the metal line 32.

On the other hand, a metal option 35 connected to the metal line 30 is formed in one body of the metal line 32.

The metal line 32 extends in the direction of the metal line 30 in a space overlapping the metal line 30 to form a contact, and the metal line 33 overlaps the metal line 31 in the space overlapping the metal line 31. The contact is formed in the region extending in the direction.

On the other hand, Figure 3 (b) is a circuit diagram showing that the metal lines of (a) are connected by a metal option, the metal line 30 is connected by a switch (SW3) formed in the metal line 32, The metal line 31 is not connected to the metal line 33 with the switch SW4 connected to the metal line 33 open.

On the other hand, the upper metal lines connected to the lower metal lines have a structure connected to the metal option, so that the additional metal lines may be different from the area in which the contact is formed and the metal option areas formed for each metal line. It reduces the routing space of the wiring and adversely affects the highly integrated semiconductor device.

An object of the present invention for solving the above problems is to reduce the metal option and the space in which the metal lines are formed by the connection of the metal lines.

Another object of the present invention is to secure a routing space of wirings.

The method of forming a metal option of a semiconductor device and a layout method thereof according to the present invention for achieving the above object is characterized in that the metal option for electrical switching between metal lines located on different layers is formed using the contact between the metal lines. do.

The invention also includes forming at least one first metal line in a first layer; Forming a metal option on the first metal line in an area for making contact with a second metal line of another layer; And forming the second metal line to make contact with the metal option in a second layer on the metal option.

The present invention also provides a method comprising: a first step of arranging a plurality of first metal lines formed parallel to each other on a first layer; Disposing metal options for making the first metal lines contact the second metal line of another layer at the same position in the direction orthogonal to the longitudinal direction of the first metal lines; And disposing the second metal line in common contact with the metal options in a second layer on the metal options.

The present invention also provides a method comprising the steps of: arranging a pair of parallel first and second metal lines in a first layer and longitudinally broken third metal lines therebetween; Disposing metal options on the both ends of the third metal line and corresponding first and second metal lines to make contact with the fourth metal line of another layer; And disposing the fourth metal line in common contact with the metal options in a second layer on the metal options.

Hereinafter, a method of forming a metal option of a semiconductor device according to the present invention, a layout method thereof, and a preferred embodiment of a switch of the semiconductor device will be described in detail with reference to the accompanying drawings.

The semiconductor device according to the present invention includes two or more metal lines positioned on different layers, and electrical switching between two metal lines disposed on the different layers is made of a metal option disposed in an area where a contact is formed.

Referring to FIG. 4A, a semiconductor device according to an embodiment of the present invention includes a plurality of metal lines 20 to 21 formed in an MO layer and metal lines 23 formed in an M1 layer. The metal line 22 has metal options 45 and 46 to be electrically connected to the metal line 23 in a broken state. Here, the M0 layer is an adjacent metal layer formed below the M1 layer.

The three metal lines 20 to 22 formed in the M0 layer are formed in parallel with each other, and the metal lines 22 broken up and down are arranged in a space separated by a predetermined distance between the metal lines 20 and 21, respectively. .

The metal lines 23 of the M1 layer are disposed to be orthogonal to the length direction of the metal lines 20, 21, and 22, and have contacts 24 in regions overlapping the metal lines 20, 21, and 22, respectively. .

On the other hand, the metal line 23 has a region that extends up and down by a predetermined length in the longitudinal direction of the metal line 22 at both ends of the broken metal line 22.

As described above, in the regions where the metal line 23 and the metal line 22 overlap in plan, contacts for connecting to each other are disposed, and between the layers where the contacts of the metal line 22 and the metal line 23 are formed. The metal options 45 and 46 are arranged to determine whether the metal line 22 and the metal line 23 are connected to each other.

Accordingly, the metal lines 23 and the metal options 45 and 46 are formed under the region where the contact for connecting the metal lines 22 is formed, and the metal lines 22 and 23 are formed by the metal options 45 and 46. ) Or disconnected.

Here, the metal line 23 and the upper metal line 22 are connected to each other by forming a metal option 45 which is a switch in a closed state, and the metal line 23 and the lower metal line 22 are in an open state. The metal options 46 which are switches of are formed and are not connected to each other. In other words, no contact is formed.

On the other hand, Figure 4 (b) is the same circuit as Figure 2 (b) previously described, the description of the structure will be omitted.

Through (a) and (b) of FIG. 4, the metal option may be formed without allocating a separate space, and another wiring may be formed in the region d1 used to allocate the existing option layer. It is possible to reduce the area in which the lines are arranged or to be advantageous for the routing of metal lines.

FIG. 5A illustrates an arrangement of metal lines formed of different structures, and includes metal lines 30 and 31 formed on the M0 layer and metal lines 32 formed on the M1 layer. And electrical connection between the metal line 32 and the metal line 32 is made by the metal options 55 and 56.

Here, the metal lines 30 and 31 are formed to extend in parallel in the longitudinal direction with spaces spaced apart by a predetermined distance therebetween, and the metal lines 32 are perpendicular to the metal lines 30 and 31 in a plane. Is placed.

The metal lines 30 and 31 are metal lines of the lower layer of M0, and the metal lines 32 are upper layers that may be formed adjacent to and connected to the metal lines 30 and 31 layer.

On the other hand, the metal line 32 extends by a predetermined area in the direction of the metal lines 30 and 31 in the region overlapping with the metal lines 30 and 31 and overlaps with the contacts.

The metal options 55 and 56 are formed between the spaces where the contacts of the metal lines 30 to 32 are disposed.

The metal line 30 is connected to the metal line 32 through the metal option 55 which is a closed switch, and the metal line 31 is connected to the metal line 56 through the metal option 56 which is a switch in the open state. 32) and breaks.

FIG. 5B is a circuit diagram illustrating the connection of the metal lines of (a), and the same structure as that of FIG. 3B will be omitted.

As shown in FIG. 5A, unlike FIG. 3A, a plurality of metal lines do not need to be formed to be connected to adjacent metal lines, and metal options are not assigned to each metal line.

Therefore, the arrangement area of the metal lines is increased by the area d2 used to allocate the existing metal option, so that other wirings may be formed or the arrangement may be advantageous for the routing of the metal lines.

Therefore, the method of forming a metal option and the layout method of the semiconductor device of the present invention form a metal option in a contact region connecting the metal lines, thereby reducing the arrangement area according to the connection of the metal lines.

In addition, as the arrangement area is reduced, there is an advantage in that it is possible to arrange other wirings in the space formed or to facilitate routing of the wirings.

Claims (4)

The metal option forming method of the semiconductor device, characterized in that the metal option for the electrical switching between the metal line located in different layers is formed by using the contact between the metal line. Forming at least one first metal line in the first layer; Forming a metal option on the first metal line in an area for making contact with a second metal line of another layer; And Forming the second metal line for making contact with the metal option in a second layer above the metal option. A first step of arranging a plurality of first metal lines formed parallel to each other on a first layer; Disposing metal options for making the first metal lines contact the second metal line of another layer at the same position in the direction orthogonal to the longitudinal direction of the first metal lines; And arranging the second metal line in common contact with the metal options on a second layer above the metal options. Disposing a pair of parallel first and second metal lines in the first layer and longitudinally broken third metal lines therebetween; Disposing metal options on the both ends of the third metal line and corresponding first and second metal lines to make contact with the fourth metal line of another layer; And And disposing the fourth metal line in common contact with the metal options on a second layer above the metal options.
KR1020070046256A 2007-05-11 2007-05-11 Method for manufacturing metal option of semiconductor device and layout method thereof KR20080100110A (en)

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KR1020070046256A KR20080100110A (en) 2007-05-11 2007-05-11 Method for manufacturing metal option of semiconductor device and layout method thereof

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9741661B2 (en) 2015-10-23 2017-08-22 Samsung Electronics Co., Ltd. Logic semiconductor devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9741661B2 (en) 2015-10-23 2017-08-22 Samsung Electronics Co., Ltd. Logic semiconductor devices
US10170421B2 (en) 2015-10-23 2019-01-01 Samsung Electronics Co., Ltd. Logic semiconductor devices

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