JP6957123B2 - Vias and semiconductor devices - Google Patents

Description

The present invention relates to vias and semiconductor devices.

In a semiconductor device or the like, the wiring is configured in multiple layers, and it may be necessary to connect the upper wiring and the lower wiring. For example, when the upper wiring 1 and the lower wiring 2 intersect as shown in FIG. 1, a small diameter via 3 is provided at the cross point where the intersection occurs, and the via 3 provides the upper wiring 1 and the lower wiring 2 And connect.

However, since the via 3 has a small diameter, there is a problem that the cross-sectional area is small and the contact resistance is high. Therefore, conventionally, as shown in FIG. 2, in addition to the connection by the small diameter via 3 at the cross point between the upper wiring 1 and the lower wiring 2, the connection is made by the second via 3A. In the case of FIG. 2, a branch line 2A is provided at a required portion of the lower wiring 2, and a via 3A is used to connect the branch line 2A and the upper wiring 1 at a cross point.

With the above configuration, resistance can be reduced, and by connecting at two locations, the risk of poor connection can be reduced, and the yield can be improved as a semiconductor device.

However, in the above method, not only is it necessary to bother to provide the branch line 2A, but the adjacent wiring 2B that is wired adjacent to the lower wiring 2 is originally a straight line without the branch line 2A. However, it becomes necessary to make the crank portion 3 as shown in FIG. That is, the method of arranging a plurality of vias is not always a good solution because it requires extra labor in the layout design process and the wiring efficiency is lowered.

Patent Document 1 discloses a semiconductor device capable of increasing the exposure margin in lithography at the time of forming a connection hole without causing a decrease in productivity, thereby improving the yield and further miniaturization. .. In the invention of Patent Document 1, the lower layer wiring provided on the substrate, the second interlayer insulating film covering the lower layer wiring, and the inside of the connection hole provided in the second interlayer insulating film in a state of reaching the lower layer wiring are made of a conductive material. It is a semiconductor device provided with an embedded via and an upper layer wiring in which a pattern is formed on a second interlayer insulating film in a state of being connected to the via.

Further, Patent Document 2 discloses a semiconductor device that suppresses a leakage current generated between a contact plug and an adjacent bit wire. This semiconductor device includes a semiconductor substrate, a first contact plug whose upper end has a larger diameter than the lower end, a first insulating film covering the first contact plug, and a lower end of the first contact plug. A second contact plug joined to the portion and having a diameter dimension of the upper end portion smaller than the diameter dimension of the lower end portion and a second insulating film covering the second contact plug are provided. Further, a wiring layer to which the upper end of the second contact plug is joined is provided at the lower end, two third insulating films covering the wiring layer, and the lower end of the second contact plug among the upper ends of the first contact plug. There is a step formed in the part that is not covered by the part.

Further, Patent Document 3 discloses a wiring member capable of suppressing disconnection of the upper conductive layer in the contact hole and suppressing poor connection between the upper conductive layer and the lower conductive layer. According to the present invention, a first resin layer containing a resin, a lower conductive layer formed in a pattern on the first resin layer and containing an inorganic conductive material, and a lower conductive layer formed on the first resin layer are formed. It has a contact hole on the layer and has a second resin layer containing a photosensitive resin. Further, this wiring member is formed on the second resin layer, is connected to the lower conductive layer in the contact hole, has an upper conductive layer containing a conductive material, and has a lower end surface of the contact hole. The end portion of the lower conductive layer is arranged inside, and the outer periphery of the lower end surface of the contact hole has a contact portion in which the first resin layer and the second resin layer are in contact with each other. ..

Patent Document 4 describes a first layer containing a plurality of conductive wirings, a second layer containing a plurality of conductive wirings, a non-conductive material between the first layer and the second layer, and a first layer. At the intersection of the first wiring of the first layer and the first wiring of the second layer, the first conductive via that penetrates the non-conductive material and connects the first layer and the second layer, and the second layer of the second layer. Disclosed is a semiconductor device comprising two wires and a second conductive via connected between the wires of any other layer of the semiconductor device and a conductive member electrically isolated from the wires. The invention of Patent Document 4 provides a technique for improving the reliability of vias that do not include redundant vias.

Japanese Unexamined Patent Publication No. 2006-24831 Japanese Unexamined Patent Publication No. 2015-60918 Japanese Unexamined Patent Publication No. 2015-228426 Japanese Unexamined Patent Publication No. 2012-182455

The present embodiment provides vias that do not require extra effort in the layout design process and do not reduce wiring efficiency.

The via according to the present embodiment is the upper wiring and the lower portion in a cross region between the upper wiring located at the upper portion and the lower wiring which is a wiring crossing the upper wiring and is located below the upper wiring. In the via connecting the wiring, the portion in contact with the upper wiring and the lower wiring has a joint surface of a region extending in both directions extending from the cross region to the length of the wiring, and the cross of the wiring facing from the joint surface. A first block portion extending toward the region is provided on the joint surface of the upper wiring, and a second block portion extending from the joint surface toward the cross region of the opposite wiring is the lower wiring. It is provided on the joint surface, and is characterized in that it is formed in a shape as if it were fused at a portion where the first block portion and the second block portion overlap.

The perspective view which shows the structure of the via which concerns on the prior art example. The perspective view which shows the structure of the via which concerns on the prior art example. FIG. 3 is a cross-sectional view of a main part of a semiconductor device having vias according to the first embodiment of the present invention. The perspective view explaining the cross region where the via which concerns on 1st Embodiment of this invention is provided. The perspective view of the state where the via is provided in the cross region where the via which concerns on 1st Embodiment of this invention is provided. The perspective view which showed the via which concerns on 1st Embodiment of this invention virtually as two blocks. Sectional drawing of the via which concerns on 1st Embodiment of this invention. The perspective view of the state where the via is provided in the cross region where the via which concerns on 2nd Embodiment of this invention is provided. The front view which showed one of the vias which concerns on 2nd Embodiment of this invention as two virtual blocks. A front view of a via according to a second embodiment of the present invention as viewed from two directions. FIG. 3 is a cross-sectional view of a via according to a second embodiment of the present invention. The perspective view which showed the via which concerns on 3rd Embodiment of this invention virtually as two blocks. FIG. 3 is a cross-sectional view of a via according to a third embodiment of the present invention.

Hereinafter, embodiments of the via and the semiconductor device according to the present invention will be described with reference to the accompanying drawings. In each figure, the same components are designated by the same reference numerals, and duplicate description will be omitted. FIG. 3 shows a cross-sectional view of a main part of the semiconductor device having the via 10 according to the first embodiment. An upper wiring 11 is provided above the via 10, and a lower wiring 12 is provided below the via 10.

An insulating layer 13 is provided between the upper wiring 11 and the lower wiring 12 where the via 10 is not provided. A semiconductor element may be arranged at a required position not shown in the drawing in the portion where the insulating layer 13 is arranged. This semiconductor element may be connected to at least one of the upper wiring 11 and the lower wiring 12.

Further, the upper side of the upper wiring 11 is an insulating layer 14. Further, the lower side of the lower wiring 12 is an insulating layer 15. A semiconductor element may be arranged at a required position not shown in the drawing in the portion where the insulating layers 14 and 15 are arranged. This semiconductor element may be connected to the upper wiring 11 or the lower wiring 12.

The upper side of the insulating layer 14 may have the same configuration as the configuration of the upper wiring 11, the lower wiring 12 vias 10 and the insulating layer 13 provided with the wiring layer, vias and insulating layers. Further, the lower side of the insulating layer 15 may have the same configuration as the configuration of the upper wiring 11, the lower wiring 12 vias 10 and the insulating layer 13 provided with the wiring layer, vias and insulating layers.

Hereinafter, the parts of the upper wiring 11, the lower wiring 12, and the via 10 will be described in detail. The upper wiring 11 and the lower wiring 12 are wirings that cross each other as shown in FIG. 4, and have a cross region R. The via 10 connects the upper wiring 11 and the lower wiring 12 in the cross region R as shown in FIG. The cross region R is a prismatic portion, and has a joint surface in which the via 10 is in contact with the upper wiring 11 and the lower wiring 12 on the upper surface or the bottom surface thereof. The via 10 is an integral conductor.

The portion in contact with the upper wiring 11 and the lower wiring 12 has a joint surface of a region extending from the cross region R in both directions in the longitudinal direction of the wiring. That is, the size of the portion where the via 10 contacts the upper wiring 11 and the portion where the via 10 contacts the lower wiring 12 is larger than the width of the cross region R.

Although the via 10 is integrated, it can be considered that the rectangular parallelepiped block A as shown in FIG. 6 and the rectangular parallelepiped block B having the same shape and the same size are fused. In this case, the first block A extending from the joint surface toward the cross region R of the opposite wiring is provided downward from the joint surface of the upper wiring 11.

Further, a second block B extending from the joint surface toward the cross region of the opposite wiring is provided on the upper side of the lower wiring 12 from the joint surface. The via 10 is formed by fusing at the portion where the first block A and the second block B overlap (FIG. 5).

When the cross section of the via 10 configured as described above is cut horizontally at a height close to the joint surface with the upper wiring 11, the via 10 has the same rectangular shape as the joint surface as shown in FIG. 7 (A). Looking at the cross section cut horizontally at the portion where the first block A and the second block B overlap, as shown in FIG. 7B, the shape is such that the same two rectangles as the upper and lower joint surfaces are overlapped. Further, looking at the cross section cut horizontally at a height close to the joint surface with the lower wiring 12, the cross section has the same rectangular shape as the joint surface as shown in FIG. 7 (C). Therefore, since the joint area is larger than the area of the cross region, the resistance of the via 10 can be reduced, and the size of the via 10 does not spread laterally enough to bypass the wiring, so that the wiring efficiency also decreases. Never.

The via 10 is created by creating a mask having holes having a shape created by cutting in the horizontal direction as shown in FIG. 7 at predetermined heights, and embedding a conductive material in the holes and solidifying the vias 10. It can be done by a method of increasing the height of the via in the height direction.

FIG. 8 shows a configuration diagram of the via 20 according to the second embodiment. In the present embodiment, the first block 21A and the second block 21B have the same shape and the same size, but are different from those of the first embodiment. The first block 21A or the second block 21B is shown in FIG. 9 (A). When these are expressed separately by the line segment L that does not originally appear as two blocks, it is as shown in FIG. 9 (A). It is composed of a rectangular parallelepiped block 22 having a predetermined thickness from the joint surface, and a quadrangular pyramid block 23 connected to the rectangular parallelepiped block 22 by a lower bottom surface (a bottom surface formed by a trapezoidal lower bottom surface). Other configurations are the same as in the first embodiment.

A cross-sectional view with the side where the first block 21A looks large is shown in FIG. 10 (A), and a cross-sectional view with the side where the second block 21B looks large is shown in FIG. 10 (B). FIG. 11 shows a cross-sectional view of each part cut by a horizontal plane parallel to the joint surface. FIG. 11 (A) is a cross-sectional view of a portion of the rectangular parallelepiped block 22 near the upper wiring 11, and FIG. 11 (B) is a cross-sectional view of the portion of the quadrangular pyramid block 23, which is shown in FIG. 11 (C). Is a cross-sectional view at the center of the via 20 in the height direction, FIG. 11 (D) is a cross-sectional view of a portion of the second block 21B that has entered the quadrangular pyramid block 23, and FIG. 11 (E) is a cross-sectional view. , Is a cross-sectional view of a portion of a rectangular parallelepiped block 22 close to the lower wiring 12.

As is clear from FIG. 11, the horizontal cross section of the via 20 according to the present embodiment is the sum of the cross section of the first block 21A and the cross section of the second block 21B. It can be seen that as the area of either of these two cross sections decreases, the area of the other increases. Therefore, the cross-sectional area is constant at any height level cross-section, and this cross-sectional area is larger than the cross-sectional area of the via 3 shown in FIG. Since the surface can be widened, the contact is good and the yield is improved. As a result, it is expected that the method of reducing resistance by providing a plurality of vias as in the past can be replaced with one via by using the configuration of the present embodiment, and the wiring efficiency is also improved. You can expect it.

The quadrangular pyramid block 23 may be a quadrangular pyramid block having a sharp tip because the two blocks enter and fuse with each other at a narrowed portion. Further, the via 20 may have no rectangular parallelepiped block 22, and the first block and the second block are a quadrangular pyramid block or a quadrangular pyramid block, and are joined to the upper wiring and the lower wiring. It may be a quadrangular pyramid block or a quadrangular pyramid block connected to the joint surface by a lower bottom surface.

FIG. 12 shows a block diagram of the via 30 according to the third embodiment. In the present embodiment, the first block 31A and the second block 31B have the same shape and the same size. The first block 31A and the second block 31B are coupled to the elliptical column block 32 having a predetermined thickness from the joint surface with the upper wiring 11 or the joint surface with the lower wiring 12 and the elliptical pillar block 32. It is composed of an elliptical frustum block 33. Other configurations are the same as those of the first embodiment, and the first block 31A and the second block 31B are fused and formed at the overlapping portion.

FIG. 13 shows a cross-sectional view of each part cut by a horizontal plane parallel to the joint surface. 13 (A) is a cross-sectional view of a portion of the elliptical column block 32 near the upper wiring 11, and FIG. 13 (B) is a cross-sectional view of the portion of the elliptical column block 33 near the upper wiring 11, and FIG. 13 (C) is a cross-sectional view of the portion of the elliptical column block 33. ) Is a cross-sectional view at the center of the via 30 in the height direction, and FIG. 13 (D) is a cross-sectional view of a portion of the second block 31B that has entered the elliptical cone base block 33. Is a cross-sectional view of a portion of the elliptical column block 32 near the lower wiring 12.

Also in this embodiment, it can be expected that the resistance is lower than that of the conventional via, and the joint surface can be widened, so that the contact is good and the yield is improved. Further, it is expected that the configuration of the present embodiment can be used to replace the via with one via, and the wiring efficiency can be expected to be improved.

10, 20, 30 Via 11 Upper wiring 12 Lower wiring 13, 15 Insulation layer A, 21A, 31A First block B, 21B, 31B Second block 22 Rectangular parallelepiped block 23 Square pyramid block 32 Elliptical column block 33 Elliptical cone Platform block

Claims (7)

In the cross region between the upper wiring located at the upper part and the lower wiring which is a wiring crossing the upper wiring and is located below the upper wiring, in the via connecting the upper wiring and the lower wiring.
The portion in contact with the upper wiring and the lower wiring has a joint surface of a region extending in both directions in the longitudinal direction of the wiring from the cross region.
A first block portion extending from the joint surface toward the cross region of the opposite wiring is provided on the joint surface of the upper wiring.
A second block portion extending from the joint surface toward the cross region of the facing wiring is provided on the joint surface of the lower wiring.
A via characterized in that the first block portion and the second block portion are formed in a shape as if they were fused at the overlapping portion. The via according to claim 1, wherein the first block portion and the second block portion have the same shape. The first block portion and the second block portion are composed of a rectangular parallelepiped block portion having a predetermined thickness from the joint surface and a quadrangular pyramid block portion connected to the rectangular parallelepiped block portion by a lower bottom surface. The via according to claim 1 or 2, characterized in that. The via according to claim 1 or 2, wherein the first block portion and the second block portion are composed of a quadrangular pyramid base block portion that is connected to the joint surface by a lower bottom surface. The first block portion and the second block portion are composed of an elliptical column block portion having a predetermined thickness from the joint surface and an elliptical frustum portion connected to the elliptical column block portion by a lower bottom surface. The via according to claim 1 or 2, characterized in that. The via according to claim 1 or 2, wherein the first block portion and the second block portion are composed of an elliptical frustum portion that is connected to the joint surface by a lower bottom surface. A semiconductor device having the via according to any one of claims 1 to 6.

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