KR20080089017A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20080089017A
KR20080089017A KR1020070031974A KR20070031974A KR20080089017A KR 20080089017 A KR20080089017 A KR 20080089017A KR 1020070031974 A KR1020070031974 A KR 1020070031974A KR 20070031974 A KR20070031974 A KR 20070031974A KR 20080089017 A KR20080089017 A KR 20080089017A
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South Korea
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film
semiconductor device
insulating film
contact hole
forming
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KR1020070031974A
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Korean (ko)
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이성권
강상길
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주식회사 하이닉스반도체
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Priority to KR1020070031974A priority Critical patent/KR20080089017A/en
Publication of KR20080089017A publication Critical patent/KR20080089017A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating a semiconductor device is provided to improve the electrical characteristic of a semiconductor device and increase a driving speed by forming a contact plug with improved electrical reliability. A target layer to be exposed in a subsequent process is formed on a substrate(51). A first insulation layer(53) is formed on the target layer. The first insulation layer is partially etched to form a groove. A second insulation layer(57A) is formed on the first insulation layer along the inner sidewall of an opening of the groove. The first insulation layer on the bottom portion of the groove is etched to form a contact hole to which the target layer is exposed. A contact plug can be filled in the contact hole. The insulation layer can be composed of a plurality of layers.

Description

반도체 소자 제조 방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

도 1은 종래기술에 따라 형성된 깊은 콘택홀을 나타낸 단면도.1 is a cross-sectional view showing a deep contact hole formed according to the prior art.

도 2는 도 1에서 발생된 깊은 콘택홀의 오픈(open) 불량을 나타낸 전자현미경사진.Figure 2 is an electron micrograph showing the open (open) failure of the deep contact hole generated in FIG.

도 3a 내지 도 3d는 본 발명의 일실시예에 따른 깊은 콘택홀 형성 방법을 나타낸 순서도.3A to 3D are flowcharts illustrating a method for forming a deep contact hole according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

51 : 기판 52 : 도전체51 substrate 52 conductors

53 : 제1 절연막 54 : 포토레지스트 패턴53: first insulating film 54: photoresist pattern

57A : 제2 절연막 58 : 깊은 콘택홀57A: second insulating film 58: deep contact hole

본 발명은 반도체 제조 기술에 관한 것으로 특히, 반도체 소자 제조 공정 중, 깊은 콘택홀의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a deep contact hole during a semiconductor device manufacturing process.

일반적으로 반도체 소자는 그 내부에 다수의 소자들을 포함하여 이루어진다. 반도체 소자가 고집적화되면서 일정한 셀(cell) 면적상에 고밀도로 소자들을 형성하여야 하며, 이로 인하여 반도체 소자, 예를 들면 트랜지스터(transistor) 및 캐패시터(capacitor)들의 크기는 점차 줄어들고 있다. 특히 DRAM(Dynamic Random Access Memory)과 같은 반도체 메모리 소자는 디자인 룰(design rule)이 감소하면서 셀의 내부에 형성되는 소자들의 크기가 점차 작아지고 있다. 실제로 최근 DRAM 소자의 최소 선폭은 0.115㎛ 이하로 형성된다. 따라서 셀을 이루는 반도체 소자들의 제조 공정에 많은 어려움들이 발생하고 있다.In general, a semiconductor device includes a plurality of devices therein. As semiconductor devices become highly integrated, devices must be formed at a high density on a certain cell area, thereby decreasing the size of semiconductor devices, for example, transistors and capacitors. In particular, semiconductor memory devices, such as DRAM (Dynamic Random Access Memory), as the design rule is reduced (size) of the elements formed inside the cell is gradually decreasing. In fact, the minimum line width of the recent DRAM device is formed to 0.115㎛ or less. Therefore, many difficulties have arisen in the manufacturing process of the semiconductor devices forming the cell.

대표적인 어려움으로써, 반도체 소자의 금속 콘택(metal contact)용 깊은 콘택홀(deep contact hole)을 형성하기 위한 식각공정을 예로 들수 있다. 이는 반도체 소자의 수직적 높이가 증가되어 콘택홀이 형성될 예정영역의 종횡비가 높기 때문이다.As a representative difficulty, an etching process for forming a deep contact hole for a metal contact of a semiconductor device is exemplified. This is because the vertical height of the semiconductor device is increased to increase the aspect ratio of the region where the contact hole is to be formed.

이를 뒷받침하는 도면인 도 1은 종래기술에 따라 형성된 깊은 콘택홀을 나타낸 단면도이다.1 is a cross-sectional view illustrating a deep contact hole formed according to the prior art.

도 1을 참조하면, 접합영역 또는 하부 금속배선 등의 도전층(12)을 갖는 기판(11) 상에 제1 절연막(13)과 식각정지막(14)과 제2 절연막(15) 및 포토레지스트 패턴(16)이 순차적으로 형성되고, 포토레지스트 패턴(16)을 식각마스크로 하부층(15~13)을 식각하여 깊은 콘택홀(17)이 형성된다.Referring to FIG. 1, a first insulating film 13, an etch stop film 14, a second insulating film 15, and a photoresist on a substrate 11 having a conductive layer 12 such as a junction region or a lower metal wiring. The pattern 16 is sequentially formed, and the deep contact holes 17 are formed by etching the lower layers 15 to 13 using the photoresist pattern 16 as an etch mask.

여기서, 반도체 소자의 고집적화로 인하여 소자의 형성 면적은 작아지고, 소 자의 높이가 증가하기 때문에 소자와 소자간을 격리시키는 절연막(13~15)의 두께가 증가하고 있다. 따라서, 두꺼워진 절연막(13~15) 내에 도전층(12)을 노출시키는 깊은 콘택홀(17)은 바닥부의 선폭(CD2)이 개구부의 선폭(CD1) 보다 좁아(CD1>CD2)지는 문제가 발생한다.Here, due to the high integration of the semiconductor device, the device formation area is reduced, and the height of the element is increased, thereby increasing the thickness of the insulating films 13 to 15 that isolate the device from the device. Therefore, the deep contact hole 17 exposing the conductive layer 12 in the thickened insulating layers 13 to 15 has a problem in that the line width CD2 of the bottom portion is narrower than the line width CD1 of the opening portion (CD1> CD2). do.

깊은 콘택홀(17) 바닥부의 선폭이 좁아지면 이 깊은 콘택홀(17)의 내부에 매립된 콘택 플러그와 접촉면적이 작아서 도전체(12)와의 콘택 저항이 증가하게 되고, 때문에 소자의 구동 속도를 감소시키고, 더 나아가서는 도전층(12)이 노출되지 않는 콘택홀 개방불량이 발생한다.When the line width of the bottom portion of the deep contact hole 17 is narrowed, the contact area with the contact plug embedded in the deep contact hole 17 is small, which increases the contact resistance with the conductor 12, thereby increasing the driving speed of the device. Decrease, and furthermore, contact hole opening defects occur in which the conductive layer 12 is not exposed.

도 2는 도 1에서 발생된 깊은 콘택홀의 오픈(open) 불량을 나타낸 전자현미경사진이다. 여기서, 설명의 편의를 위해 도 1의 도면부호를 인용한다.FIG. 2 is an electron micrograph showing an open defect of the deep contact hole generated in FIG. 1. Here, reference numerals of FIG. 1 are referred to for convenience of description.

도 2를 참조하면, 깊은 콘택홀(17)에서 개구부의 폭(CD1)이 바닥부의 폭(CD2) 보다 큰 것을 알 수 있다.Referring to FIG. 2, it can be seen that the width CD1 of the opening in the deep contact hole 17 is larger than the width CD2 of the bottom portion.

한편, 이를 해결하기 위한 방법으로 전체적으로 깊은 콘택홀의 선폭을 증가시키는 방법이 있으나, 이는 소자의 디자인 룰(rule)에 있어서, 소자의 형성 면적이 커지기 때문에 소자의 고집적화에 어려움이 있다.On the other hand, there is a method for increasing the line width of the deep contact hole as a whole, but in the design rule of the device, since the formation area of the device is large, there is a difficulty in high integration of the device.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 개방불량 해소 또는 콘택홀의 개구부의 폭을 감소시키는 반도체 소자의 제조 방법을 제공하는 것을 제1 목적으로 한다.The present invention has been proposed to solve the above-mentioned problems of the prior art, and a first object of the present invention is to provide a method of manufacturing a semiconductor device for reducing the opening defect or reducing the width of the opening of the contact hole.

또한, 전기적 신뢰성이 우수한 콘택 플러그를 갖는 반도체 소자의 제조 방법을 제공하는 것을 제2 목적으로 한다.Moreover, it is a 2nd objective to provide the manufacturing method of the semiconductor element which has the contact plug excellent in electrical reliability.

상기의 목적을 달성하기 위한 본 발명의 일측면에 따르면, 기판 상에 후속 공정을 통해 노출될 대상막을 형성하는 단계, 상기 대상막 상에 제1 절연막을 형성하는 단계, 상기 제1 절연막을 일부 식각하여 홈을 형성하는 단계, 상기 홈의 개구부 내측벽을 따라 상기 제1 절연막 상에 제2 절연막을 형성하는 단계, 상기 홈 바닥부의 상기 제1 절연막을 식각하여 상기 대상막이 노출되는 콘택홀을 형성하는 단계를 포함하는 반도체 소자 제조 방법을 제공한다.According to an aspect of the present invention for achieving the above object, forming a target film to be exposed through a subsequent process on a substrate, forming a first insulating film on the target film, partially etching the first insulating film Forming a groove, forming a second insulating film on the first insulating film along the inner wall of the opening, and etching the first insulating film at the bottom of the groove to form a contact hole through which the target film is exposed. It provides a method for manufacturing a semiconductor device comprising the step.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 3a 내지 도 3d는 본 발명의 일실시예에 따른 깊은 콘택홀 형성 방법을 나타낸 순서도이다.3A to 3D are flowcharts illustrating a method for forming a deep contact hole according to an embodiment of the present invention.

우선, 도 3a에 도시된 바와 같이, 도전층(52)인 대상막이 형성된 기판(51) 상에 제1 절연막(53)을 형성한다.First, as shown in FIG. 3A, the first insulating film 53 is formed on the substrate 51 on which the target film, which is the conductive layer 52, is formed.

일반적으로, 제1 절연막(53)은 단층 또는 복수개의 층으로 이루어지는데, 예를 들면, BPSG(Boron Phosphorus Silicate Glass)막, PSG(Phospho Silicate Glass) 막, BSG(Boro Silicate Glass)막, TEOS(Tetra Ethyl Ortho Silicate)막 및 HDP(High Density Plasma) 산화막 중 어느하나 또는 이들의 적층막으로 형성한다. 여기서, BPSG막은 산화막에 붕소(B) 또는 인(P)과 같은 불순물을 첨가시켜 낮은 온도에서 평탄화되도록 사용되는 절연막으로써, 평탄화의 수단으로 사용되고, 열에 대한 플로우(flow) 특성 - 850℃에서 점성(viscosity)이 급격하게 변화 - 이 좋은 막질이다. 그리고, PSG막은 산화막에 인(P)이 첨가된 절연막으로써, 절연특성이 우수하고, 열에 대한 플로우 특성이 우수하다.In general, the first insulating layer 53 is formed of a single layer or a plurality of layers. For example, a Boron Phosphorus Silicate Glass (BPSG) film, a Phospho Silicate Glass (PSG) film, a Boro Silicate Glass (BSG) film, and a TEOS ( It is formed of any one of a Tetra Ethyl Ortho Silicate (HDD) film and a High Density Plasma (HDP) oxide film or a laminated film thereof. Here, the BPSG film is an insulating film which is used to planarize at a low temperature by adding impurities such as boron (B) or phosphorus (P) to the oxide film. The viscosity changes abruptly-this is a good film quality. The PSG film is an insulating film in which phosphorus (P) is added to the oxide film, and has excellent insulation characteristics and excellent flow characteristics with respect to heat.

또한, 적어도 두 개층 이상으로 제1 절연막(53)을 형성할 시에는 효율적인 식각정지를 위해 예시한 각 박막 사이에 식각선택비가 다른 예컨대, 질화막을 개재시킬 수 있다. 이 박막을 식각정지막이라고 명명한다.In addition, when the first insulating film 53 is formed of at least two layers, for example, a nitride film having a different etching selectivity may be interposed between the illustrated thin films for efficient etching stop. This thin film is called an etch stop film.

그리고, 도전층(52)은 소스/드레인(source/drain) 영역, 픽업(pick up) 영역 및 웰(well) 영역과 같은 접합 영역일 수 있으며, 또는 워드라인(word line), 비트라인(bit line) 및 하부 금속배선일 수 있다.The conductive layer 52 may be a junction region such as a source / drain region, a pick up region, and a well region, or may be a word line or a bit line. line) and bottom metallization.

이어서, 제1 절연막(53) 상에 포토레지스트 패턴(54)을 형성한다.Next, the photoresist pattern 54 is formed on the first insulating film 53.

이 포토레지스트 패턴(54)은 깊은 콘택홀을 형성하기 위한 식각마스크로써, 포토레지스트 패턴(54)과 제1 절연막(53) 사이에 하드마스크층을 더 개재할 수 있다.The photoresist pattern 54 is an etching mask for forming a deep contact hole, and may further include a hard mask layer between the photoresist pattern 54 and the first insulating layer 53.

하드마스크층은 비정질 탄소막이 대표적인데, 비정질 탄소막을 사용할 경우 비정질 탄소막과 포토레지스트 패턴(53) 사이에 질화막을 더 개재하는 것이 효율적이다. 이는 비정질 탄소막과 포토레지스트 패턴(54)이 유사한 물성을 갖기 때문이 고, 비정질 탄소막과 질화막은 식각선택비가 높기 때문에 비교적 얇은 두께의 질화막으로도 두꺼운 비정질 탄소막을 용이하게 식각할 수 있기 때문이다.The hard mask layer is typically an amorphous carbon film. When an amorphous carbon film is used, it is more efficient to interpose a nitride film between the amorphous carbon film and the photoresist pattern 53. This is because the amorphous carbon film and the photoresist pattern 54 have similar physical properties, and since the amorphous carbon film and the nitride film have high etching selectivity, the thick amorphous carbon film can be easily etched even with a relatively thin nitride film.

다음으로, 도 3b 도시된 바와 같이, 포토레지스트 패턴(54)을 식각마스크로 제1 절연막(53)을 1차 식각한다. Next, as illustrated in FIG. 3B, the first insulating layer 53 is first etched using the photoresist pattern 54 as an etching mask.

제1 절연막(53)의 1차 식각은 제1 절연막(53)을 완전히 관통시켜 홀(hole)을 형성하는 것이 아니라, 홈(56)을 형성시키는 식각공정이다. 그리고, 홈(56)의 형성공정은 제1 절연막(53) 내에서 식각정지막으로 작용하는 즉, BPSG막, PSG막, TEOS막 및 HDP 산화막과 식각선택비가 다른 박막에서 멈추는 것이 바람직하다.The primary etching of the first insulating layer 53 is an etching process of forming the grooves 56, not forming a hole by completely penetrating the first insulating layer 53. In the forming process of the grooves 56, the etching stop film acts as the etch stop film in the first insulating film 53, that is, the BPSG film, the PSG film, the TEOS film, and the HDP oxide film are preferably stopped at a thin film having a different etching selectivity.

그리고, 1차 식각 공정에서 포토레지스트 패턴(54)의 오픈폭은 홈(56) 바닥부의 선폭을 고려하여 충분히 넓은 폭을 갖고 있어야 한다. 즉, 홈(56) 형성 공정시 발생하는 개구부와 바닥부의의 선폭 차이를 고려하여 바닥부의 선폭이 정상적인 선폭을 갖도록 개구부의 선폭을 조절하는 것으로 도면을 참조하면, 종래의 개구부의 선폭(CD4)보다 본 발명의 제1 실시예에서의 선폭(CD3)이 넓은 것을 볼 수 있다. In the first etching process, the open width of the photoresist pattern 54 should have a sufficiently wide width in consideration of the line width of the bottom of the groove 56. That is, the line width of the opening is adjusted so that the line width of the bottom portion has a normal line width in consideration of the line width difference between the opening portion and the bottom portion generated during the groove 56 forming process. It can be seen that the line width CD3 in the first embodiment of the present invention is wide.

다음으로, 도 3c에 도시된 바와 같이, 홈(56)이 형성된 결과물 상에 제2 절연막(57)을 형성한다. Next, as shown in FIG. 3C, a second insulating film 57 is formed on the resultant product in which the grooves 56 are formed.

제2 절연막(57)은 PECVD(Plasma Enhanced Chemical Vapor Depostion) 방식의 질화막, 산화막 및 실리콘산화질화막 중 어느하나 또는 이들의 적층막으로써, 피복성이 불량한 절연막이다. 때문에 제2 절연막(57)은 홈(56)의 개구부 내측벽과 포토레지스트 패턴(54)의 상부에 형성되고, 홈(56)의 바닥부에는 형성되지 않는다. 만약, 홈(56)의 바닥부에 제2 절연막(57)이 형성되더라도 미세한 두께를 갖기 때문에 후속 공정에서 제거 가능하다.The second insulating film 57 is one of a nitride film, an oxide film and a silicon oxynitride film of a Plasma Enhanced Chemical Vapor Depostion (PECVD) method or a laminated film thereof, and is an insulating film having poor coating properties. Therefore, the second insulating layer 57 is formed on the inner wall of the opening 56 of the groove 56 and the upper portion of the photoresist pattern 54, but not on the bottom of the groove 56. If the second insulating film 57 is formed at the bottom of the groove 56, the second insulating film 57 may be removed in a subsequent process because of its fine thickness.

다음으로, 도 3d에 도시된 바와 같이, 홈(56) 바닥부의 제1 절연막(53)을 식각하여 도전층(52)이 노출되는 깊은 콘택홀(58)을 형성한다. 이때, 제2 절연막(57)도 일부 식각되어 콘택홀(58)의 입구 선폭을 확보한다.Next, as illustrated in FIG. 3D, the first insulating layer 53 of the bottom portion of the groove 56 is etched to form a deep contact hole 58 through which the conductive layer 52 is exposed. At this time, the second insulating layer 57 is also partially etched to secure the inlet line width of the contact hole 58.

본 발명의 일실시예를 정리해 보면, 깊은 콘택홀(58)은 바닥부의 선폭을 확보하면서 개구부의 선폭을 바닥부의 선폭보다 좁거나, 동일하게 형성할 수 있다. 이는 제2 절연막(57)의 형성두께 및 식각후 잔류두께를 조절하면 된다.In one embodiment of the present invention, the deep contact hole 58 may be formed to have the line width of the opening narrower than or equal to the line width of the bottom portion while securing the line width of the bottom portion. This may be done by adjusting the formation thickness of the second insulating layer 57 and the remaining thickness after etching.

만약, 깊은 콘택홀(58)의 개구부의 선폭을 좁힐 경우에는 콘택플러그의 상부가 스토리지 노드(storage node)에 완전히 감쌀 수 있어서, 콘택저항값을 감소시킬 수 있다.If the line width of the opening of the deep contact hole 58 is narrowed, the upper portion of the contact plug may be completely wrapped around the storage node, thereby reducing the contact resistance value.

또한, 깊은 콘택홀(58) 바닥부의 선폭을 증가시켜 도전체(52)와의 접촉면적을 증가시켜 콘택저항값을 감소시킨다.In addition, the line width of the bottom portion of the deep contact hole 58 is increased to increase the contact area with the conductor 52, thereby reducing the contact resistance value.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

이상에서 살펴본 바와 같이, 본 발명은 깊은 콘택홀의 바닥부가 개구부보다 좁아지는 문제점을 해결한다.As described above, the present invention solves the problem that the bottom of the deep contact hole is narrower than the opening.

이에 따라, 전기적 신뢰성이 우수한 콘택 플러그를 형성할 수 있으며, 결과적으로 반도체 소자의 전기적 특성 개선, 구동 속도 증가 및 수율 증대 효과를 획득할 수 있다.Accordingly, a contact plug having excellent electrical reliability can be formed, and as a result, an improvement in electrical characteristics of the semiconductor device, an increase in driving speed, and an increase in yield can be obtained.

Claims (6)

기판 상에 후속 공정을 통해 노출될 대상막을 형성하는 단계;Forming a target film to be exposed through a subsequent process on the substrate; 상기 대상막 상에 제1 절연막을 형성하는 단계;Forming a first insulating film on the target film; 상기 제1 절연막을 일부 식각하여 홈을 형성하는 단계:Partially etching the first insulating layer to form a groove; 상기 홈의 개구부 내측벽을 따라 상기 제1 절연막 상에 제2 절연막을 형성하는 단계;Forming a second insulating film on the first insulating film along an inner wall of the opening of the groove; 상기 홈 바닥부의 상기 제1 절연막을 식각하여 상기 대상막이 노출되는 콘택홀을 형성하는 단계Etching the first insulating layer of the groove bottom to form a contact hole exposing the target layer; 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 콘택홀에 매립되는 콘택플러그를 형성하는 단계를 더 포함하는 반도체 소자 제조 방법.And forming a contact plug buried in the contact hole. 제1항에 있어서,The method of claim 1, 상기 제2 절연막은 PECVD(Plasma Enhanced Chemical Vapor Depostion) 방식의 질화막, 산화막 및 실리콘산화질화막 중 어느하나 또는 이들의 적층막으로 형성 하는 것을 특징으로 하는 반도체 소자 제조 방법.The second insulating film is a semiconductor device manufacturing method characterized in that formed of any one or a laminated film of a nitride film, oxide film and silicon oxynitride film of the PECVD (Plasma Enhanced Chemical Vapor Depostion) method. 제1항에 있어서,The method of claim 1, 상기 제1 절연막은 복수개의 층으로 형성하는 반도체 소자 제조 방법.And the first insulating film is formed of a plurality of layers. 제4항에 있어서,The method of claim 4, wherein 상기 홈을 형성하는 식각공정은 상기 제1 절연막 내에서 식각선택비가 다른 절연막에 의해 식각이 멈추는 반도체 소자 제조 방법.The etching process of forming the groove is a semiconductor device manufacturing method in which the etching is stopped by the insulating film having a different etching selectivity in the first insulating film. 제1항에 있어서,The method of claim 1, 상기 대상막은 도전층으로 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.The target film is a semiconductor device manufacturing method, characterized in that formed as a conductive layer.
KR1020070031974A 2007-03-30 2007-03-30 Method for fabricating semiconductor device KR20080089017A (en)

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