KR20080086253A - Thin film transistor array substrate and manufacturing method thereof - Google Patents

Abstract

A thin film transistor array substrate and a manufacturing method thereof are provided to conform peripheral edges of source and drain electrodes to a peripheral edge of an ohmic contact layer by exposing the channel portion through dry etch using source/drain conductive pattern group. A thin film transistor array substrate comprises a gate electrode(34), a gate insulation layer(41) an active layer(35), an ohmic contact layer(36), a source electrode(38), and a drain electrode. The gate electrode is formed on a substrate. The gate insulation layer is formed on the substrate to cover the gate electrode. The active layer overlaps with the gate electrode on the gate insulation layer. The ohmic contact layer is deposited on the active layer. The source electrode is formed on the ohmic contact layer and has a peripheral edge substantially conforming to a peripheral edge of the ohmic contact layer. The drain electrode faces the source electrode with a semiconductor channel portion having an exposed active region, and has a peripheral edge conforming to a peripheral edge of the ohmic contact layer. The drain electrode is formed on the ohmic contact layer. The source and drain electrodes includes copper.

Description

Thin Film Transistor Array Substrate and Manufacturing Method Thereof

1 is a perspective view schematically showing a conventional liquid crystal display panel.

FIG. 2 is a cross-sectional view of the thin film transistor unit of the conventional thin film transistor array substrate of FIG. 1.

3A to 3C are cross-sectional views illustrating a process of forming a source / drain conductive pattern group and a semiconductor channel portion.

4 is a plan view showing a thin film transistor array substrate according to the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor array substrate of FIG. 4 taken along the line II ′. FIG.

6A and 6B are a plan view and a sectional view for explaining a first mask process in the method of manufacturing a thin film transistor array substrate according to the present invention.

7A and 7B are a plan view and a sectional view for explaining a second mask process in the method of manufacturing a thin film transistor array substrate according to the present invention.

8A to 8H are cross-sectional views for explaining a second mask process according to the present invention step by step mainly in the thin film transistor region.

9A and 9B are plan and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor array substrate according to the present invention.

10A and 10B are a plan view and a sectional view for explaining a fourth mask process in the method of manufacturing a thin film transistor array substrate according to the present invention.

<Explanation of symbols for the main parts of the drawings>

31 substrate 41 gate insulating film

48: protective film 32: gate line

GP: Gate Pad DP: Data Pad

132: gate pad lower electrode 133: data pad lower electrode

142: gate pad upper electrode 143: data pad upper electrode

35 active layer 36 ohmic contact layer

37 semiconductor pattern 38 source electrode

39: drain electrode 33: data line

34: gate electrode 40: pixel electrode

49, 134, 135: contact hole

46: mask P1: transmission region

P2: diffraction exposure area P3: blocking area

47A, 47B, 47: photoresist pattern 42: amorphous silicon layer

44 source / drain metal layer 182 strip solution

43: Amorphous Silicon Layer Doped With Impurities

P: contaminants

The present invention relates to a thin film transistor array substrate and a method of manufacturing the same. In particular, the present invention prevents the residue of the strip solution from contaminating the semiconductor channel portion, and also the outer edge of the ohmic contact layer and the outer edge of the source / drain conductive pattern group when forming a source / drain conductive pattern group using copper substantially. The present invention relates to a thin film transistor array substrate and a method of manufacturing the same.

Thin film transistors (hereinafter, referred to as "TFTs") are mainly used in active matrix flat panel displays. A flat panel display includes a plurality of pixel arrays defined by the intersection of gate lines and data lines on a substrate. Each pixel receives an electrical signal by a TFT connected to the gate line and the data line. A representative example of a flat panel display including a TFT is a liquid crystal display (LCD).

A liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel (hereinafter, referred to as a liquid crystal panel) for displaying an image through a liquid crystal cell matrix, and a driving circuit for driving the liquid crystal panel.

1 illustrates a liquid crystal panel. 2 is a cross-sectional view of the TFT portion of the TFT array substrate shown in FIG. 1.

Referring to FIG. 1, a conventional liquid crystal panel includes a color filter array substrate 1 and a thin film transistor array substrate 10 bonded together with a liquid crystal 6 interposed therebetween.

The liquid crystal 6 having dielectric anisotropy rotates in accordance with the electric field formed by the data signal of the pixel electrode 20 and the common voltage Vcom of the common electrode 5 to adjust the light transmittance.

The color filter array substrate 1 includes a black matrix 3, a color filter 4, and a common electrode 5 sequentially formed on the upper substrate 2. The black matrix 3 is formed in a matrix form on the upper substrate 2. This black matrix 3 divides the area of the upper substrate 2 into a plurality of cell areas in which the color filter 4 is to be formed, and prevents light interference and reflection of external light between adjacent cells. The color filter 4 is formed to be divided into red (R), green (G), and blue (B) in the cell region divided by the black matrix 3 to transmit red, green, and blue light, respectively. The common electrode 5 is a transparent conductive layer entirely coated on the color filter 4 and supplies a common voltage Vcom which is a reference when driving the liquid crystal 6. In addition, the color filter array substrate 1 may further include an overcoat layer (not shown) between the color filter 6 and the common electrode 8 to planarize the color filter 4.

The TFT array substrate 10 includes a TFT and pixel electrodes 20 formed on the lower substrate 11 for each cell region defined by the intersection of the gate line 12 and the data line 13. The gate line 12 and the data line 13 cross each other insulated by the gate insulating film 21. The TFT supplies the data signal from the data line 13 to the pixel electrode 20 in response to the gate signal from the gate line 12. To this end, the TFT is in ohmic contact with the gate electrode 14 connected to the gate line 12, the semiconductor pattern 17 overlapping the gate electrode 14, and the semiconductor pattern 17 as shown in FIG. 2, and the pixel contact is performed. The drain electrode 18 is connected to the pixel electrode 20 through the hole 29, and the source electrode 19 is in ohmic contact with the semiconductor pattern 17 and connected to the data line 13.

The semiconductor pattern 17 is composed of an active layer 15 and an ohmic contact layer 16 stacked on the active layer 15. The active layer 15 is exposed between the source electrode 18 and the drain electrode 19 to serve as a channel, and the ohmic contact layer 16 allows the electrodes 18 and 19 to make ohmic contact with the active layer 15.

Such conventional TFT array substrates are formed using a number of mask processes. One mask process includes a plurality of processes such as a thin film deposition (coating) process, a cleaning process, a photolithography process (hereinafter, a photo process), an etching process, a photoresist removing process, an inspection process, and the like.

The mask process for forming the semiconductor channel portion 110 of the TFT array substrate among the plurality of mask processes described above leaves the residue P in the semiconductor channel portion 110, and is connected to the ohmic contact layer 16 and the ohmic contact layer 16. A step is formed between the electrodes 18 and 19. This problem is noticeable when the source / drain conductive pattern group including the source electrode 18 and the drain electrode 19 includes copper (hereinafter referred to as “Cu”) for low resistance wiring.

Hereinafter, a process of forming the semiconductor channel unit 110, the source electrode 18, and the drain electrode 19 will be described in detail with reference to FIGS. 3A to 3C.

3A through 3C, the semiconductor channel unit 110, the source electrode 18, and the drain electrode 19 are formed by the same photoresist pattern 27. That is, the semiconductor channel unit 110, the source electrode 18, and the drain electrode 19 are formed using one photoresist pattern 27 as a mask.

In more detail, the metal layer including Cu is wet-etched using the photoresist pattern 27 as a mask to form the source electrode 18 and the drain electrode 19 as shown in FIG. 3A. In the process of wet etching the metal layer including Cu, Cu is rapidly etched at the portion in contact with the edge of the photoresist pattern 27. Accordingly, the width of each of the source electrode 18 and the drain electrode 19 formed through wet etching is smaller than the width of the photoresist pattern 27.

Next, as shown in FIG. 3B, the ohmic contact layer 16 exposed by the formation of the source electrode 18 and the drain electrode 19 using the photoresist pattern 27 as a mask is dry-etched to dry the semiconductor channel part 110. To form. In the dry etching of the ohmic contact layer 16, the outer edge of the ohmic contact layer 16 may coincide with the outer edge of the photoresist pattern 27 along the same line without a step. As a result, the outer edge of the ohmic contact layer 16 has a step with the outer edge of the source / drain conductive pattern group including the source electrode 18 and the drain electrode 19. In general, the outer edge of the ohmic contact layer 16 in the semiconductor channel unit 110 is formed on the same line as the outer edge of the source / drain conductive pattern group, and thus the electrical characteristics of the TFT device are better. Therefore, when Cu is applied, a step between the outer edge of the ohmic contact layer 16 formed in the semiconductor channel part 110 and the outer edge of the source / drain conductive pattern group causes a decrease in the electrical characteristics of the TFT device.

Thereafter, the photoresist pattern 27 is removed as shown in FIG. 3C by using the strip solution 122 sprayed through the nozzle 121. At this time, the residue P of the strip solution 122 remains in the semiconductor channel portion 110.

As such, the semiconductor channel unit 110 is exposed to the strip solution 122 and contaminated by the residue P generated during the strip process. If the semiconductor channel portion 110 is contaminated, the electrical characteristics of the TFT element are degraded.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the same, wherein the residue of the strip solution is prevented from contaminating the semiconductor channel portion.

In addition, another object of the present invention is to form a thin film transistor array substrate in which the outer edge of the ohmic contact layer and the outer edge of the source / drain conductive pattern group coincide along substantially the same line when forming a source / drain conductive pattern group using copper and It is to provide a manufacturing method.

In order to achieve the above object, the TFT array substrate according to the present invention comprises a gate electrode formed on the substrate; A gate insulating film formed on the substrate to cover the gate electrode; An active layer overlapping the gate electrode on the gate insulating layer; An ohmic contact layer laminated on the active layer; A source electrode stacked on the ohmic contact layer and having an outer edge coincident with a line substantially the same as an outer edge of the ohmic contact layer; And a drain electrode facing the source electrode and the semiconductor channel portion where the active layer is exposed, and having an outer edge coincident with a line substantially the same as an outer edge of the ohmic contact layer and stacked on the ohmic contact layer. do. The source electrode and the drain electrode may be made of a metal including copper.

A method of manufacturing a TFT array substrate according to the present invention includes forming a gate conductive pattern group including a gate electrode of a thin film transistor on a substrate; Forming a gate insulating film on the substrate to cover the gate conductive pattern group; Forming a source / drain metal layer including an amorphous silicon layer, an amorphous silicon layer doped with impurities, and copper on the gate insulating layer; Forming a photoresist pattern of partially different height on said source / drain metal layer; Etching the source / drain metal layer, the amorphous silicon layer doped with impurities, and the amorphous silicon layer using the photoresist pattern to form a semiconductor pattern including an active layer and an ohmic contact layer; Ashing the photoresist pattern; Wet etching the source / drain metal layer using the ashed photoresist pattern to form a source / drain conductive pattern group including a source electrode and a drain electrode of the thin film transistor; Stripping the photoresist pattern with the ohmic contact layer remaining between the source electrode and the drain electrode; And forming a semiconductor channel portion to which the active layer is exposed by dry etching using the source / drain conductive pattern group.

In forming the semiconductor channel portion in which the active layer is exposed by dry etching using the source / drain conductive pattern group, outer edges of each of the source and drain electrodes coincide with substantially the same line as the outer edge of the ohmic contact layer. .

The dry etching gas includes SF ₆ gas in the step of forming the semiconductor channel portion to which the active layer is exposed by dry etching using the source / drain conductive pattern group.

The gate conductive pattern group includes a gate line connected to the gate electrode and a gate pad lower electrode connected to the gate line.

The source / drain conductive pattern group includes a data line connected to the source electrode and a data pad lower electrode connected to the data line.

After the forming of the semiconductor pattern, forming a passivation layer including a pixel contact hole exposing the drain electrode on the gate insulating layer; And forming a pixel electrode connected to the drain electrode through the pixel contact hole on the passivation layer.

Other objects and advantages of the present invention other than the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 to 10B.

4 is a plan view showing a TFT array substrate according to the present invention. FIG. 5 is a cross-sectional view of the TFT array substrate illustrated in FIG. 4 taken along the line "I-I '".

4 and 5, a TFT array substrate according to the present invention includes a TFT and a pixel electrode 40 formed on a lower substrate 31 for each cell region defined by an intersection of a gate line 32 and a data line 33. It is provided. The TFT array substrate further includes a gate pad portion GP for supplying a gate signal to the gate line 32 and a data pad portion DP for supplying a data signal to the data line 33.

The gate pad part GP passes through the gate pad lower electrode 132, the gate insulating layer 41, and the passivation layer 48 extending from the gate line 32 to supply a gate signal to the gate line 32. The gate pad contact hole 134 exposing the lower electrode 132 and the gate pad upper electrode 142 connected to the gate pad lower electrode 132 through the gate pad contact hole 134.

The data pad part DP penetrates the data pad lower electrode 133 and the passivation layer 48 extending from the data line 33 to supply a data signal to the data line 33. And a data pad upper electrode 143 connected to the data pad lower electrode 133 through the data pad contact hole 135 to be exposed and the data pad contact hole 135.

The TFT supplies the data signal from the data line 33 to the pixel electrode 40 in response to the gate signal from the gate line 32. To this end, the TFT has a gate electrode 34 connected to the gate line 32, a semiconductor pattern 37 overlapping the gate electrode 34, a drain in ohmic contact with the semiconductor pattern 37, and connected to the pixel electrode 40. An electrode 39 and a source electrode 38 in ohmic contact with the semiconductor pattern 37 and connected to the data line 33.

The semiconductor pattern 37 is composed of an active layer 35 and an ohmic contact layer 36 stacked on the active layer 35. The active layer 35 is exposed in the semiconductor channel portion 30 between the source electrode 38 and the drain electrode 39 to serve as a channel, and the ohmic contact layer 36 includes the electrodes 38 and 39 as the active layer 35. ) To make ohmic contact.

There is no residue of the strip solution in the semiconductor channel portion 30. As such, since the semiconductor channel portion 30 is not contaminated, the electrical characteristics of the TFT element are not deteriorated, and as a result, driving reliability is improved.

The outer edge of each of the source electrode 38 and the drain electrode 39 is patterned substantially without step difference with the outer edge of the ohmic contact layer 36. In other words, the outer edge of each of the source electrode 38 and the drain electrode 39 and the outer edge of the ohmic contact layer 36 coincide along substantially the same line.

6A to 10B, a manufacturing process of a TFT array substrate according to the present invention will be described.

6A and 6B are a plan view and a sectional view for explaining a first mask process of a TFT array substrate according to the present invention.

6A and 6B, a gate conductive pattern group including a gate line 32, a gate electrode 34, and a gate pad lower electrode 132 is formed on the substrate 31 by a first mask process. The gate conductive pattern group is a single layer made of a metal material such as molybdenum (Mo), titanium (Ti), Cu, aluminum neodymium (AlNd), aluminum (Al), chromium (Cr), Mo alloy, Cu alloy, Al alloy, etc. Or bilayers or more.

7A and 7B are a plan view and a sectional view for explaining a second mask process of a TFT array substrate according to the present invention. 8A to 8H are diagrams for explaining a second mask process step by step according to the present invention.

7A and 7B, a gate insulating layer 41 is formed on the substrate 31 on which the gate conductive pattern group is formed. A source / drain conductive pattern group including a data line 33, a source electrode 38, a drain electrode 39, and a data pad lower electrode 133 is formed on the gate insulating layer 41 by a second mask process. The semiconductor pattern 37 is overlapped under the source / drain conductive pattern group. The semiconductor pattern 37 includes an active layer 35 and an ohmic contact layer 36, and the active layer 35 is exposed at the channel portion 30 between the source electrode 38 and the drain electrode 39. In addition, the outer edge of each of the source electrode 38 and the drain electrode 39 and the outer edge of the ohmic contact layer 36 coincide along substantially the same line.

Hereinafter, the second mask process according to the present invention will be described step by step based on the TFT region.

An amorphous silicon layer doped with a gate insulating layer 41, an amorphous silicon layer 42, and an impurity (n + or p +) is formed on the substrate 31 on which the gate conductive pattern group is formed, as shown in FIG. 8A. (Hereinafter referred to as " n + amorphous silicon layer ", for example, when the n + impurity is doped) 43, the source / drain metal layer 44, and the photoresist 45 are sequentially formed. As the gate insulating layer 41, an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like is used. As the source / drain metal layer 44, Cu metal for low resistance wiring is used. Subsequently, a second mask 46 is disposed on the substrate 31. As the second mask 46, a diffraction exposure mask or a transflective mask is used. Hereinafter, the case where a diffraction exposure mask is used is demonstrated as an example. The second mask 46, which is a diffraction exposure mask, includes a transmission region P1 that transmits ultraviolet rays, a diffraction exposure region P2 that diffracts the ultraviolet rays and transmits only a portion of the ultraviolet rays, and a blocking region P3 that blocks the ultraviolet rays. Equipped.

By exposing and developing the photoresist 45 using the second mask 46 described above, a photoresist pattern 47 having a partially different height is formed on the source / drain metal layer 44 as shown in FIG. 8B. Is formed. The photoresist pattern 47 has a step at a portion corresponding to the blocking region P3 and the diffraction exposure region P2. That is, the photoresist pattern 47A of the first height h1 is formed in the portion corresponding to the blocking region P3, and the photoresist pattern of the first height h1 is formed in the portion corresponding to the diffraction exposure region P2. A photoresist pattern 47B of a second height h2 having a height lower than 47A is formed. Thereafter, the exposed source / drain metal layer 44, the n + amorphous silicon layer 43 and the amorphous silicon layer 42 are sequentially etched and removed using the photoresist pattern 47. At this time, the source / drain metal layer 44 is wet etched, the n + amorphous silicon layer 43 and the amorphous silicon layer 42 are removed by dry etching.

As illustrated in FIG. 8C, the source / drain connection pattern 140 and the semiconductor pattern 37 are formed through the above-described etching process. Although not shown, the source / drain connection pattern 140 is formed simultaneously with the data line and the data pad lower electrode. The semiconductor pattern 37 is formed under the data line, the data pad lower electrode, and the source / drain connection pattern 140, and includes an active layer 35 and an ohmic contact layer 36. In the process of wet etching the source / drain metal layer 44, Cu used as the source / drain metal layer 44 may be rapidly etched at a portion contacting the edge of the photoresist pattern 47. Accordingly, the width of the source / drain connection pattern 140 formed through wet etching is smaller than the width of the photoresist pattern 47 overlapping the source / drain connection pattern 140.

Thereafter, by ashing the photoresist pattern 47 through an ashing process using plasma, as shown in FIG. 8D, the photoresist pattern 47A having the first height is thinned and the photoresist pattern 47B having the second height is thinned. Is removed. Accordingly, a portion of the source / drain connection pattern 140 corresponding to the photoresist pattern 47B of the second height is exposed. In addition, during the ashing process, both sides of the photoresist pattern 47A having the first height are simultaneously removed along with the removal of the photoresist pattern 47B having the second height. As a result, the outer edge of the semiconductor pattern 37 is exposed.

The exposed source / drain connection patterns 140 are removed through a wet etching process using the ashed photoresist pattern 47A as shown in FIG. 8E. At this time, the source / drain connection pattern 140 adjacent to the edge of the ashed photoresist pattern 47A is rapidly etched by the etchant as described above with reference to FIG. 7C. Accordingly, the source / drain connection pattern 140 is separated into the source electrode 38 and the drain electrode 39, and the width of each of the source electrode 38 and the drain electrode 39 is overlapped with the photoresist pattern ( It is formed narrower than the width of 47A).

Thereafter, the remaining photoresist pattern 47A is removed by the strip solution 182 sprayed through the nozzle 141 as shown in FIG. 8F. The active layer 35 is protected by the ohmic contact layer 36.

After completion of the strip process, the residue P of strip solution 182 remains on the ohmic contact layer 36 as shown in FIG. 8G and thus does not contaminate the active layer 35 serving as a semiconductor channel.

The exposed ohmic contact layer 36 is removed through a dry etching process using a source / drain conductive pattern group including the source electrode 38 and the drain electrode 39 as shown in FIG. 8H. The source / drain conductive pattern group may further include a data line and a data pad upper electrode. When the exposed ohmic contact layer 36 is removed, the semiconductor channel part 30 exposing the active layer 35 is formed between the source electrode 38 and the drain electrode 39. In addition, since the residue P remaining on the ohmic contact layer 36 is also removed while the ohmic contact layer 36 is removed, the residue P does not remain in the semiconductor channel part 30. Since the dry etching process according to the present invention is performed in a state where Cu is exposed, it is preferable to use one that does not damage Cu as an etching gas used in the dry etching process. That is, as the dry etching gas, one having a large difference in etching selectivity between Cu and amorphous silicon may be used. Examples are sulfur hexafluoride gas (hereinafter referred to as "SF ₆ gas"). Here, it is preferable that the SF ₆ gas does not include chlorine (Cl ₂ ) which easily corrodes Cu.

As described above, in the second mask process of the present invention, the photoresist pattern 47A is stripped after the source / drain conductive pattern group is formed and before the semiconductor channel portion 30 is formed. It doesn't work. In the present invention, since the semiconductor channel portion 30 is formed by the dry etching using the source / drain conductive pattern group after stripping the photoresist pattern 47A, the outer edge of the source / drain conductive pattern group and the ohmic contact layer 36 are formed. The outer edges of) coincide along substantially the same line.

9A and 9B are a plan view and a sectional view for explaining a third mask process of a TFT array substrate according to the present invention.

9A and 9B, a plurality of contact holes 49 are formed on the gate insulating layer 41 on which the semiconductor pattern 37 and the source / drain conductive pattern group are formed and the semiconductor channel portion 30 is exposed. , A protective film 48 including 134, 135 is formed. The protective film 48 may be an inorganic insulating material such as the gate insulating film 41 or an acryl-based organic compound having a low dielectric constant, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), or the like. Organic insulating materials are used. The plurality of contact holes 49, 135, and 134 may include a pixel contact hole 49 exposing the drain electrode 39, a gate pad contact hole 134 exposing the gate pad lower electrode 132, and a data pad lower electrode. And a data pad contact hole 135 exposing 133. The pixel contact hole 49 penetrates the passivation layer 48 to expose the drain electrode 39. The gate pad contact hole 134 passes through the passivation layer 48 and the gate insulating layer 41 to expose the gate pad lower electrode 132. The data pad contact hole 135 penetrates the passivation layer 48 to expose the data pad lower electrode 133.

10A and 10B are a plan view and a sectional view for explaining a fourth mask process of a TFT array substrate according to the present invention.

10A and 10B, a transparent conductive pattern group including the pixel electrode 40, the gate pad upper electrode 142, and the data pad upper electrode 143 is formed on the passivation layer 48 by a fourth mask process. . The pixel electrode 40 is connected to the drain electrode 39 through the pixel contact hole 49. The gate pad upper electrode 142 is connected to the gate pad lower electrode 132 through the gate pad contact hole 134. The data pad upper electrode 143 is connected to the data pad lower electrode 133 through the data pad contact hole 135. In addition, materials of the transparent conductive pattern group include tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (Indium tin zinc oxide): Transparent oxide conductive layer including ITZO).

As described above, in the present invention, after forming the source / drain conductive pattern group, the photoresist pattern is stripped without the semiconductor channel portion formed. Subsequently, in the present invention, the semiconductor channel portion is exposed by a dry etching process using a source / drain conductive pattern group, so that the residue of the strip process does not remain in the channel portion. Accordingly, the present invention can improve the electrical characteristics of the thin film transistor device.

In addition, in the present invention, since the semiconductor channel portion is formed by a dry etching process using a source / drain conductive pattern group after stripping the photoresist pattern, the same line is formed between the outer edge of each of the source and drain electrodes and the outer edge of the ohmic contact layer without stepping. Can be matched accordingly. Accordingly, the present invention can improve the electrical characteristics of the thin film transistor device.

In addition, since the present invention is made through a four mask process, which is a standard mask process, without adding or changing manufacturing equipment such as a mask, manufacturing cost according to a mask change is not added.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

A gate electrode formed on the substrate; A gate insulating film formed on the substrate to cover the gate electrode; An active layer overlapping the gate electrode on the gate insulating layer; An ohmic contact layer laminated on the active layer; A source electrode stacked on the ohmic contact layer and having an outer edge coincident with a line substantially the same as an outer edge of the ohmic contact layer; And a drain electrode facing the source electrode and the semiconductor channel portion where the active layer is exposed, and having an outer edge coincident with a line substantially the same as an outer edge of the ohmic contact layer and stacked on the ohmic contact layer. and; The source electrode and the drain electrode are thin film transistor array substrate, characterized in that made of a metal containing copper. The method of claim 1, A gate line connected with the gate electrode; The gate line includes a gate pad lower electrode connected to the gate line, a gate pad contact hole exposing the gate pad lower electrode, and a gate pad upper electrode connected to the gate pad lower electrode through the gate pad contact hole. A thin film transistor array substrate connected to the gate pad. The method of claim 1, A data line connected to the source electrode; The data line is A data pad including a data pad lower electrode connected to the data line, a data pad contact hole exposing the data pad lower electrode, and a data pad upper electrode connected to the data pad lower electrode through the data pad contact hole. The thin film transistor array substrate, characterized in that. The method of claim 3, wherein A lower portion of the lower electrode of the data line and the data pad And the active layer and the ohmic contact layer overlap each other. The method of claim 1, A passivation layer formed on the gate insulating layer and including a pixel contact hole exposing the drain electrode; And And a pixel electrode formed on the passivation layer and connected to the drain electrode through the pixel contact hole. Forming a gate conductive pattern group including a gate electrode of a thin film transistor on a substrate; Forming a gate insulating film on the substrate to cover the gate conductive pattern group; Forming a source / drain metal layer including an amorphous silicon layer, an amorphous silicon layer doped with impurities, and copper on the gate insulating layer; Forming a photoresist pattern of partially different height on said source / drain metal layer; Etching the source / drain metal layer, the amorphous silicon layer doped with impurities, and the amorphous silicon layer using the photoresist pattern to form a semiconductor pattern including an active layer and an ohmic contact layer; Ashing the photoresist pattern; Wet etching the source / drain metal layer using the ashed photoresist pattern to form a source / drain conductive pattern group including a source electrode and a drain electrode of the thin film transistor; Stripping the photoresist pattern with the ohmic contact layer remaining between the source electrode and the drain electrode; And Forming a semiconductor channel portion in which an active layer is exposed by dry etching using the source / drain conductive pattern group. The method of claim 6, In forming the semiconductor channel portion in which the active layer is exposed by dry etching using the source / drain conductive pattern group, outer edges of each of the source and drain electrodes coincide along a line substantially the same as the outer edge of the ohmic contact layer. A method of manufacturing a thin film transistor array substrate, characterized in that. The method of claim 6, And forming a semiconductor channel portion in which the active layer is exposed by dry etching using the source / drain conductive pattern group. The dry etching gas includes SF ₆ gas. The method of claim 6, The gate conductive pattern group includes a gate line connected to the gate electrode and a gate pad lower electrode connected to the gate line. The method of claim 6, The source / drain conductive pattern group includes a data line connected to the source electrode and a data pad lower electrode connected to the data line. The method of claim 6, After forming the semiconductor pattern Forming a passivation layer including a pixel contact hole exposing the drain electrode on the gate insulating layer; And Forming a pixel electrode connected to the drain electrode through the pixel contact hole on the passivation layer.

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