KR20080084801A - Improved phase reference generator with driving point voltage estimator for resistance welding - Google Patents

Abstract

An improved phase reference generator for use in resistance welding, and a method and system for estimating a driving point voltage of a resistance weld system. The method includes the steps of creating a volt-time area of the observed voltage, a current-time area of the observed current, a current-difference-time area of the observed current, an estimated line resistance, and an estimated line reactance of the system, and using them for creating a driving point voltage area or waveform. The estimated driving point voltage time area is used to drive the firing of a thyristor. The system includes circuitry for implementing the method for a resistance weld control.

Description

IMPROVED PHASE REFERENCE GENERATOR WITH DRIVING POINT VOLTAGE ESTIMATOR FOR RESISTANCE WELDING}

The invention claims the benefit of U.S. Provisional Patent No. 60 / 727,425, filed October 17, 2005, the contents of which are incorporated herein by reference. The invention also discloses US Patent Nos. 11 / 517,747, entitled "Phase Reference Generator with Driving Point Voltage," filed September 8, 2006, and "Method and System for Estimating Driving Point, filed September 8, 2006." Claims priority of US Patent No. 11 / 517,687 entitled " Voltage. &Quot;

The present invention relates generally to systems and methods for providing improved thyristor timing in an AC phase controller, and more particularly to systems and methods for providing improved timing for resistance welding operations.

In general, phenomena that can limit the performance of thyristors or silicon controlled rectifier (SCR) based phase controllers and especially resistance welding controllers are distortions of observed voltage waveforms caused by the presence of line impedance when current flows. to be. In a phase controlled resistance welder, accurate control of the current over several line cycles is required to generate the energy profile required to achieve strong and safe welding. In order to achieve this, firing pulses that trigger the SCRs are required to be accurately timing with respect to the AC power source applied to them. Current resistance welding control must therefore maintain an accurate internal time base with respect to the power source. This internal time base is referred to herein as a phase reference generator (PRG).

Traditionally, weld control maintains an internal time base where phase locked loop systems utilize a phase discriminator based on zero-crossing of the observed waveform to generate timing information from which an internal time base can be generated. . However, this method is inadequate for generating a time base for resistance welding applications because the flow of current to the welding point causes distortion in zero-crossing of the voltage waveform as observed by the welding control at the terminal of the welding point. Do.

Many attempts have been made to provide improved welding conditions. U. S. Patent No. 5,856, 920 discloses a method for estimating phase error between two independent time bases. In particular, the patent discloses a method for estimating the phase error between an internally maintained time base (phase reference generator) and the observed sinusoidal voltage. The method of estimating the phase error between two independent time bases comprises the steps of dividing the time base of the internal phase reference generator into "quadrants" and the observed complete value voltage-time region of the sinusoidal voltage across the quadrants. Incorporating. In one embodiment, the phase estimator calculates the ratio of the difference between the sum of the voltage-time domains of the first two quadrants and the sum of the last two quadrants, divided by the total sum of all quadrants. In another embodiment, the voltage-time domain of two adjacent quadrants is used to estimate the phase error.

US Pat. No. 5,869,800 discloses the use of a phase distortion compensation time base for welder control to improve timing of firing thyristors in solid state phase controlled resistance welder control.

U.S. Patent No. 5,963,022 includes the steps of observing a voltage, estimating phase distortion caused by coupling of an AC line voltage source to the load as a result of the load being supplied from phase angle ignition control in the presence of line impedance, and A method and apparatus are disclosed for tuning an internal time base to an observed line voltage based on adjusting an internal phase reference generator in response to an estimated phase distortion. The patent also discloses a system for observing phase errors resulting from observing line voltage waveforms under conditions in which the system does not conduct current, and estimating phase under current conditions without compensating for observed phase errors. Fixing the phase reference generator frequency and phase for one or more line cycles conducting this current, and then biasing the phase error in subsequent phase error samples by the observed amount while compensating for the biased phase error. Start the step. The method disclosed in this patent greatly improves the performance of resistance welding control, especially when the purpose of control is to generate a sequence of current pulses of the same current. However, in certain circumstances, especially when the current changes from the original value to the final value over multiple line cycles, the performance is better than a system without such compensation, but not as accurate as possible.

U.S. Patent No. 6,013,892 calculates an ignition sequence based on estimated line impedance models, open circuit line voltage, and an estimated relationship between load current and conduction angle and mathematical relationship between ignition angle, conduction angle and load circuit power. A phase controlled welding system is disclosed. The system also uses the measured values received in real time to correct the nominal firing angle. Such a system is also not as accurate as possible.

The present invention is provided to solve the problems discussed above and other problems and to provide advantages and aspects not provided by this type of conventional systems. A complete discussion of the features and advantages of the present invention will be in accordance with the following detailed description, which will proceed with reference to the accompanying drawings.

A method and system for improved timing of an AC phase controller, such as the resistance welding controller of the present invention. In particular, the improved method and system can be used with the EQ5400 AC Resistance Weld Control. Such welding control is used in resistance welded applications, including but not limited to automotive body assemblies.

The present invention improves the performance of the resistance welding control's ability to estimate the driving point voltage (open circuit voltage to be observed if no current flows) by estimating the driving point voltage waveform in real time under substantially all conditions. do. It is no longer necessary to "lock" the phase and frequency of the phase reference generator at the start of the weld. The present invention accomplishes this by estimating a simple circuit model for the power system and distribution system that provides power to the welding control, which includes an ideal, time varying drive point voltage source, a series of line resistances and a series of line reactances. Using estimated parameter values of line resistance and line reactance, the estimated drive point voltage-time domain is calculated and used in a conventional manner as a basis for generating a phase reference generator that automatically tracks the power source under all conditions. do.

In accordance with one embodiment of the present invention, the system estimates the drive point voltage magnitude and phase of an AC phase controlled resistance welding application with respect to an internal phase reference generator. The system improves tracking of the drive point voltage phase during welding. This results in more accurate timing of the thyristor firing point and consequently better current accuracy during resistance welding operation. The system also provides improved run to run load impedance estimation, resulting in more accurate feed-forward control. The system also provides improved line voltage compensation during welding.

In accordance with another embodiment of the present invention, a method and system are provided for estimating the drive point voltage of a resistance welding system. The method includes periodically sampling the supplied voltage and the supplied current of the system to obtain a plurality of sets of sampled voltage values and sampled current values. The sampled voltage and current are used to generate the voltage-time region of the sampled voltage, the current time region of the sampled current, and the current difference time region of the sampled current. The method includes determining whether a current flows, taking a first set of sampled voltage values and sampled current values when no current flows, and generating a sample of the sampled voltage value and sampled current values when current flows. Further comprising taking two sets. From these two sets of values, the method includes generating an estimated line resistance and an estimated line reactance of the system.

The method uses the voltage-time domain of the sampled voltage, the current time domain of the sampled current, the current difference time domain of the sampled current, the estimated line resistance, and the estimated line reactance to produce an estimated drive point voltage time domain. It further comprises the steps of using. The estimated drive point voltage time domain is used to drive the ignition of the thyristor of the resistance welding device.

Generating the voltage-time domain of the sampled voltage, generating the current time domain of the sampled current, and generating the current difference time domain of the sampled current may be performed on quadrant by quadrant logic. In this embodiment, periodically sampling the supplied voltage and the supplied current of the system includes sampling the supplied voltage and current a set number of times for each quadrant.

The method may further include various provisions to ensure that the estimated phase reference is in phase with the supplied voltage. In this regard, the method includes using the estimated drive point voltage time domain to calculate the phase error between the supplied voltage and the internal phase reference. The phase error can then be used to generate a drive point voltage waveform model in synchronization with the supplied voltage.

Circuits in the welding control of the resistance welding system, and components for measuring the supplied voltage and current, are used by the system to perform the method steps. The circuit can include a digital signal processor having firmware and / or software necessary to carry out the disclosed functions.

According to another embodiment of the present invention, a method of estimating a driving point voltage for timing ignition elements of a resistance welding device includes measuring a supplied current and a supplied voltage of a power distribution system at a plurality of predetermined intervals, Estimating line resistance and line reactance based on measured values of supplied voltage and supplied current and driving point voltage based on measured values of supplied voltage and supplied current and estimated line resistance and line reactance. Estimating. The estimated drive point voltage is used by the phase reference generator as timing logic to provide an ignition signal to the thyristor of the resistance welding device.

The method includes calculating a voltage time domain of the supplied voltage from the measured value of the supplied voltage, calculating a current time domain of the supplied current from the measured value of the supplied current, and measuring the measured current of the supplied current. The method may further include calculating a current difference time domain of the supplied current from the value. The voltage time domain, current time domain and current difference time domain are used to estimate the drive point voltage.

Estimating line resistance and line reactance includes measuring a first set of sampled voltage values and sampled current values when no current flows, and a second of sampled voltage values and sampled current values when current flows. Measuring the set, and generating an estimated line resistance and an estimated line reactance of the system based on the first set of sampled voltage values and sampled current values and the second set of sampled voltage values and sampled current values. It may include the step. The estimated line resistance and line reactance can also be used to estimate the drive point voltage.

The method may further comprise estimating a phase error between the supplied voltage and the estimated driving point voltage. The estimated phase error can be used to determine the phase difference between the phase of the estimated driving point voltage and the internal time base.

According to another aspect of the invention, a method is provided for estimating the drive point voltage of a resistance weld system. The method includes periodically sampling the supplied voltage and the supplied current of the system to obtain sets of sampled voltage values and sampled current values. And obtaining first, second, and third sets of sampled voltage values and sampled voltage values, and calculating current difference values for each of the first, second, and third sets. have. The method includes a first set of sampled voltage values, sampled current values and calculated current difference values, sampled voltage values, second set of sampled current values and calculated current difference values, and sampled voltage values, sampling Generating an estimated line resistance and an estimated line reactance of the system based on the third set of calculated current values and calculated current difference values.

The method may also include acquiring one of the sampled sets when no current is flowing (ie, when the current is zero). The method may include determining whether or not current is flowing and sampling voltage when no current is flowing. Selecting such a data set can simplify some of the calculations involved in determining the drive point voltage.

According to a further embodiment of the invention, a phase reference generator is provided for recording the drive point voltage waveform of a power distribution system for use in resistance welding control. The phase reference generator includes a digital signal processor, the digital signal processor comprising: a digital volt-time area generator for generating a voltage-time region of the observed voltage; A digital current-time domain and current-difference-time domain generator for generating a current-time domain of the observed current and a current-differential-time domain of the observed current; Line impedance estimator; And a driving point voltage domain estimator configured to receive values from the digital voltage-time domain generator, the digital current-time domain and current-difference-time domain generator, and to generate an estimate of the driving point voltage. . The phase reference generator can be used to provide an output signal for firing a resistance welder.

The phase reference generator further includes an analog-to-digital converter for converting each of the observed voltage and the observed current from an analog signal to a digital signal. The phase reference generator also includes an interval timer that triggers the analog-to-digital conversion of the observed voltage and observed current.

The phase reference generator may also include a phase error estimator. The phase error estimator is configured to estimate the phase difference between the estimated drive point voltage and the timing cycle generated by the phase reference generator. The phase error estimator is implemented in the firmware of the digital signal processor once for every timing cycle generated by the phase reference generator.

The phase reference generator further includes a compensator configured to adjust the frequency of the timing cycle to move the timing cycle toward a phase synchronized with the estimated drive point voltage. To accomplish this, the compensator increases the frequency of the timing cycle if the timing cycle is later than the estimated drive point voltage, or decreases the frequency of the timing cycle if the timing cycle is faster than the estimated drive point voltage.

The phase reference generator may further comprise a quadrant generator. The quadrant generator is configured to provide an indication of the current quadrant of the timing cycle.

According to another embodiment of the present invention, welding control for a resistance melting point system is provided. The weld control includes a phase reference generator configured to provide an estimated drive point voltage of the supplied voltage and generate a signal for firing the thyristor of the welding system during the welding operation. The weld control also includes a phase reference generator and a voltmeter function coupled to the input line to provide sampled values of the input line voltage, and a phase reference generator and an ammeter function coupled to the input line to provide sampled values of the line current. .

The phase reference generator may include a digital signal process. The digital signal processor may include firmware and / or software configured to function as a digital voltage-time domain generator, a digital current-time domain and current-difference-time domain generator, a line impedance estimator, and a driving point voltage-domain estimator. . The digital voltage-time domain generator generates an estimate of the input line voltage based on the sampled values of the input line voltage. The digital current-time domain and current-difference-time domain generators produce an estimate of the line current and the difference in line current from the sampled values of the line current.

The digital signal processor further includes a line impedance estimator. The line impedance estimator is configured to generate an estimate of line resistance and line reactance based on the first difference in measured input line voltage, measured line current, and calculated line current.

The digital signal processor further includes a driving point voltage-time domain estimator. The drive point voltage-time domain estimator is configured to provide an estimate of the drive point voltage-time domain based on an estimate of input line voltage, an estimate of line current, and a difference in line current, line resistance, and line reactance.

The digital signal processor further includes a quadrant generator for providing a phase reference generator timing cycle with frequency. Additionally, the digital signal processor includes a phase error estimator for estimating the phase error between the drive point voltage estimate and the internal system timing cycle. Based on the estimated phase error, the digital signal processor uses a compensator to adjust the frequency of the timing cycle to bring the timing cycle in synchronization with the drive point voltage.

According to a further embodiment of the invention, a digital phase reference generator for use in welding control is disclosed. The digital phase reference generator includes an interval timer configured to trigger an analog-to-digital conversion of the sampled input line voltage and the sampled input line current on a reoccurring basis. Input line voltage and current are provided by the power distribution system. The digital phase reference generator further includes a digital signal processor configured to execute an interrupt routine that is initiated by each completion of the analog-to-digital conversion of the sampled input line voltage and the sampled input line current. The number of interrupt routines define timing cycles, and the digital signal processor provides a voltage-time domain estimate of the input line voltage, a current-time domain estimate of the input line current and a current-difference-time domain estimate of the input line current, and a line impedance estimate. It is further configured to generate. The digital signal process is configured to provide a drive point voltage-time domain estimate of the input line voltage. The driving point voltage-time domain estimate is used as the basis for calculating the error between the timing of the phase reference generator and the driving point voltage. The phase reference generator is used as the timing basis for the firing of thyristors in a resistive redundant system. Unlike the conventional system in which the phase reference generator timing period remains constant during the first few cycles of welding, in which the system determines the phase error caused by the distortion of the driving point voltage by the line impedance, the present invention disclosed herein. The integrated system can keep track of the drive point voltage even when the welding current changes rapidly.

Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the following drawings.

BRIEF DESCRIPTION OF THE DRAWINGS In order to understand the present invention, exemplary embodiments will be described with reference to the accompanying drawings.

1 is a block diagram of a phase reference generator in accordance with an embodiment of the present invention.

FIG. 2 is a diagram that defines quadrants of the phase reference generator cycle when the phase reference generator is properly synchronized with the observed line voltage waveform.

3 is a block diagram of a phase reference generator compensation control system used in the phase reference generator of FIG.

4 is a flow chart of a quadrant generator.

5 is a block diagram of a digital voltage-time domain generator used in the phase reference generator of FIG.

6 is a block diagram of a digital current-time domain generator used in the phase reference generator of FIG.

7 is a block diagram of a driving point voltage-time domain estimator used in the phase reference generator of FIG. 1.

8 is a block diagram of a line impedance estimator used in the phase reference generator of FIG.

FIG. 9 is a block diagram of a run to run (R2R) autoregressive filter used in the line impedance estimator of FIG. 8.

10 is a logic flow diagram of a line impedance supervisor used in the phase reference generator of FIG.

11 is a block diagram of a phase error estimator used in the phase reference generator of FIG.

12 is a state diagram of a phase reference generator state machine.

13 is a table illustrating phase reference generator settings for resistance weld control.

FIG. 14 is a quadrant diagram of a phase reference generator cycle showing the relationship between PRG and input voltage sinusoids when PRG is synchronized with an input voltage sinusoid.

FIG. 15 is a quadrant diagram of a phase reference generator cycle illustrating the relationship between PRG and input voltage sinusoids when PRG is not synchronized with the input voltage sinusoid.

16 is a table of parameter values of a sampled data system.

FIG. 17 is a stem plot showing sample values of the voltage waveform with respect to the parameter values in the table of FIG. 16.

18 is a circuit diagram of an ideal circuit model for welding control.

19 is a circuit diagram of a system model for welding control with line impedance.

20 is a table of parameter values for the circuit of FIG. 19.

21 are waveforms of source voltage, observed voltage and welding current showing distortion due to the presence of line impedance.

22 is a centralized parameter circuit diagram of a resistance welding control and associated power distribution system.

23 is a line voltage waveform as a function of time and a line voltage waveform as a function of viewing angle.

24 is a simplified model of a welding circuit assuming no line impedance.

FIG. 25 is the voltage waveform resulting from the firing of the thyristor over time and the voltage waveform resulting from the firing of the thyristor for viewing angle.

FIG. 26 is a current waveform caused by applying the parameter values in the table of FIG. 27 to the welding current equation. FIG.

27 is a table of parameter values for the welding current equation.

While the invention is capable of many different forms of embodiments, it is to be understood that the invention is to be regarded as illustrative of the principles of the invention and is not intended to limit the broad features of the invention to the embodiments shown. Examples are shown in the drawings and will be described in detail.

Referring to FIG. 1, a block diagram of elements of a phase reference generator (“PRG”) 10 to provide improved tracking of line voltage to create a more precise firing point of a resistance welding device is disclosed. The invention is preferably performed in combination with resistance welding control, such as the EQ5400 AC resistance welding control, sold by Square D Company, to create a PRG timing cycle to match the drive point voltage of the power supply and distribution system. . EQ5400 AC resistance welding control can be modified to incorporate the features of the present invention as discussed below.

In an embodiment using the EQ5400 AC resistance welding control, a commercially available digital signal processor (DSP), preferably Model TMS320F2407A, manufactured by Texas Instruments, was used to analog-to-digital conversion of external voltage and current signals, digital signal processing. And timing generation. In this embodiment, the PRG timing is controlled by the hardware interval timer included in the DSP, and the interval of the DSP can be set under software control. When the timer period expires, it starts timing a new period and simultaneously initiates an analog-to-digital conversion of the sequence of selected signals independent of the current processing being performed by the DSP. This includes signals responsive to the instantaneous welding current and voltage observed at the input terminals of the welding control. Completion of the analog-to-digital conversion sequence triggers an interrupt in the DSP, which then waits for a while to execute the firmware interrupt routine. In this way, time critical operations can be performed at regular intervals in a timely manner. The particular DSP feature used is that the interval timer is "shadowed", meaning that when a new period is provided to the interval timer, this new period is applied at the expiration of the current interval.

In the EQ5400 AC resistance weld control implementation, the PRG cycle is defined at extended intervals by 128 interrupts taken by the DSP in accordance with the above description. Each PRG cycle is divided into four quadrants labeled ql, q2, q3 and q4 in FIG. Each quadrant represents an interval of 32 DSP interrupts. From the foregoing discussion, the time period of the PRG cycle is variable, and this feature allows the PRG cycle to synchronize with the observed sine waveform shown in FIG. 2 and discussed below. When the system is designed, the interrupt interval is constant within the PRG cycle.

The purpose of the PRG 10 is to synchronize the internal quadrant with the observed voltage source, so if the PRG cycle is synchronized with a pure magnitude sinusoidal voltage, the quadrant corresponds to (visually shown in Figure 2): The interval between the negative to positive zero crossing of the sinusoid and the positive vertex of the sinusoid; The second quadrant represents the interval between the positive vertex of the sinusoid and the zero crossing of the positive to negative sinusoid; The third quadrant represents the distance between the positive to negative zero crossing and the sinusoidal negative vertex; The quadrant 4 represents the interval between the negative vertex of the sine function and the zero crossing of the sine function from negative to positive.

1 is a plan block diagram of a closed loop system of the present invention for modeling, estimating and tracking drive point voltages. The various elements shown may be implemented in firmware and / or software of the DSP, and include additional elements of additional circuitry, sometimes referred to herein as a function of the PRG. The exponent "n", which appears in various quantities, refers to the nth PRG cycle after the reference cycle, typically the first cycle after the system has been driven. This exponent n is a mathematical entity and merges to use differential equations in the standard mathematical format. The value of the interrupt period, Ts (n + 1), for the next PRG cycle is supplied by the PRG compensator 1. The inputs to the PRG compensator 1 are the phase error sequence e (n) generated by the phase error estimator 2 and the "state" of the PRG generated by the PRG state machine 3 and labeled PRGState (n). "to be. When all the inputs required to run the PRG compensator for the current PRG cycle are available, the PRG compensator 1 is executed once per PRG cycle, sometimes at intervals in the four quadrants of FIG.

The interrupt period Ts (n + 1) generated by the PRG compensator 1 is supplied to the quadrant generator 4, which is a function residing in the DSP firmware. Quadrant generator 4 is executed once per interrupt. It declares to the system the current quadrant value q in the set {ql, q2, q3, q4}. It also supplies a universal logic signal (NQ) that, when set to TRUE, indicates the start of a new quadrant. The value of this logic signal is generally known to all functions in the PRG system. The quadrant generator 4 also manages the timing of the application of the new interrupt period, setting it at the transition between q4 of the current PRG cycle and q1 of the next PRG cycle. The PRG quadrant value q is the PRG state machine 3, the digital volt-time domain generator 5 labeled digital VTA in FIG. 1, and the digital current-time and current-time-time generator labeled digital ITA in FIG. (6) is input.

The digital VTA generator 5 is executed once per DSP interrupt and is observed for each quadrant from the quantized and digitized samples of the continuous analog line voltage waveform V _wc (t) generated by the DSP's analog to digital converter function. Generate an estimated V _wc TA (q, n) in the volt-time domain. The digital VTA generator 5 also produces an estimated AV _wc TA (q, n) of the absolute volt-voltage region observed in the manner described later.

The digital ITA generator 6 is also executed once per DSP interrupt, and with quadrant current-time estimation ITA (q, n) from the quantized and digitized samples of the instantaneous current generated by the DSP's analog versus digital converter function. The quadrant is generated by the estimated ΔITA (q, n) of the area of the first difference of the current.

The drive point VTA estimator function 7 is executed once per quadrant, and the line supplied by the line impedance estimator function 8 to generate the quadrant estimate V _dp TA (q, n) of the drive point volt-time area. V _wc TA (q, n) supplied by the digital VTA generator function 5 and the digital ITA generator function 6 together with the estimated values R ^* _line (m) and X ^* _leq (m) of the resistance. ITA (q, n) and ΔITA (q, n) values supplied by The importance of the index "m" in R ^* _line (m) and X ^* _leq (m) will be discussed later. Quadrant estimation of V _dp TA (q, n) is sent to the phase error estimator function 2, which is executed once per PRG cycle when drive point volt-time area estimation is available from the 2nd and 3rd quadrants. The phase error estimator 2 calculates an estimate of the phase error between the estimated open circuit source voltage waveform and the current timing of the PRG quadrants. The output of the phase error estimator 2 is a sequence e (n) of phase error values once per PRG cycle, which is sent to the PRG compensator 1 with closing the loop.

As mentioned above, the estimated sequences R ^* _line (m) and X ^* _leq (m) of the line resistance are supplied by the line impedance estimator function 8. This line impedance estimator function, along with the outputs supplied by the digital VTA generator 5 and the digital ITA generator 6, calculates a new line impedance estimate supplied by the line impedance monitor function 9 which will be described later. Use external perception of envy

In the block diagram of FIG. 1, the line impedance monitor function 9 executes a software signal command to determine which PRG cycles to calculate a new estimate of the line impedance parameters R ^* _line (m) and X ^* _leq (m). Supply to line impedance estimator function (8). The index “m” in line impedance parameter values refers to the mth update of the line impedance parameters from the initialization of the system since power was first applied.

FIG. 3 shows a system block diagram of the PRG compensator function 1 of FIG. 1. In the EQ5400 AC resistance weld control, these functions are fully implemented in the DSP firmware. The PRG compensator function 1 is the time Ts after quadrant q3 and when the quadrant generator 4 sets the base sample rate for the next PRG line cycle when the most recent phase error estimate e (n) is available. At (n + 1), it is executed once per PRG cycle.

The PRG compensator 1 slightly increases the internal PRG frequency to "catch up" the estimated drive point voltage signal if the PRG timing cycle phase is lag than the estimated drive point voltage signal, or the estimated If the phase error indicates that the PRG timing cycle is lead over the external drive point voltage signal, the PRG timing cycle and estimated drive are reduced by reducing the internal PRG frequency so that the estimated drive point voltage signal can "catch up" with the PRG timing. An attempt is made to derive the estimated phase error between the point voltage signals.

Mathematically, there are three internal state variables maintained by the PRG compensator function 1 in FIG. 3, labeled x0 (n), xl (n) and x2 (n). The state variable x2 (n) represents the cumulative sum of the phase errors since the PRG compensator 1 was started in a manner to be described later. The state variables x0 (n) and x (n) are integrated so that the response of the system can be fully controlled, resulting in a timing adjustment at the quadrant transition between q4 of the current cycle and q1 of the next cycle, while phase error is Accept the fact that it is estimated at the point in the center of the PRG cycle. Using well understood techniques of modern linear control theory, it can be seen that when coupled to a system such a system is fully controllable in control system sensing and the response of the system can be set to any reasonable desired value.

In matrix format, the form of the state difference equation describing the PRG compensator function 1 is:

Where output Ts (n + 1) is given by:

Where kxO, kxl, ki, kp, and K2 are control system parameters and the value Ts _nom represents the expected base sample period. Specific values of these constants depend on the state of the PRG generator 10 and are provided by the PRG state machine 3 in the state variable PRGState (n + l). The discussion of actual parameter values used as a function of system state is deferred to the description of the PRG state machine.

Quadrant generator 4 is also implemented in the DSP firmware and runs at each DSP interrupt in the system. 4 is a flowchart showing the process of the quadrant generator 4. Quadrant generator 4 maintains an internal counter SC of DSP interrupts from the beginning of the current PRG quadrant. When entering 401 at the kth DSP interrupt after the start of the current PRG quadrant, quadrant generator 4 initially increments the value of the SC counter in process block 402. In decision block 403, the DSP compares the value of the counter SC with a constant value SPQ to indicate the number of DSP interrupts per quadrant. In the implementation of the EQ5400 AC resistance welding control, the SPQ is 32. If the value of SC is less than or equal to SPQ, control passes to control block 404, where the new quadrant signal NQ is set to FALSE, indicating that this base sample does not indicate the beginning of a new quadrant. The value of this signal is generally known to the system. Once the NQ beacon is set to FALSE at 404, the quadrant has not changed, so the system at process block 405 replaces the current quadrant value, q (k) with the previous value, q (k). Set to -1).

In decision block 406, the quadrant generator 4 finds the particular condition of the last DSP interrupt in quadrant q4. This condition is indicated by both of the following conditions which are true.

q (k) = q4 (3)

SC = SPQ-1 (4)

If any of these conditions is FALSE, the routine is typically at 408. If both conditions are true, the quadrant generator 4 loads the DSP's hardware interval counter with the value Ts (n + 1) obtained from the PRG compensator 1. This typically occurs first at process block 407 prior to being present at 408. As previously discussed, this new setpoint value will be loaded next to set the DSP interrupt period, the interval counter reaches its setpoint value, and the interval counter's setpoint value is over the next PRG cycle. The exact moment to set the DSP interrupt cycle.

Referring back to decision block 403, if the sample count SC is equal to or greater than the constant value SPQ, it is time to transition to the new quadrant, and process blocks 409, 410, and 411 are executed sequentially. . In process block 409, the counter SC is reset to zero. At process block 410, the value of quadrant, q (k), is increased. At process block 411, the value of the new quadrant signal, NQ, is set to TRUE, indicating to the remaining PRG functions that this DSP interrupt represents the first quadrant of the new quadrant.

Control is then passed to decision block 412, where in block 412, the increased quadrant value q (k) is compared in process block 410 so that the new quadrant value is in the range {q1, q2, q3. , q4}. If so, the routine is typically at 408. If not, the quadrant value q (k) is set to q1, indicating the start of a new PRG cycle. Control then typically resides at 408.

5 is a block diagram of the digital VTA generator 5. The digital VTA generator 5 has an observed line input of weld control for each quadrant q∈ {q1, q2, q3, q4} of the PRG labeled V _wc TA (q, n) in FIG. Generates the volt-time domain estimates of the line voltage at and yields both AV _wc TA (q, n) for each quadrant formed by first taking the absolute value of the observed welding voltage to produce a trapezoidal accumulation. In the EQ5400 AC resistance weld control, the digital VTA generator function is implemented in a combination of analog electronic circuits, digital electronic circuits and digital signal processing firmware. The original analog voltage line voltage input signal V _wc (t) is the signal that appears at the power input of the welding control. This is a power line voltage signal and typically has a nominal value of 480 volts RMS in an auto body shop in the United States. The power system can also supply very large currents to anything connected to it. Thus, in order to limit the potential current that may flow into the digital VTA function to safe levels while simultaneously reducing the voltage observed by the system to levels that low voltage digital and analog circuits can afford. 21) is incorporated into the design. In the EQ5400 AC resistance welding control, the voltage attenuator circuit comprises two commercially available, high-voltage voltage divider networks based on thick film technology. The output of the voltage attenuator circuit 21 is a signal V _wca (t) responsive to V _wc (t) but attenuated by approximately 125: 1 times, so that a sine wave voltage signal of 480 V RMS at the input is attenuator. It appears as a sine wave signal of about 3.84 V RMS at its output.

The analog signal V _wca (t) is supplied to the anti-aliasing filter 23, and the anti-aliasing filter functions to band limit the signal supplied to the A / D converter function 25. As can be seen in the study of sampled data systems, in order to faithfully represent an analog signal as a sequence of digital samples, the sampled signal should only be band limited to half the sampling frequency, or commonly referred to as aliasing. Will confuse the results. In the EQ5400 AC resistance weld control, the six-pole elliptic filter is implemented with analog hardware that band-limits the sampled signal. The attenuated, band limited representation of the line voltage signal is labeled V _wcf (t) in FIG. 5.

The analog-to-digital converter function 25 is integrated into the DSP and samples the signal V _wcf (t) in response to V _wc (t) once per DSP interrupt. The sample period for a given PRG cycle is Ts (n), calculated by the PRG compensator 1 and set by the quadrant generator 4. Analog-to-digital converters quantize each sample into 10-bit numbers in a form that can be used by the DSP. This numerical sequence is labeled V _wes (k) in FIG. In EQ5400AC resistance weld control, the 128 samples are taken per PRG cycle.

The sampled and quantized sequence V _wes (k), generated by the DSP's A / D converter function, is supplied to a functional block labeled with a trapezoidal integrator / accumulator 27 in FIG. This function is implemented in the DSP firmware and estimates the volt-time region of each quadrant by accumulating samples on the quadrant using a trapezoidal integration rule.

(5)

(5)

Here, index j refers to the basic samples V _wes (k), but is referenced at the start of the nth PRG cycle. This function forms the four estimates per PRG cycle. The previous quadrant estimates are complete, and the new estimate begins when the universal quadrant signaler NQ is received from the quadrant generator 4. In order to generate the sequence AV _wc TA (q, n), supplied by the digital VTA function and used by the PRG state machine 3, the mathematical absolute value of the sequence V _wes TA (k) is first adopted (see Shown by number 28). The output of this absolute value function, labeled AV _wes TA (k), is fed to another trapezoidal integrator 29 which operates in the same way as generating the sequence V _wes TA (k). The output of the trapezoidal integrator 29 is the sequence AV _we TA (q, n), shown in FIG.

FIG. 6 shows a block diagram of the digital ITA generator function 6 of the PRG system 10 for estimating the current-time region (ITA) and current time-difference region of each PRG quadrant. As in the case of the digital VTA generator function 5, this function is implemented by a combination of electronic hardware and DSP firmware. In the EQ5400 AC resistance welding control, the welding current is delivered through a commercially available passive AC current transformer 31 with an associated load resistor. The current transformer 31 generates a secondary current that is proportional to the main welding current passing through its aperture. When this current passes through a load resistor attached across the secondary side of the transformer, a voltage V _ct (t) is produced. As in the digital VTA generator function, the voltage V _ct (t) is filtered by an analog six pole elliptic anti-aliasing filter 32. The resulting band limited signal is labeled V _ctf (t) in FIG. 6.

In response to the instantaneous welding current, the band limited signal V _ctf (t) is sampled at a rate Ts (n) established by the PRG compensator 1 and the quadrant generator 4 by the DSP analog-to-digital converter 33. The DSP analog-to-digital converter is an analog-to-digital channel separate from the analog-to-digital converter of the digital VTA generator function unit 5, or operates in the same manner as the analog-to-digital converter of the digital VTA generator function unit 5. It is necessarily sampled at the same instant as the analog-to-digital converter of the digital VTA generator function 5. The sequence of numbers resulting from this sampling and quantization is labeled i (k) in FIG.

The sequence i (k) is fed directly to the trapezoidal integrator / accumulator 35, and the trapezoidal integrator / accumulator 35 operates in the same manner as described in the digital VTA generator function 5, one per PRG quadrant. Generate quadrant estimates of the time domain ITA (q, n), where q \ {q1, q2, q3, q4}. The sequence i (k) is also supplied to a current difference function 37, which generates the sequence Δi (k) as follows.

Δi (k) = i (k) -i (k-1) (6)

This signal is fed to another trapezoidal integrator / accumulator 39, one per PRG cycle quadrant, the current-difference-time domain, quadrant of ΔITA (q, n), where q∈ {q1, q2, q3, q4} Generate estimates, where the trapezoidal integrator / accumulator 39 also operates in the same manner as described in the digital VTA generator function 5.

FIG. 7 is a block diagram describing the operation of a driving point VTA estimator function 7. This function is executed once per quadrant upon transition from one quadrant to another to generate quadrant open circuit VTA estimates V _dp TA (q, N) used by the phase error estimator (2). Once all the data is available, the system performs the calculation of FIG. 7 implementing the following equation.

(7)

(7)

FIG. 8 is a block diagram of the line impedance estimator function unit 8, wherein the line impedance estimator function unit 8 supplies line impedance estimates R ^* _line (m) and X ^* _leq (m) to the drive point VTA estimator 7. ). The line impedance estimator function 8 is conditionally executed at certain points in time to update the estimates of line resistance and reactance. The command to perform the update is represented by a logical assertion of the signal LI_COMPUTE, which is sometimes asserted to be discussed subsequently by the Line Impedance Supervisor function 9. The index m of values R ^* _line (m) and X ^* _leq (m) refers to the update of the m-th commanded line impedance values.

및

의 새로운 추정치를 생성한다. 상기 n번째 라인 주기에서, LI_COMPUTE 신호가 단정될 때, 모두가 디지털 ITA 생성기(6)에 의해 제공되는 값들

,

,

, 및

뿐만 아니라 디지털 VTA 생성기(5)에 의해 제공되는 값들

및

, 그리고 앞서 언급된 지연된 볼트-시간 영역 값들

및

이 추정기 매트릭스(83)를 공급한다. 추정기 매트릭스(83)는 하기의 공식에 따라 출력들 R(m) 및 X(m)을 생성한다 :In the implementation of the EQ5400 AC resistance weld control, the line impedance estimator 8 continuously maintains the memory of the previous value for the observed VTA estimates for quadrants 2 and 3. These signals are represented as the outputs of the unit delay blocks 81 and 82 in FIG. 8 and are labeled V _wc TA (q2, n-1) and V _wc TA (q3, n-1), respectively. As determined by the assertion of the LI_COMPUTE signal, the line impedance estimator 8 at the time of line impedance values

And

Create a new estimate of. In the nth line period, all values provided by the digital ITA generator 6 when the LI_COMPUTE signal is asserted.

,

,

, And

As well as the values provided by the digital VTA generator 5

And

, And the aforementioned delayed volt-time domain values

And

This estimator matrix 83 is supplied. The estimator matrix 83 produces outputs R (m) and X (m) according to the following formula:

(8)

(8)

Where R (m) and X (m) are instantaneous estimates and inductive reactances of resistance for the m th estimate, respectively. Mathematics beyond the matrix formula will subsequently be derived.

The assumptions considered in calculating the line impedance estimates are: 1) there is only one device that loads the weld bus at any time, and 2) the drive point voltage is a sinusoid and the interval on which the calculation is based. Is kept constant throughout. However, individual welding control does not know in advance the presence or activity of other devices that can draw current from the welding power bus, and other equipment is not able to make one or both of these assumptions over the line periods in which the estimate was generated. It is recognized that there may be an error in the instantaneous estimate produced by Equation (8) above in case of a violation of the welding bus load. To help alleviate this condition, each of the values R (m) and X (m) is filtered utilizing run-to-run (R2R) filters 85 and 87. A block diagram for the form of the same filters is shown in FIG. 9. The filters are autoregressive filters having the following general form:

(9)

(9)

또는

이다.Here, u (m) is input to a (R (m) or X (m) of Fig. 8) the filter, x (m) is an internal state variable, K _f is a filter coefficient 0≤K _f ≤1 Y (m) is the output of the filter, respectively,

or

to be.

Run-to-run filters tend to "smooth out" errors that can be generated in individual impedance estimates, and are more consistent than those made by using individual estimates R (m) and X (m). Derive estimates. Indeed, using the unfiltered individual estimates R (m) and X (m) directly (which can be done by setting K _f = 1) yielded perfect results-run to run filters are essential for the operation of the present invention. And should not be considered as limiting the invention. However, for operation in noisy environments such as car repair shops, it has been experimentally found that the inclusion of these run-to-run filters with K _f = 0.25 provides an additional means of noise immunity against conditions in which these assumptions are violated. lost.

The function of the line impedance management function 9 is to determine in which periods of the PRG the line impedance estimate function 8 is executed. In this embodiment, it is an object to implement the line impedance estimator 8 in a first period in which current flows, with several periods in which no current flows following the first period. In typical vehicle applications, resistance welding control is generally idle for a few seconds, while some or all of the vehicle is moved to the welded state. During this period of time when no current flows, the PRG 10 may acquire an undistorted drive point voltage waveform of the power system. If it is assumed that the voltage waveform of the power source does not vary much from cycle to cycle, it can be assumed that the voltage waveform in the last line period before welding represents the drive point voltage waveform of the power source in the first period in which welding started. The function of the line impedance management function 9 is to monitor the system for such conditions and to trigger the execution of the line impedance estimator function 8 when a suitable condition is detected.

10 is a flowchart of a line impedance management function 9 which is a DSP firmware entity executed once per PRG period. The integration for the line impedance management function 9 is a static IDLE counter, and the line impedance management function (to determine when the system is idle for a period of time sufficient to ensure that the PRG reliably follows the power source voltage waveform) 9) are used. Referring to FIG. 10, upon input to firmware logic at 1401 during line period n, first the line impedance management function 9 first determines at block 1403 whether the system is welded during line period n. Decide If it is assumed that the system is not welded during line period n, then flow proceeds to process block 1405, where the integral IDLE counter is incremented by the DSP. Once the counter is incremented, in decision block 1407, the result count is compared with an integer number N _LI , which is a design parameter that indicates the minimum number of non-welding cycles required to ensure that the PRG accurately follows the power source voltage. do. If the value of the idle counter is greater than N _LI , the precondition number of non-welding periods has been met and the value of the count is set to N _LI in process block 1409. Proceeding to process block 1411 is made, where the LI_COMPUTE semaphore is set to a logical FALSE value, which indicates to the line impedance estimator 7 that no update of line impedance should be performed.

If the line impedance management function 9 determines in block 1407 that the value of the IDLE counter is less than or equal to N _LI , control is passed directly to process block 1411 and the LI_COMPUTE semaphore is a logical FALSE value as described above. Is set. Once process block 1411 is executed, the routine ends at 1413 until it is executed again in the next PRG cycle.

Referring back to decision block 1403, if it is determined that a welding current is flowing in welding period n, control passes to decision block 1415, where the value of the IDLE counter is compared to the value N _LI . If it is determined that the value of the IDLE counter is not exactly equal to the value N _LI , an insufficient number of non-welding periods have been detected to ensure a new estimate of line impedance. This condition exists when a break occurs between individual welds below N _LI line periods or because the system is shortly in the middle of performing the weld. In either case, if an insufficient number of non-welding cycles are detected by the routine, the LI_COMPUTE semaphore is set to logical FALSE state at process block 1417 and the IDLE counter value is set to zero at process block 1419.

At decision block 1415, if the IDLE counter value is equal to N _LI , then the conditions for executing and updating the line impedance estimate are met. Control is passed to process block 1421, where LI_COMPUTE semaphore is set to TRUE. Once so set, control is passed to process block 1419, where the IDLE counter value is set to zero as above. Once process block 1419 is executed, the routine ends at 1413 as above until executed again in the next PRG cycle.

및

가 구동점 전압 추정기(7)에 의해 생성된 이후 사분면(q4) 동안에 PRG 주기당 한 번 실행된다. 각각의 라인 주기 n 동안에, 상기 블록은 사분면들(2 및 3)로부터의 개방 회로 볼트-시간 추정치들, 즉

및

를 활용하고, 상기 개방 회로 볼트-시간 추정치들은 내부 시간 베이스(즉, PRG 타이밍 주기) 및추정된 구동점 전압 사이의 에러를 추정하기 위해 구동점 전압 추정기(7)에 의해 공급된 것이다. 도 11의 블록도는 하기의 수학식을 구현한다 : 11 is an enlarged block diagram describing the phase error estimator 2 of the PRG system. The function is implemented in the DSP firmware, and the drive point voltage estimates from quadrants 2 and 3

And

Is executed once per PRG period during quadrant q4 after is generated by the drive point voltage estimator 7. During each line period n, the block has open circuit volt-time estimates from quadrants 2 and 3, ie

And

And the open circuit volt-time estimates are supplied by the drive point voltage estimator 7 to estimate the error between the internal time base (ie, the PRG timing period) and the estimated drive point voltage. The block diagram of FIG. 11 implements the following equation:

(10)

10

How the above equation estimates error will be discussed later.

The PRG state machine 3 determines the state of the PRG, and if nothing is known about the relationship between the PRG timing and the actual power system timing, the initialization process causes the PRG to be declared "synchronized" with the power system and welded. Guide to the point where it can begin. 12 shows a system state diagram of the PRG state machine 3. The output of the PRG state machine 3 is a PRG state variable PRGState (n) that takes the value of the set {NOSYNC, SYNCING, SYNC}.

을 관찰하고 사분면(q2)으로부터 사분면(q3)으로의 전이 부근에서 상기

의 양으로부터 음으로의 제로 크로싱(the positive to negative zero crossing)이 이루어지도록 PRG 사분면들을 정렬하는 것이다. 상기 조건이 존재하는 것은 하기의 세 가지 조건들의 충족에 의해 결정된다 :The PRG state machine 3 is implemented in the DSP firmware and runs when the PRG is in quadrant 4 after the phase error estimator 2 is executed during the current PRG period. From the power-on state indicated by PON in Fig. 12, the system state is immediately set to NOSYNC. When the system is in the NOSYNC state, nothing is estimated about the relationship between the PRG quadrants and the observed line voltage waveform. The purpose of the PRG (10) in the NOSYNC state is the line voltage

Is observed and is located near the transition from quadrant q2 to quadrant q3.

The PRG quadrants are aligned to achieve the positive to negative zero crossing. The presence of such conditions is determined by the fulfillment of three conditions:

은 최소값보다 더 크다. 상 기 조건은 시스템이 실제로 단지 전력 시스템의 개방 회로 조건에 따른 불규칙 잡음이 아니라 최소값의 전력 시스템에 의해 전달되는 실제 전압을 쫓고 있음을 보장하기 위해 요구된다. EQ5400 AC 저항 용접 제어의 실제 설계에서, 상기 조건을 충족시키기 위해 요구되는 최소 AVTA는 라인 전압이 PRG와 적절하게 동기화될 때 30볼트 RMS의 사인 전압 입력을 인가함으로써 획득될 수 있는 이론적 값이다(그러나, 다른 전압들이 사용될 수도 있다).Condition 1: The sum of the absolute volt-time regions of the quadrant from the preceding line period, also referred to as AVTA (n-1) in the future, i.e.

Is greater than the minimum value. This condition is required to ensure that the system is actually chasing the actual voltage delivered by the power system of the minimum value, not just random noise due to the open circuit conditions of the power system. In the actual design of the EQ5400 AC resistance welding control, the minimum AVTA required to meet the above conditions is a theoretical value that can be obtained by applying a sine voltage input of 30 volts RMS when the line voltage is properly synchronized with the PRG (but Other voltages may be used).

Condition 2: The value of V _dp TA (q2, n) is a positive value and the value of V _dp TA (q3, n) is a negative value. This indicates that zero crossing of the power waveform to be "tracked" occurs somewhere between the current quadrants q2 and q3.

Condition 3: The error value e (n) calculated by the phase error estimator is "sufficiently small" to allow the PRG to start a closed loop acquisition. For the EQ5400 AC Resistance Weld Control, this value is approximately 22.4 °.

When in the NOSYNC state, the EQ5400 AC Resistance Weld Control is not allowed to conduct current. As an intended result of this, the drive point voltage is the same as observed by the system at the input terminal of the EQ5400 AC Resistance Weld Control. In order to achieve a nominal alignment between the PRG 10 and the input sinusoid, the PRG compensator constants kx0, kx1, ki, kp and K2 shown in FIG. 3 remain forced to zero when the system is in the NOSYNC state. Is set to the values x0 (n), x1 (n), and x2 (n) and zero of the state variables being set, so that the PRG 10 does not change the interrupt sampling period from the nominal value TS _nom . . This induces a fixed PRG cycle frequency and at the same time induces a NOSYNC mode.

The nominal operating line frequency voltage of the welding control system is assumed to be known a priori. For example, it is known that the system is intended to operate at a nominal line frequency of 60 Hz in North America, and that frequency will be very accurately adjusted by a power utility that generates powers-typically within +/- 0.2 Hz. When in NOSYNC mode, the EQ5400 AC Resistance Well Control utilizes the value of TS _nom to generate a PRG frequency that is 1 Hz less than the expected operating frequency. For example, for a system intended to operate at 60 Hz, TS _nom is set to 132 Hz, which leads to a PRG cycle frequency of approximately 59 Hz. Thus, in situations where the positive-negative zero crossing of the actual observed line voltage occurs outside of quadrants q2 and q3, the zero crossing of the line voltage in each subsequent PRG cycle is in the current PRG cycle rather than in the previous PRG cycle. It will happen earlier and sometimes "overlap" in the next PRG cycle. Eventually, zero crossing will occur near the transition between q2 and q3 of the PRG. Under certain conditions, assuming linear frequency is a nominal value, the estimated phase error should change by only 6 ° per PRG cycle, assuming that condition 1 is achieved and the waveform observed is actually sinusoidal in nature. In other words, it ensures that the remaining conditions can be met in 1/3 second under normal circumstances. For systems operating nominally at 50 Hz, TS _nom is chosen so that the nominal PRG cycle frequency is approximately 49 Hz.

Once the above conditions are met, the PRG state machine declares that the PRG is in SYNCO state. In this state, the values of TS _nom remain fixed at the NOSYNC setting, but the constants kx0, kx1, ki, kp, and K2 are set to their operating values. The table in FIG. 13 provides parametric values of the PRG compensator 1 currently being used in the EQ5400 AC Resistance Weld Control for 60 Hz operation.

The values x0 (n), x1 (n) and x2 (n) of the state variables shown in FIG. 3 are explicitly initialized to zero when the SYNCO state is entered first. However, unlike the NOSYNC state, they do not remain zero but are allowed to assume values according to the operation of the PRG compensator 1 described above.

When operated in a closed loop scheme according to the PRG system 10 described herein, the selected parametric values can provide a good system response with good disturbance rejection, which is zero in response to appropriate power system line voltages. It derives the estimated phase error sequence e (n) that is directed to and also establishes the relationship between the observed power voltage waveform and the PRG required in FIG.

Once the PRG constant values are set and the state variables are initialized to zero, the PRG 10 is allowed to operate in the SYNCO state, until the interrupt duration Ts (n + 1) until one of the three events below occurs. Calculate the modifications to

(1) The observed error e (n) is below a fixed threshold for more than a fixed number of consecutive PRG cycles. (2) The observed error e (n) is greater than the fixed threshold for more than a fixed number of consecutive PRG cycles. In the EQ5400 AC Resistance Weld Control, this fixed number is 30 in both cases. (3) The total AVTA observed during the previous line cycle is less than the minimum value provided in the description of the NOSYNC state above.

For the EQ5400 AC Resistance Weld Control, the error threshold set in the case of the SYNCO state is approximately 11.25 °. If condition 1 is met, the PRG transitions to the SYNC state. If either condition 2 or condition 3 is met first, the PRG switches back to the NOSYNC state. Under "normal" operating environments it is noted that the error threshold condition that is met during 30 consecutive cycles requires setting a very small phase error until a switch to "SYNC" is made. In the case of a system operating at 60 Hz, this corresponds to 1/2 second of stable operation under normal conditions.

Upon switching from SYNCO to SYNC state, the values of the state variables x0 (n), x1 (n) and x2 (n) shown in FIG. 3 are initialized to zero, and the value of TS _nom is from the SYNCO state. It is set to TS (n) which is the last generated interrupt duration value. Under normal conditions, this new value of TS _nom creates a PRG cycle period very close to that of the line voltage, so that the system now makes minimal modifications to the interrupt sample period for the PRG to maintain synchronization with the line voltage. I only need them.

In the SYNC state, the EQ5400 AC Resistance Weld Control is allowed for welding. Once in the SYNC state, the PRG remains in that state until one of the following two conditions occurs.

Condition 1: The magnitude of the error estimate e (n) exceeds approximately 22 ° for more than five consecutive PRG cycles, in which case the system switches back to the SYNCO state. This causes the PRG to generate any minimum disturbance that may occur in the power system, while at the same time disabling welding if the disturbance is large and also attempting to reacquire synchronization with the line voltage.

Condition 2: The total AVTA observed over the previous line cycle is less than the minimum AVTA described in the NOSYNC state description above. If this happens, the PRG immediately drops to the NOSYNC state, and the system is initialized and operated according to the description of the NOSYNC state above.

Phase reference generator 10 in the welding timer provides a timing basis for ignition of the thyristor. It also drives the timing of the RMS current estimator function (digital current meter) as well as the RMS voltage estimator function (digital voltmeter). The phase error estimation method is based on integrating some of the observed input line voltages into the system.

The following description presents formulas useful for understanding the operation of the present invention in AC resistance welding applications.

In the mathematical circuit model of the power distribution system, the voltage generated by the power generation and distribution system can be modeled as an ideal drive point voltage source (V _dp (t)) in the form of equation (11):

식(11)

Formula (11)

는 기준 시간 t=0에 대한 사인곡선의 위상이고, V_m(t)는 시간의 함수로서 표기되는 피크 전압이다. 이러한 논의의 시점에서는, V_m(t)가 시간에 따라 변하는 조정 항이라는 것이 인지된다. 분석을 간단하게 할 V_m(t)의 반응에 대한 가정들이 그로 인해서 이루어질 것이다.Where f is the frequency,

Is the phase of the sinusoid with respect to the reference time t = 0 and V _m (t) is the peak voltage expressed as a function of time. At the point of this discussion, it is recognized that V _m (t) is an adjustment term that changes over time. Assumptions on the response of V _m (t) will thereby be made which will simplify the analysis.

The purpose of the phase reference generator 10 of the present invention is to create an internal time base that can continuously track the drive point voltage V _dp (t) to ensure that the following two conditions are maintained: Condition 1: Phase The basic period T of the reference generator corresponds to f in equation (0.11). Condition 2: The phase error observed between the PRG and the voltage source V _dp (t) is zero at the positive-negative zero crossing of the sinusoidal waveform.

Referring to equation (11), the basic assumption in the present analysis is that the input power source for the welding control is a fixed and closely known sinusoidal source of frequency, but is unknown for the internal phase reference generator 10. It is a fixed phase. It is also assumed that the voltage adjustment term V _m (t) in equation (11) above is slowly changing and also effectively constant over the interval on which the calculations are based.

Although the phase reference generator 10 does not inherently generate a waveform, the timing of the PRG may be viewed as a square wave of frequency twice that of the fundamental period of the sinusoidal curve it attempts to track. In this representation, one PRG cycle includes two cycles of a square wave. This concept is used in the practical implementation of the PRG in a digital signal processor (DSP) because it is possible for the DSP to generate a square wave as an output, so it can be observed for a sinusoid using an oscilloscope.

Figure 14 shows this representation with its input sinusoid assuming that the phase reference generator is in complete synchronization with the input sinusoid. In this representation, four “transitions” of the phase reference generator can be identified during each cycle of the sinusoid by dividing the sinusoid into quadrants q1, q2, q3 and q4 in FIG. 14. It is important to note that "quadrants" are defined for a PRG that may or may not be synchronized with the sinusoid.

The analog-to-digital converter function of the EQ5400 AC Resistance Weld Control, by design, is synchronized with the PRG and takes a constant number of uniformly spaced samples of the line voltage waveform per internal PRG line cycle. In a practical implementation of the EQ5400 AC Resistance Weld Control, the analog-to-digital converter generates 128 such digitized voltage samples per PRG cycle, or 32 samples per quadrant. It is assumed that there is a function residing in the system that can generate a true mathematical integral of voltage across each quadrant of the PRG. Of interest in this analysis is the voltage-time domain on quadrants q2 and q3 representing the shaded regions VTA2 and VTA3 in FIG. 14. Since the sinusoidal curve has radix symmetry around the 180 degree point, when the PRG is synchronized with the sinusoidal curve in FIG. 14, the voltage-time regions VTA2 and VTA3 have the same but opposite signs, so that the regions When added, it can be seen that the net sum of the voltage-time domain is zero.

This is not the case when the PRG is not synchronized. FIG. 15 shows the lag conditions of the transition from q2 to q3 of the PRG by the positive to negative zero crossing angle ε of the input voltage. In this case, it can be easily seen that the voltage-time regions represented by VTA2 and VTA3 do not have the same magnitude. 14 and 15, it can be seen that the calculated magnitude of VTA2 when the PRG derives the input voltage is larger than when the PRG is synchronized, and the calculated magnitude VTA3 is smaller than when the PRG is synchronized. Thus, VTA2 and VTA3 are added as quantities that are the sign of VTA2 positive and VTA3 negative, resulting in a positive amount, which indicates the leading of the PRG with respect to the input voltage. Similarly, if PRG lags behind the input voltage, the sum of VTA2 and VTA3 will be a negative amount, which indicates that it represents a lagging condition.

For small phase error values ε between PRG and the input voltage sinusoid, the standard sum of VTA2 and VTA3 provides a very good direct estimate of the phase error. With reference to FIG. 15, the equation describing the input voltage wavelength V _dp (t) with time called PRG is as follows:

(12)

(12)

Where V _m is the fixed magnitude of the voltage sinusoid, f is the frequency of the sinusoid and ε is the phase error between the sinusoid and the PRG. To repeat again, the frequency is known and it is assumed that all three of these values are constant. As noted above, positive ε indicates that the sinusoid is behind the PRG, or equally the PRG is ahead of the sinusoid. The fundamental period of the PRG is denoted T, and if it is assumed that the PRG and sinusoid have the same fundamental frequency, T is associated with f by:

(13)

(13)

In Fig. 15, the interval q2 is represented as a closed time interval [T / 4, T2]. The interval q3 is represented by the closed interval [T2, 3T / 4]. These intervals are defined so that the integral of the q2 phase sinusoid expressed in VTA2 is:

(14)

(14)

Using the relationship with the planar structure:

(15)

(15)

Equation (14) is simply as follows:

(16)

(16)

Similarly, VTA3 is provided as follows:

(17)

(17)

Adding VTA2 and VTA3 forms the following equation:

(18)

(18)

Subtract VTA3 from VTA2 as follows:

(19)

(19)

Now, the amount E is defined as follows:

(20)

20

Substituting and simplifying (16) and (17) for VTA2 and VTA3 form the following equation:

(21)

(21)

This is approximated as follows for small phase error (ε) values:

(22)

(22)

Thus, for small phase error values, the amount E calculated by the voltage-time domains provides a good estimate of the phase error (in radians) under given assumptions. This phase error estimate can be used in a closed loop feedback system to derive the PRG in synchronization with the line voltage.

As mentioned above, the EQ5400 AC resistance weld control is a sampled data system in which samples of external continuous time signals are taken at discrete fixed time intervals using an analog to digital converter. These samples are designed to be synchronized to the timing of the PRG, and in practice the PRG period is defined as the time required to obtain 128 said samples in the preferred embodiment. The continuous time signal x (t) is approximated to a data system sampled by a sequence of discrete sample points x (k) according to the following equation:

(23)

(23)

Where T _s is the default sample period of the system-DSP interrupt interval for EQ5400 AC resistance weld control. In the following, the value x (k) is the k th basic sample of entity x (t). For example, this application to the observed voltage waveform of (11) gives the following sequence:

(24)

(24)

As an example of such a sequence, let the parametric values of 24 be provided in the table shown in FIG. This corresponds to sampling at 480 VRMS, 60 Hz at 128 samples per line cycle. Corresponding samples are shown in the stem diagram in FIG. 17.

In the EQ5400 AC resistance weld control, the voltage is sampled at discrete intervals as described above, and a trapezoidal approximation for voltage-time domain integration is performed. If the number of samples obtained by the digital voltmeter function over the internal PRG period is N _s ., There are N / 4 samples obtained over four minutes. The evaluations of the voltage-time domains of the quadrants 2 and 3 labeled V _wc TA (q2) and V _WC TA (q3) are generated using the following equation:

(25)

(25)

And

(26)

(26)

Here, index "j" is the j th sample of the voltage waveform (DSP interrupt) in the PRG cycle as described above.

In resistance welding applications where large currents are induced for short periods of time, the presence of line impedance collapses the "shape" of the observed voltage, which is no longer sinusoidal. We then develop a current equation for an AC phase controller, such as a resistance welder, and investigate the effects of line impedance on the observed sinusoid.

The mathematical solution is developed in two parts. First, the current equation of a fixed drive point voltage source driving a load having both resistance and inductance components is investigated. Next, the resistance and inductive line impedance elements are introduced in series between the driving point voltage source and the point where the voltage is actually observed, and the driving point voltage and the actual voltage observed by the welding control are examined.

18 shows an ideal circuit model for AC phase control, such as a resistance welder driving inductive loads. The ideal voltage source on the label V _dp (t) provides the source voltage to the system. The switch labeled SW1 opens and closes on demand and represents thyristors that form the solid state switching elements of the phase control. The load includes a resistor R _load and an inductor L _load . The next current is label i (t) and the voltage applied to the _load is V _load (t).

As noted above, in this first scenario, V _dp (t) is a sinusoidal voltage source of the form:

(27)

(27)

Where ω is the sinusoidal radian frequency relative to frequency (Hz) as follows:

(28)

(28)

When a semiconductor switch such as SCR is used as the switching device, a simple model of this device is to close the switch at the commanded time τ from the zero crossing of the sine voltage source. When the switch closes and current begins to flow, it continues to flow until the current naturally dissipates itself, at which point the switch cuts off the voltage. Under these conditions, the current flow in the circuit is given as a function of time:

(29)

Where φ is referred to as the "lag angle" and relates to resistance and inductance as follows:

(30)

(30)

And T is the conduction time, ie the time that elapses from the firing time until the current naturally dissipates itself, and is simply expressed mathematically as follows:

(31)

(31)

The function u (t) is commonly known as the "unit step function" and is defined mathematically as follows:

(32)

(32)

The origins of equation 29 and its derivatives will be discussed later.

In general, equation 29 cannot be solved in a closed form for conduction time, but iterative methods can be used to derive approximations. Equation 29 can be normalized to frequency and thus time independent. The impedance Z _load , firing angle α and conduction angle, γ of phase control are defined as follows:

And

Let θ be the observation angle, that is, the angle after the zero crossing of the sinusoid. Then (29) becomes:

This is the "normalized" form of the phase control equation.

Next, consider a more complex circuit model of a lumped parameter system that forms the mathematical basis for the present invention. In this model, shown in FIG. 19, it is not assumed that the weld power source is "stiff" as in the previous discussion, but includes three lumped constant circuit elements, i.e. Series lumped constant line resistance, labeled as the original, "rigid" drive point voltage source, V _dp (t) and R _line ; And an L _line inserted between the drive point voltage source and the welding control.

This concentrated constant parameter model of the power source combines the resistance from all sources between the hypothesized stiff voltage source and the input stages of the welding control. This includes the winding resistance of the distribution transformer, the inductance of the transformer, the resistance and inductance of the power distribution system, such as wires, busway, switch contacts, and the like. This line impedance can be significant for the load impedance. In FIG. 19, the voltage observed by the welding control is labeled V _wc (t), and V _dp by the current flowing through R _line and L _line under conditions where the welding control fires under load. from (t).

Referring to Fig. 19, several things are clear: the welding current, the line impedance and load impedance factor for determining i (t); If there is no current flowing and therefore no voltage drop across the line impedance, the voltage V _wc (t) observed by the welding control is equal to the source voltage, V _dp (t). However, when current is flowing in the circuit, the voltage observed by the welding control is not the voltage of the voltage source, V _dp (t), because of the voltage drops across the line resistance and line inductance.

From the elementary circuit analysis, for the current we can write:

Where R _eq and L _eq , in this case, are equivalent series resistance and inductance, and are given as:

And

And φ, and T are computed per equation (but using the equivalents) describing the simple model of FIG. The voltage V _wc (t), observed by the welding control, is related to the ideal voltage source modeled as V _dp (t) as follows:

The voltage observed by the voltmeter of the welding control becomes quite complicated and it is difficult to visualize the effect. However, FIG. 21 shows simulation results showing the effect of line resistance and line inductance on the observed voltage on the parametric values of the circuit of FIG. 19, presented in the table shown in FIG. 20. The simulations and charts presented were generated using MATLAB, a commercially available software package suitable for this task.

Comparing the voltage waveform (top) of the driving point voltage source of FIG. 21 with the voltage waveform (center) to be observed by the voltmeter function of the welding control of FIG. 21, the observed voltage waveform is a significantly distorted version of the source voltage. Under load, the welding control cannot directly observe the drive point voltage source, V _dp (t), which is strictly a mathematical construct, and thus specific to apply connections to measure voltage. Because there is no point. Although a suitable point can be found in the power distribution system to monitor the actual source voltage, the monitor point will be located some distance from the welding control, and the welding control is localized. stand alone). The EQ5400 AC Resistance Weld Control monitors the voltage at the inputs.

The voltage distortion shown in FIG. 21 limits the performance of AC resistance weld control in two ways without the benefit of the present invention. The first limitation is that applying the phase estimation method discussed in detail above to the distorted waveform (center) of FIG. 21 produces an incorrect estimate of the phase relative to the drive point voltage source. In the above example, using the presented phase error estimation method, the same method is applied to the observed welding control voltage, V _wc (t) (center) of FIG. 21 during welding, so that the phase reference generator ) Is originally "locked" on line voltage source V _dp (t) (the term "lock" means zero phase error generated before welding), the phase error estimator is approximated. This results in a phase error of -7.7 degrees. If the PRG is allowed to respond to this estimation error during welding, the timing of the system will be inaccurate and the system will generate false ignition points for the thyristors to achieve the target welding current. If closed loop control is employed to change the ignition points to obtain a constant current, the response to the generated phase error will cause at least a disturbance in the welding current. Since resistive welds are generally short (in order of a total of 10 line cycles), such disturbance can affect the metallurgy of the weld.

The second limitation is that the RMS voltage measured by the welding control in FIG. 21 is lower than the drive point voltage design model V _dp (t). In this example given, the RMS value of the voltage source is 480 volts, while the RMS voltage of the waveform (center) of FIG. 21 is 453 volts. This is a waveform observed directly by the welding control. One feature of some prior art welding controls is the ability to automatically compensate for variations in observed voltages to keep the current constant. From the foregoing extension of the welding current equation of a system with line resistance and reactance, it is noted that the current delivered for a given ignition point of the thyristors depends on the equivalent of the drive point voltage, resistance and inductance (including load and line values). Obvious. Thus, using the observed line voltage (which is different from the drive point voltage when the current flows) as a basis for voltage compensation introduces constraints on welding control performance. Conversely, the fact that the estimated drive point voltage described in the present invention can be used as a basis for line voltage compensation results in a significant improvement in this respect.

The efficiency of the welding control based on the circuit model of FIG. 19 to generate the appropriate thyristor firing points (timings) depends on the accuracy with which the PRG can estimate the relative phase error between itself and the mathematical model of the driving point source voltage. As discussed, the very action of conducting current in resistance welding distorts the voltage waveform observed by welding control, and applying the above method directly to the observed voltage results in errors in the thyristors firing timing. Will effect.

However, assume that the parameters of line resistance and line reactance (inductance) can be estimated. If so, from the equation 40 and from the observation of the welding control voltage V _wc (t), the load current i (t), the derivative of the load current, di (t) / dt at the input of the welding control, an open circuit fault The estimate of the voltage source, V _dp ^* (t), can be made using:

를 추정하기 위해 상기 수학식들을 적용하고, 이후에 상기 추정된 전압을 PRG에서의 위상 에러를 계산할 때 사용하는 것은 PRG의 더 정확한 타이밍, 따라서 사이리스터들의 점화 포인트들을 제공해야 하며, 피드-포워드(feed-forward) 제어 방식에서 도 19의 모델의 사용을 더 용이하게 한다. 따라서, 본 발명의 일 특징은 전력 분배 시스템의 라인 레지스턴스 및 라인 리액턴스를 추정하는 수단이다.Source voltage

Applying the above equations to estimate, and then using the estimated voltage in calculating the phase error in the PRG should provide more accurate timing of the PRG, thus ignition points of the thyristors, and feed-forward -forward) to facilitate the use of the model of FIG. 19 in a control scheme. Thus, one feature of the present invention is a means for estimating line resistance and line reactance of a power distribution system.

To proceed with developing the equations, equation (40) can be solved so that V _dp (t) obtains the following equation:

The relation is independent of the values of the load impedance elements, R _load and L _load . As described above, close control similarly estimates the value of i (t) at discrete intervals and a digital voltage sampling function (analog to digital converter) that can estimate (measure) V _we (t) at discrete intervals. It includes a digital current sampling function. If the values of R _line and L _line can be estimated, equation (42) indicates that the instantaneous driving point voltage V _dp (t) can be estimated.

As mentioned above, the EQ5400 AC Resistance Weld Control operates as a sampled data system that samples voltage and current indication signals at discrete intervals defined as follows in the sequence of points {t _k }:

t _k = _k T _s

T _s is the basic sampling interval. Applying the above equation to equation (42) yields a sequence of points V _dp (k) with k th samples in the sequence given by:

Thereafter, whenever the index "k" occurs, it is understood that the corresponding sample time is t = kT, k = 0, 1, 2, ..., _s . In the above understanding, the nomenclature of equation (43) is simplified to yield the following equation:

Tightness control does not provide a derivative sequence di (k) / dt at each point but provides sampling functions that provide estimates of the voltage sequence V _we (k) and current i (k). However, the simplification for the derivative sequence can be performed by defining the first backward difference Δi (k) as follows:

Δi (k) = i (k) -i (k-1) equation (45)

The derivative is approximated using the following equation:

Substituting Eq. (46) into Eq. (44) gives the following equation:

Now, define X _leq as:

T _s is the known sample period of the system. By substituting the above formula, the following formula is provided:

Several methods of estimating the assumed constant values of R _line and X _leq are explored. In order to accomplish this, development will begin by the general approach and preferred method being developed. When examining equation (49) for a given sample k, there are three quantities that can be "known" to the system via measurements: 1) V _we (k) which can be measured using the digital voltmeter function. ), 2) i (k) which can be measured using the digital current meter function, 3) Δi (which can be calculated by the knowledge of i (k) and i (k-1) according to equation (45). k). There are three _unknown values in the formula, V _dp (k), R _line and X _leq . None of these values can be observed when current flows, and the sequence V _dp (k) is not always constant. There are several ways you can proceed to produce estimates of R _line and X _leq , but in each case some assumptions must be made regarding the properties of V _dp (k) that cannot be observed directly.

Some possible methods for estimating constant values of R _line and X _leq assume that the system obtains measurable quantities of observations at distinct sample times k0, k1, k2 (not necessarily in monotonically increasing order), It is assumed that there is a known constant equation between V _dp (k1), V _dp (k2), and V _dp (k3) that can be expressed as follows:

M ₁ and M ₂ are known constants. In this setup, the following matrix equations can be recorded for three samples:

In this case,

V = A * U equation (52),

V is a matrix of measured voltage points:

U is a matrix of unobservable quantities (two of which, R _line and X _leq are the targets of the estimate):

A is a matrix of observable and known quantities related to V and U according to (51):

If matrix A is not singular, then there is a mathematical inversion of A, and we can solve (51) to obtain the following equation:

Therefore, estimates of R _line and X _leq can be obtained. Equation (56) can yield the value of V _dp (k 0), but most important values of the present invention are line resistance and reactance.

One important variant in this method is that cyclical in k where V _dp (k) has an integer period N _s , and thus:

For the values of p in the set of natural numbers p = {1,2, ...}. This is interesting in the context of the present invention because 1) the drive point voltage is periodic and 2) the PRG period as described above contains N _s samples (DSP interrupts). Thus, if the PRG is already synchronized to the drive point voltage, the periodic relation exists and is known. If k0, k1, k2 are related as in the following equation:

When both p1 and p2 are natural numbers, M ₁ = 1 and M ₂ = 1 in equation (56) are calculated from equation (57). In general, the method means that samples are taken at the same relative "position" in different PRG cycles. Of course, setting M ₁ and M ₂ = 1 in equation (56) does not guarantee that the matrix is not singular and can be transformed, so the method cannot be implemented in the general case. In particular, if the system using the method operates in a "stable state", and thus the current and the current difference are obtained at the same respective sample point, the matrix can be clearly singular, and the method is R _line and X _No usable estimates of _leq can be generated.

To search for other more practical means for estimating R _line and X _leq , substitute equation (49) into the following equation:

Now, we can record the determinant for three data samples:

During one of the samples (referred to as k0), assuming that both current and current difference are zero, the above calculation can be significantly simplified. If it becomes as above, from equation (60), the equation can be expressed as:

(61)

(61)

If (57) is applied, the equation becomes

(62)

(62)

This may explain the linear resistance and reactance.

(63)

(63)

It also assumes that the current and current difference matrices are non-singular, but only 2 × 2 matrices.

The assumption that line cycles can be found where no current is flowing and therefore not flowing (and therefore current and current difference are both zero at point k1) is the application of welding current while mechanical welding "tips" allow the metals to be bonded to each other. This makes sense in conventional resistance welding applications as long as no current flows. Moreover, it is reasonably reasonable that once the current begins to flow, the current flowing in the first line cycle of the weld will be different from the continuous line cycle of the current, since this forcing on the metal is usually not complete, This is because the steady state will not reach until the metal actually begins to melt.

For continued deployment, if it is assumed that samples can be taken in a PRG cycle known to not flow and other PRG cycles known to flow, there is no need to force all samples by equation (57), If samples are taken in pairs (ka, kb),

(64)

(64)

및

이 존재한다고 가정하면 다음과 같이 된다. In particular, two pairs of data points

And

Assuming this exists,

(65), 및

65, and

(66)

(66)

및

에 대해 적용되는 것을 가정한다. 그러면 (67)에서 역행렬이 존재한다고 다시 가정하고 다음과 같이 식을 나타낼 수 있다. And k ₀₁ and k ₀₂ are samples taken from the PRG cycles in which no current is flowing, and k ₁ and k ₂ are taken from the PRG cycles in which current is flowing, in particular (57) for each pair.

And

Assume that it applies to. Then at (67) we can assume again that an inverse exists, and we can write

(67)

(67)

및

의 추정이 두 라인 사이클 내에서 개별 DSP 샘플들로부터 행해지게(그러나 요구하지는 않음) 하는데, 하나는 전류가 흐르고 있지 않으며, 하나는 전류가 흐른다. 이를 허용하는 것은 (67)에서 역행렬이 존재할 가능성을 매우 향상시킨다. These methods

And

An estimate of is made (but not required) from the individual DSP samples within two line cycles, one without current and one with current. Allowing this greatly improves the likelihood that an inverse exists in (67).

In a factory environment, the magnitude of the actual drive point voltage does not change over time, and this change is one factor that can affect the accuracy of the estimation of linear resistance and linear reactance. If line cycles farther apart in time are selected in the discussion above, the drive point voltage magnitude is more likely to be significantly different. Thus, in the disclosed embodiment of the present invention, adjacent line cycles are selected such that the line cycle through which current flows and is measured is adjacent to the sequence of line cycles where no current flows for a substantial number of line cycles. It will be understood that this particular embodiment does not limit the usefulness of the present invention, and in particular, that the line resistance and line reactance are calculated using a sequence in which current flows in a certain line cycle and no current flows in successive line cycles. You can think of an example. Embodiments of the present invention are preferred because if the current does not flow for a significant number of line cycles before conducting the current, the PRG will be exactly synchronized with the drive point voltage when current begins to flow. Since there is a natural delay in response to one line cycle in the disclosed PRG implementation, current samples taken in a first line cycle through which current flows after a long period of non-current flow may affect the PRG until after measurements have been taken. none. This is an ideal condition for obtaining samples.

이 소스 전압

과 같으며, Subsequently, assume the following: (1) The weld control voltage observed because the system did not weld for a period of time.

This source voltage

Is the same as

(68)In other words,

(68)

의 변조 항은 일정하며, 다음과 같이 표현될 수 있다. (2) the driving point voltage for a period of two predetermined line cycles

The modulation term of is constant and can be expressed as follows.

(69)

(69)

Consider two sample points taken exactly one period apart under these conditions; One flows a welding current, the other falls exactly one PRG period and no current flows. Recall again that there are N _s samples (DSP interrupts) per PRG period. Under the foregoing assumption, it can be expressed as follows.

(70)

(70)

Applying this to equation (49), it can be expressed as follows for a particular case where no current flows for one line cycle and current flows for successive line cycles.

(71)

(71)

If two sets of samples (samples k1 and k2 (k1 and k2 are not equal)) can be selected from adjacent line cycles, where the current and current difference values are not zero and are distinctly different from each other, the matrix form Can be represented,

(72)

(72)

This can be calculated in the matrix form, assuming that the inverse matrix is a static matrix, to obtain a matrix form as follows.

(73)

(73)

Equation (73) provides one means by which line impedance parameters can be estimated.

The potential limitation of using individual points to make line impedance parameter estimates is more severe in factory environments where the observed signals are generally “noise”, especially with many on / off control and power circuits and other switching devices. The calculated values of line resistance and line reactance are sensitive to the actual values of the voltage and current used in equation (73).

(74) A more robust means of estimating parameters is now provided. As mentioned above, the system generates a VTA for each quadrant using the trapezoidal integration used to provide quadrant estimates. This is understood in the study of the probability process that when signals are corrupted by uncorrelated phenomena, zero mean noise, taking the average over the sum of many samples reduces the deviation of the estimate. The voltage-time domain, current-time domain and current-differential domain can be used to complete this estimation. For the typical sequence x (k), the generic "X-time domain" and PRG line cycle n, where X (k), x (k), (q = q1, q2, q3, q4) of x (k) for quadrant q Is limited to,

(74)

은, Where j is the exponent of the sequence x (k) but is indexed from the beginning of the PRG cycle, ie j = 0 corresponds to the transition of q4 to q1 of the PRG function 10. With this definition, the estimated voltage-time domain of the observed welding voltage for quadrant q,

silver,

이며,

Is,

,

및

을 다음과 같이 정의한다. This is the exact sum used to calculate the voltage-time domain of the quadrant used in the PRG function 10. Now, in an accurate analog way,

,

And

Define as

을 관측된 용접 전압 샘플

, 전류 샘플

및 제1 전류차

와 관련시키는 선형식 임을 관찰한다. 그것은 선형 관계이기 때문에, 상기 관계는 또한 양(quantity)들 XTA(q)에 동일하게 적용된다:Next, equation (49) shows a driving point voltage sample for each sample n.

Observed weld voltage sample

Current samples

And first current difference

Observe that this is a linear equation. Since it is a linear relationship, the relationship also applies equally to the quantities XTA (q):

(79)

(79)

Here, R _line and X _leq are assumed to be constant parameters.

By selecting q2 and q3 as quadrants used to estimate the parameters, one is obtained (in matrix form):

(80)

(80)

The terms nomenclature R ^* _line and X ^* _leq represent the estimates of the resistance and inductance of the power distribution system, respectively, and the indices (q2, n) and (q3, n) are the upper limits of the current line cycle in which current is flowing. And upper bound estimates from 3, the indices (q2, n-1) and (q3, n-1) specify upper bounds 2 and 3 from the previous line cycle in which no current is flowing. Again, one can describe the estimated parameters to obtain:

(81)

(81)

This important result is the method used in line impedance parameter estimation in the EQ5400 AC resistance weld control to calculate R ^* _line (m) and X ^* _leq (m) values in FIG. 8 above.

The closed form solution for the weld current delivered by the AC storage weld control is now developed using Laplace transform techniques. This analysis assumes a stiff drive point voltage source and ideal thyristor switches. The results are provided as a function of observation angle as well as time. Conditions are also provided that determine the conduction time or angle of the thyristor as a function of firing point and load impedance.

22 is a simplified lumped parametric circuit model for a storage welding controller and associated power distribution system and welding load, which model will be used to obtain the mathematical calculations of the welding controller. The lump parameter model includes a welding power source 11, a welding controller 20, and a welding load impedance 30. The welding power source 11 is modeled as two circuit elements, the voltage source V _s (t) 12 and the lumped line impedance Z _line connected in series, the voltage source V _s (t) 12 having a series impedance. The ideal voltage source is assumed to have no impedance Z _line , and the impedance Z _line creates a voltage drop between the ideal voltage source and welding control proportional to the welding load current. The welding timer 20 can observe the load current I _load through the current transducer 24 and the voltage V _wc (t) applied to its input terminals. Using solid state thyristor switches 22, the welding timer generates a welding voltage V _load (t) at its output terminals with the corresponding welding current I _load (t). Welding load impedance 44 includes a weld transducer 20, a workpiece, tooling 22, fixtures and other impedance sources. To simplify the mathematical calculations, the impedance of all these elements is lumped with Z _load , the amount of one impedance reflected at the output terminals of the weld control. If the welding control applies the voltage V _load (t) to the load impedance, the resulting current is I _load (t).

Next, the line impedance Z _line is assumed to be zero, and the voltage source V _s (t) is considered as an ideal source of the form:

V _s (t) = Vsin (2πft) (82)

Where V is the magnitude of the line voltage and f is the line frequency (Hz) of the line voltage source. This sinusoid as a function of time is shown in FIG. 23 (top). Note that zero crossings of this waveform occur at the following points:

(83)

(83)

To eliminate frequency dependency, timing in resistance welding applications is typically expressed in degrees rather than time. In this analysis, the viewing angle (corresponding to time) is designated by θ. FIG. 23 (bottom) shows the voltage waveform as a function of the viewing angle and has zero degrees referred to as the negative to positive zero crossing of the sine wave. In this case, the sinusoidal zero crossings are located at the following angles:

θ = 180 * n, n = 0,1, ... (84)

Thyristor switches are assumed to be ideal switches that do not have a voltage drop. The load impedance reflected on the primary side of the weld transducer can be reasonably modeled as lump load resistance R _load and series load inductance L _load as shown in FIG. 24.

The effect of igniting the solid state thyristor welding contactor closes the switch of FIG. 24 at time t = τ (or angle α) with respect to the zero crossing of the voltage source shown in FIG. 23. 25 shows the voltage waveform resulting from thyristor ignition. When the switch is pulled and current begins to flow to the load, the switch is either at time t = τ + t _cond as shown in FIG. 25 (top) or at an angle θ = α + γ as shown in FIG. 25 (bottom). It remains closed until the current goes back to zero. The actual value of t _cond or γ depends on the ignition point and load circuit parameters and will be obtained here. Mathematically, the voltage applied to the load takes the form:

(85)

(85)

Where u (t) is the unit step function.

The purpose of this analysis is given in (82) above and as shown in FIG. 23 a closed form for the welding current resulting from ignition of the thyristor switch at time τ in relation to the zero crossing of the source voltage v _s (t). Is to deploy the solution. In addition, the shape of the current waveform will be provided as a function of the observation angle θ as described in FIG. 23 (bottom). Another important amount is the resulting conduction time t _cond or the corresponding conduction angle γ, which is defined as the angle at which the thyristor conducts or alternatively the angle at which current flows as a result of the thyristor ignition.

The following assumptions are made to simplify the analysis of welding current:

1. The voltage source v _s (t) is ideal and is therefore assumed to be "stiff". Thus, there is no line impedance.

2. The frequency of the voltage source remains constant.

3. The thyristor switch is assumed to be an ideal switch with no voltage drop. When the thyristor is triggered, the thyristor is conducted until the current flowing through the thyristor is exactly zero.

4. The load impedance, including the load resistance and load inductance reflected on the first side, is assumed to be constant during welding. This assumption represents a linear, time invariant system.

Under these assumptions, the closed form solution for the load current i _load (t) resulting from the thyristor ignition at time τ in relation to the zero crossing of the sinusoidal input voltage is:

(86)

(86)

Where V is the magnitude of the sinusoidal input voltage; R is the resistance of the weld transducer, gun and tooling reflected on the first side of the weld transducer; L is the inductance of the weld transducer, gun and tooling reflected on the first side of the weld transducer; ω is the radian frequency of the line voltage source; φ is the lag angle of the load impedance defined by equation (87);

(87)

(87)

τ is the time that the thyristor is ignited in relation to the zero crossing of the line voltage as shown in FIG.

The load current i (θ) expressed in relation to the observation angle θ is:

(88)

(88)

 Where θ is the observed angle measured from the negative to positive zero crossing of the sinusoidal voltage source; φ is the lag angle of the load impedance as given by equation (87) above; α is the ignition angle associated with τ by equation (89);

α = ωτ (89)

| Z _load | is the magnitude of the load impedance given by equation (90):

(90)

(90)

) 및 유사한 전도각(

)에 대한 값들은 다음과 같다:Fall time

) And similar conduction angles (

) Are the following values:

)은 전압 소스(

)의 것과 동일하다. 라인 임피던스가 존재하면, 용접 제어에 의해 관측되는 라인 전압(

)은 라인 임피던스를 통해 흐르는 전류에 의한

의 것으로부터 감소될 것이다. It is assumed that a rigid weld source provides a simple representation of the voltage waveform provided to the load. Referring to Fig. 22, when there is no line impedance, the voltage observed by the welding control (

) Is the voltage source (

Same as). If line impedance is present, the line voltage observed by welding control (

) Is caused by the current flowing through the line impedance

Will be reduced from

To analyze the effect of line impedance on the welding current, one of ordinary skill in the art can lump the line impedance and the load impedance into one entity. Assuming line impedance is also essentially inductive (ignoring the capacitance of a distributed system), the equivalent resistance and inductance can be defined as:

If these values are replaced by the various equations described above, the resulting current is an accurate estimate of what actually happens in the weld control.

)가 시스템이 선형이고 시 불변(time invariant)이라고 가정하기 위해서 요구된다. 이러한 가정이 없다면, 라플라스 변환 기술이 사용될 수 없다. 다행스럽게도, 이러한 가정은 애플리케이션에서 매우 높은 정도로 실현된다. Fixed radian line frequency (

Is required to assume that the system is linear and time invariant. Without this assumption, the Laplace transform technique cannot be used. Fortunately, this assumption is realized to a very high degree in the application.

An ideal thyristor is assumed for simplicity. Thyristor models with a fixed voltage drop, or any linear model for these thyristors, could be used. If a model is used that incorporates a fixed voltage drop, it is modeled as a DC voltage source. In the linear system model, the resulting welding current can be expressed as a superposition of the DC voltage applied to the system at firing time and the response to the sine wave as expressed in the equations described above.

Constant load impedance is required to allow modeling the analysis of lumped parameters into a linear, time invariant system. Inductance is mainly determined by the work piece and the geometry of the tool, which can change as the geometry of the tooling changes. One such example is that shunts and cables have a tendency to "jump" at the start of welding. The resistance is generally very constant, typically at 1/2 cycle. During an expulsion period, when the excessive amount of heat is applied, the molten metal is released from the welding tips and the cast metal is observed as if a shower of sparks is emitted from the welding tips. Can be changed quickly. In this case, the shape of the welding current will not follow the above equations well.

The basic form of welding current can be derived as discussed below. The loop equation for the circuit of Figure 24 is as follows:

Taking the Laplace transform for the equation (0-67):

or

In Figure 24 it can be arranged as follows:

Here I can summarize I (S) as follows:

To obtain the Laplace transform for the load current, multiplying equation (99) by equation (97):

This can be summarized as follows:

Where F (S) is:

Now note the following properties of the Laplace transform:

는 시간 지연을 의미하며, 즉 One.

Means a time delay, i.e.

이다.

to be.

2. The Laplace transform of the derivative is:

Looking at equation 101 in terms of (103) and (104), the inverse Laplace transform of F (s) is f (t) and the load current i (t) is:

Thus, if f (t) can be found from 102, equation 105 shows how to induce a welding current. F (s) can be expanded to a fractional fraction representation as follows:

Cross-multiplication and gathering in equation 106 provide the following equation:

Equation 107 is a polynomial for 's'. In order to satisfy (107) for all values of s, the coefficients of each term of the polynomial must all be zero. This gives the following relationship between a, b, and c:

And

Solve for 'a' at (106):

From 108, 'b' is as follows:

Solve (109) for 'c' as follows:

Substitute and simplify (111) as follows:

Substituting again (111), (112), and (114) for (106) gives:

Taking the inverse Laplace transform for (115) gives:

The derivative of (116) is given by:

Substitution of (116) and (117) with (105) is as follows:

Rearrange the terms as follows:

Two triangular identity sources that can be used to simplify (119) are:

Applying the above identity to (119) is as follows:

The basic concept of AC circuit analysis is the concept of the delay angle of the R-L circuit, denoted by φ and defined as:

From this the following relationship can be described:

To facilitate the use of these relationships, first multiply the amount of L / L = 1 through 122 and rearrange the terms as follows:

Applying (124) and (125) now gives:

Applying (120) to (127) gives:

Equation (128) is the welding current as a function of time for the zero crossing of the line voltage, the equivalent load resistance R and the load inductance L reflected in the primary coil of the welding transformer and the parameter values of the firing time τ with respect to the radian line frequency ω. Typical form of the equation of.

The point at which the thyristor fires is usually expressed in terms of the angle of fire α rather than the time of fire. The fire angle α is related to the fire time τ and the radian line frequency ω by the following equation:

Similarly, the observation angle θ can be defined by the following equation.

Once these two quantities are defined, we can rewrite the exponential function at (128) as follows:

Applying 123, 130 and 129 to 131 is as follows:

In addition, the magnitude of the AC load impedance of the R-L circuit is obtained as follows:

Substituting (133) for (133), (132), (129), and (130) as equation of the welding current for the firing angle α, the circuit delay angle φ and the observation angle θ is as follows:

FIG. 26 is a plot of the current waveform as a result of applying the parameter values shown in FIG. 27 to equation (134).

When the thyristors ignite and the current begins to conduct, the thyristors continue to conduct the current at zero crossing until the current naturally extinguishes itself. Using equation (128), the time that the thyristor is turned off satisfies:

Where i (t) is given by (128) above. Equation 135 is a mathematically rigorous statement that the conduction time is the interval between the ignition of the thyristor (at t = τ) and the time when the welding current first passes zero again. There is no closed form solution for t _cond , but equation (128) can be solved with a relatively high degree of accuracy. Likewise, the conduction angle γ is an angle satisfying the following equation:

Assuming a linear lump parametric model of the welding circuit, a closed form solution to the welding current can be found. While the analysis presented herein makes quite a few assumptions, some of these may be considered suspicious in real welding applications, and the results presented are generally accepted as "solutions" to welding current and have been repeatedly referenced in the paper. . By integrating the model for the source impedance provided by the welding voltage source, more accurate modeling of the system can be easily achieved, and assuming a linear model for each, the effect of the thyristor can also be easily investigated.

While specific embodiments have been shown and described, modifications may be made without departing substantially from the spirit of the invention, and the scope of protection is limited only by the appended claims.

Claims (41)

A phase reference generator for tracking the driving point voltage of a power distribution system for use in resistance welding control, Includes a digital signal processor, The digital signal processor, A digital volt-time domain generator for generating a volt-time domain of the observed voltage; A digital current-time domain and current-difference-time domain generator for generating a current-time domain of the observed current and a current-differential-time domain of the observed current; A line impedance estimator; And A drive point voltage domain estimator configured to receive values from the digital volt-time domain generator, Wherein the digital current-time domain and current-difference-time domain generator and the line impedance estimator produce estimates of the driving point voltage, Phase Reference Generator. The method of claim 1, And an analog-to-digital converter for converting each of the observed voltages and the observed currents from an analog signal to a digital signal. The method of claim 2, And an interval timer for triggering an analog-to-digital conversion of the observed voltage and observed current. The method of claim 3, wherein And a phase error estimator configured to estimate a phase difference between the timing cycle generated by the phase reference generator and the estimated driving point voltage. The method of claim 4, wherein The phase error estimator is implemented in the firmware of the digital signal processor once during every timing cycle produced by the phase reference generator. The method of claim 4, wherein And a compensator configured to adjust the frequency of the timing cycle to move the timing cycle toward a synchronous phase with the estimated driving point voltage. The method of claim 6, The compensator increases the frequency of the timing cycle when the timing cycle is lags to the estimated drive point voltage, or decreases the frequency of the timing cycle when the timing cycle leads to the estimated drive point voltage. Phase reference generator, characterized in that. The method of claim 4, wherein And further comprising a quadrant generator configured to provide an indication of the current quadrant of the timing cycle. The method of claim 1, And an output for providing a signal to ignite the resistance welder. As a welding controller for a resistance welding system, A phase reference generator configured to provide an estimated drive point voltage of a supply voltage and generate a signal to ignite a thyristor of the welding system during a welding operation; A voltmeter coupled to the input line and the phase reference generator for providing sampling values of an input line voltage; And Ammeter coupled to the input line and the phase reference generator for providing sampling values of line current Welding control device comprising a. The method of claim 10, The phase reference generator, And a digital signal processor configured to include a digital volt-time domain generator, a digital current-time domain and current-difference-time domain generator, an impedance estimator, and a driving point volt-domain estimator. The method of claim 11, And the digital volt-time domain generator generates an estimate of the input line voltage based on sampling values of the input line voltage. The method of claim 12, And said digital current-time domain and current-difference-time domain generators generate a difference value of said line current and an estimate of said line current from sampling values of said line current. The method of claim 13, The digital signal processor further comprising a line impedance estimator configured to generate line resistance and line reactance based on the estimate of the input line voltage and the estimate of the line current and the difference between the line currents. Control unit. The method of claim 14, The digital signal processor is configured to provide an estimate of the driving point volt-time region based on the estimate of the input line voltage, the estimate of the line current, and the difference between the line current, the line resistance and the line reactance. And a drive point bolt-time domain estimator. The method of claim 15, And the digital signal processor further comprises a quadrant generator for providing a phase reference generator timing cycle with frequency. The method of claim 16, And the digital signal processor further comprises a phase error estimator for estimating a phase error between the driving point voltage and the timing cycle. The method of claim 17, And the digital signal processor further comprises a compensator for adjusting the frequency of the timing cycle such that the timing cycle is synchronized with the driving point voltage. Digital phase reference generator for use in welding controls, An interval timer configured to trigger an analog-to-digital conversion of the sampling input line voltage and the sampling input line current based on regeneration; And A digital signal processor configured to execute an interrupt routine initiated by each completion of the analog to digital conversion of sampling input line voltage and sampling input line current And a predetermined number of the interrupt routines define timing cycles, the digital signal processor further comprising a volt-time domain estimate of the input line voltage, a current-time domain estimate of the input line current, Further configured to generate a current-difference-time domain estimate, and a line impedance estimate, Digital Phase Reference Generator. The method of claim 19, And the digital signal processor is further configured to provide a drive point volt-area estimate of the input line voltage. As a method of estimating the driving point voltage of a resistance welding system, Periodically sampling the supply voltage and supply current of the system to obtain sets of sampling voltage value and sampling current value; Obtaining a first set of sampling voltage values and sampling current values; Obtaining a second set of sampling voltage values and sampling current values; Obtaining a third set of sampling voltage values and sampling current values; Calculating a current difference value for each of the first set, the second set, and the third set; And The first set of sampling voltage values, the sampling current values and the calculated current difference values, the second set of sampling voltage values, the sampling current values and the calculated current difference values, and the third set of sampling voltage values, the sampling currents. Generating an estimated line resistance and an estimated line reactance of the system based on the value and the calculated current difference value Driving point voltage estimation method comprising a. The method of claim 21, Acquiring the first set of sampling voltage values and sampling current values comprises: Determining whether the current is flowing or not flowing; And Sampling the voltage when the current is not flowing. The method of claim 21, Creating a volt time region of the sampling voltage; Creating a current time domain of the sampling current; Generating a current difference time domain of the sampling current; And Generating an estimated driving point voltage time region using the volt time region of the sampling voltage, the current time region of the sampling current, the current difference time region of the sampling current, an estimated line resistance, and an estimated line reactance Drive point voltage estimation method comprising a. The method of claim 23, And driving the ignition of the thyristor of the resistance welding device using the estimated drive point voltage time domain. The method of claim 23, Generating a volt time region of the sampling voltage, generating a current time region of the sampling current, and generating a current difference time region of the sampling current are performed on a quadrant based on a quadrant; Point voltage estimation method. The method of claim 25, And periodically sampling the supply voltage and the supply current of the system comprises sampling the supply voltage and current for a set number of times for each quadrant. The method of claim 23, And calculating a phase error between the supply voltage and an internal phase reference using the estimated drive point voltage time domain. The method of claim 27, Generating the estimated driving point voltage time region using the volt time region of the sampling voltage, the current time region of the sampling current, the current difference time region of the sampling current, an estimated line resistance and an estimated line reactance. And using the calculated phase error. A drive point voltage estimation system of a resistance welding control device, Circuitry for periodically sampling a supply voltage and a supply current of the system to obtain a plurality of sets of sampling voltage values and sampling current values; Circuitry for generating a volt time region of said sampling voltage; Circuitry for generating a current time domain of the sampling current; Circuitry for generating a current difference time domain of the sampling current; Circuitry for determining whether current flows or not; Circuitry for obtaining a first set of sampling voltage values and sampling current values when the current is not flowing; Circuitry for obtaining a second set of sampling voltage values and sampling current values when the current flows; And Circuitry for generating an estimated line resistance and an estimated line reactance of the system based on the first set of sampling voltage values and sampling current values, and the second set of sampling voltage values and sampling current values. Driving point voltage estimation system comprising a. The method of claim 29, A circuit for generating an estimated driving point voltage time region using the volt time region of the sampling voltage, the current time region of the sampling current, the current difference time region of the sampling current, the estimated line resistance, and the estimated line reactance The driving point voltage estimation system further comprises. The method of claim 30, And a circuit for driving the ignition of the thyristor of the resistance welding device using the estimated driving point voltage time domain. The method of claim 30, And the system comprises a digital signal processor. The method of claim 29, A circuit for generating a volt time region of the sampling voltage, generating a current time region of the sampling current, and generating a current time difference region of the sampling current, generates a volt time region of the sampling voltage, the current of the sampling current. And circuitry for performing time domain generation, and the current difference time domain generation of the sampling current on a quadrant basis on a quadrant basis. The method of claim 32, And a circuit for periodically sampling the supply voltage and the supply current of the system comprises a circuit for sampling the supply voltage and the supply current for a set number of times for each quadrant. A drive point voltage estimation method for timing of ignition elements of a resistance welding device, Measuring a supply voltage and a supply current of the power distribution system at a plurality of predetermined intervals; Estimating line resistance and line reactance based on the measured values of the supply voltage and the supply current; And Estimating the driving point voltage based on the measured values of the supply voltage and the supply current and the estimated line resistance and line reactance. Driving point voltage estimation method comprising a. 36. The method of claim 35 wherein Calculating a voltage time domain of the supply voltage from the measurements of the supply voltage; Calculating a current time domain of the supply current from the measurements of the supply current; And Calculating a current difference time domain of the supply current from the measured values of the supply current, wherein the voltage time domain, the current time domain, and the current difference time domain are used to estimate the driving point voltage. A drive point voltage estimation method, characterized in that it is used. 36. The method of claim 35 wherein Estimating the line resistance and the line reactance, Measuring a first set of sampling voltage values and sampling current values when no current flows; Measuring a second set of sampling voltage values and sampling current values when current flows; And Generating an estimated line resistance and an estimated line reactance of the system based on the first set of sampling voltage values and sampling current values, and the second set of sampling voltage values and sampling current values. A drive point voltage estimation method. The method of claim 37, wherein And determining whether the current is flowing or not flowing during each of the plurality of predetermined intervals. The method of claim 38, And providing an ignition signal to a thyristor of a resistance welding apparatus based on the estimated driving point voltage. 36. The method of claim 35 wherein Estimating a phase error between the supply voltage and the estimated driving point voltage. The method of claim 40, And using said estimated phase error as feedback for further calculations of said estimated drive point voltage.

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