MX2008004949A - Improved phase reference generator with driving point voltage estimator for resistance welding - Google Patents

Abstract

An improved phase reference generator for use in resistance welding, and a method and system for estimating a driving point voltage of a resistance weld system. The method includes the steps of creating a volt-time area of the observed voltage, a current-time area of the observed current, a current-difference-time area of the observed current, an estimated line resistance, and an estimated line reactance of the system, and using them for creating a driving point voltage area or waveform. The estimated driving point voltage time area is used to drive the firing of a thyristor. The system includes circuitry for implementing the method for a resistance weld control.

Description

ENHANCED PHASE REFERENCE GENERATOR WITH EXCITATION VOLTAGE ESTIMATOR FOR RESISTANCE WELDING FIELD OF THE INVENTION The invention is generally concerned with a system and method for providing an improved thyristor that synchronizes in AC phase controllers and more particularly with a system and method for providing improved synchronization for resistance welding operations.

BACKGROUND OF THE INVENTION A phenomenon that can limit the performance of rectifier based phase controllers controlled by tirisitor or silicon (SCR) in general and resistance welding controllers in particular, is the distortion of the observed voltage waveform caused by the presence of line impedance when the current flows. In controlled resistance welders, precise control of the current is required in a few line cycles in order to generate the energy profile required to establish a strong, safe weld. To accomplish this, it is required that the trigger pulses that activate the SCRs be synchronized in a precise manner in relation to the AC power source applied thereto. Therefore, a modern resistance welding control must maintain an exact internal time base with respect to the power source. This Internal time base is referred to herein as a phase reference generator (PRG). Traditionally, weld controls maintain an internal time base in which phased locked loop systems employ a phase discriminator based on the zero crossings of an observed waveform to generate synchronization information on which a base of time can be generated. However, this method is not suitable for generating a time base for resistance welding applications because the current flow to the weld causes distortion at the zero crossings of the voltage waveform as observed by the welding control in its terminals. Several attempts have been made to provide improved welding conditions. U.S. Patent 5,856,920 discloses a method for estimating the phase error between two independent time bases. In particular, this patent discloses a method for estimating the phase error between an internally maintained time base (phase reference generator) and an observed sinusoidal voltage. The method for estimating the phase error between the two independent time bases comprises dividing the time base of the internal phase reference generator into "quadrants" and integrating the voltage-time area of the observed absolute value of the sinusoidal voltage in the quadrants . In one implementation, the phase estimator calculate the ratio of the difference between the sum of the voltage-time area of the first two quadrants and the sum of the last two quadrants, divided by the sum total of all the quadrants. In another implementation, the volt-time area of two adjacent quadrants is used to estimate the phase error. U.S. Patent 5,869,800 discloses the use of a phase-compensated time base for a weld control to improve the firing timing of the thyristors in a solid state phase-controlled resistor welder control. US Patent 5,963,022 discloses a method and apparatus for synchronizing an internal time base with an observed line voltage based on observing the voltage, estimating the phase distortion generated by the coupling of the AC line voltage source to the load as a result of the load that is energized from the phase angle trip control in the presence of line impedance and adjust the internal phase reference generator in response to the estimated phase distortion. This patent also reveals observing the line voltage waveform under a condition in which the system is not conducting current, paralyzing the frequency of the phase reference generator and the phase for one or more line cycles in which the system is driving current to observe the phase error resulting from estimating the phase under current flow conditions without compensating for the observed phase error, then biasing the phase error in subsequent phase error samples by the observed amount until the polarized phase error is compensated. The method described in this patent makes a very notable improvement in the performance of a resistance welding control, especially when the control intent is to generate a sequence of current pulses of the same current. However, in certain circumstances, particularly those in which the current ramps from an initial value to a final value in a number of performance line cycles, while they are better than in a system without such compensation, it is not. as accurate as it could be. U.S. Patent 6,013,892 discloses a phase-controlled welding system that calculates a firing sequence based on estimated models of line impedance, open-circuit line voltage and an estimated relationship between charge current and conduction angle and mathematical relationship between the firing angle, conduction angle and energy of the charging circuit. The system also uses measured values received in real time to modify the nominal firing angle. This system is not as accurate as it could be. The present invention aims to solve the problems discussed above and other problems and provide advantages and aspects not provided by prior art systems of this type. A full discussion of the elements and advantages of the present invention is deferred to the following detailed description, which proceeds with reference to the appended figures.

BRIEF DESCRIPTION OF THE INVENTION The present invention is a method and system for improved synchronization in AC phase controllers, such as resistance welding controllers. Specifically, the improved system and method can be used with an AC EQ5400 resistance welding control. This welding control is used in resistance welding applications, which include, but are not limited to, automotive body assembly. The present invention substantially improves the performance of the resistance welding control capability to track the excitation voltage (the open circuit voltage that would be observed if no current was flowing) by estimating in real time the voltage waveform of excitement under all conditions. There is no longer a need to "paralyze" the phase and frequency of the phase reference generator at the start of a weld. The present system does this by assuming a simple circuit model for the power source and system distribution that provides power to the weld control comprising an ideal variant timing excitation voltage source, a series line resistor and a series line reactance. Using the estimated parametric values of line resistance and line reactance, an estimated impulse point volt-time area is calculated and conventionally used as the basis for generating a phase reference generator that automatically tracks the source of energy under all conditions. According to one embodiment of the invention, the system estimates the magnitude and phase of the excitation voltage in an AC phase controlled resistance welding application in relation to an internal phase reference generator. The system provides improved tracking of the excitation voltage phase as long as it is welded. This results in a more accurate synchronization of thyristor trip points and consequently better current accuracy during a resistance welding operation. The system also provides estimated impedance values of improved run-to-run load, resulting in more accurate accelerator feed control. The system also provides improved line voltage compensation as long as: it is soldered. According to another embodiment of the invention, provides a method and system for estimating an excitation voltage of a resistance welding system. The method comprises the steps of periodically sampling a supplied voltage and a current supplied from a system to obtain a plurality of sampled voltage sets and a sampled current value. The sampled voltage and current are used to create a volt-time area of the sampled voltage, a current time area of the sampled current and the current difference time area of the sampled current. The method further includes determining whether the current is flowing or not flowing and taking a first stage of a sampled voltage value and a sampled current value when the current is not flowing and taking a second set of sampled voltage value and a value of current sampled when the current is flowing. From these two sets of values, the method includes creating an estimated line resistance and an estimated line reactance of the system. The method further comprises the step of using the sampled voltage volt-time area, the current time area of the sampled current, the current difference time area of the sampled current, the estimated line resistance and the reactance of estimated line to create an estimated excitation voltage time area. The estimated excitation voltage time area is used to boost the firing of a thyristor of a resistance welding device. The steps of creating a sampled voltage volt-time area, creating a current time area of the sampled current and creating a current difference time area of the sampled current can be performed on a quadrant quadrant basis. In this instance, the step of periodically sampling a supplied voltage and current supplied from a system comprises taking samples of voltage and current supplied a set of number of times for each quadrant. The method may also include several provisions to ensure that the estimated phase reference is in phase with the voltage supplied. In this regard, the method includes using the estimated excitation voltage time area to calculate a phase error between the supplied voltage and an internal phase reference. The phase error can then be used to create a driving point mounting waveform model in synchronization with the supplied voltage. The circuits in a welding control of the resistance welding system and components to measure the voltage and current supplied are used by the system to implement the method steps. The circuits may include a digital signal processor that has fixed elements and / or programming elements necessary to implement the functions described. According to another embodiment of the invention, a method for estimating an excitation voltage for synchronizing the firing elements of a resistance welding device comprises measuring a supplied voltage and a supplied current of an energy distribution system to a plurality of predetermined intervals, estimate a line resistance and a line reactance based on the measured values of the supplied voltage and the current supplied and estimate the excitation voltage based on the measured values of the supplied voltage and the supplied current and on the resistance of the line and line reactance estimated. The estimated excitation voltage is used by a phase reference generator as the synchronization base to provide a tripping signal to a thyristor of a resistance welding device. The method may further include calculating a time area voltage of the supplied voltage from the measured values of the supplied voltage, calculating a current time area of the supplied current from the measured values of the supplied current and calculating a time area. of current difference of the supplied current from the measured values of the supplied current. The voltage time area, the current time area and the area of current difference are used to estimate the excitation voltage. The step of estimating a line resistance and a line reactance comprises measuring a first set of a sampled voltage value and a sampled current value when the current is not flowing, measuring a second set of a sampled voltage value and a value of current sampled when the current is flowing and create an estimated line resistance and an estimated line reactance of the system based on the first set of a sampled voltage value and a sampled current value and the second set of a sampled voltage value and a sampled current value. The estimated line resistance and line reactance can also be used to estimate the excitation voltage. The method may further include estimating a phase error between the supplied voltage and the estimated excitation voltage. The estimated phase error can be used to determine the difference in phase between an internal time base and the phase of the estimated excitation voltage. According to another aspect of the invention, a method for estimating an excitation voltage of a resistance welding system is provided. The method includes taking periodic samples of a supplied voltage and a current supplied from a system to obtain sets of a sampled voltage value and a sampled current value. This may include first taking a first, second and third set of a sampled voltage value and a sampled current value and calculating a current difference value for each of the first, second and third sets. The method further includes creating an estimated line resistance and an estimated line reactance of the system based on the first set of a sampled voltage value, a sampled current value and a calculated current difference value, the second set of a value of sampled voltage, a sampled current value and a calculated current difference value and the third set of a sampled voltage value, a sampled current value and calculated current difference value. The method can also include taking one of the sampled sets when the current is not flowing (that is, equals 0). This can include the steps of determining if the current is flowing or not flowing and taking voltage samples when the current is not flowing. Choosing these data sets can simplify some of the calculations involved in determining the excitation voltage. According to a further embodiment of the invention, a phase reference generator is provided to track the voltage waveform of excitation of an energy distribution system for use in a resistance welding control. The phase reference generator comprises a digital signal processor configured to include: a digital volume-time area generator to generate a volt-time area of an observed voltage; a digital current-time area and a current-time-difference area to generate a current-time area of an observed current and a current-time-difference area of the observed current; a line impedance estimator; and an excitation voltage area estimator configured to receive values from the digital volt-time area generator, the digital time-current area generator and the current-difference-time area generator and the line impedance estimator and generates estimated excitation voltage values. The phase reference generator can be used to provide an output signal for firing a resistance welder. The phase reference generator further comprises an analog to digital converter for converting each of the observed voltage and the observed current from an analog signal to a digital signal. The phase reference generator also includes an internal synchronizer that triggers an analog-to-digital conversion of the observed voltage and current observed.

The phase reference generator may also include a phase error estimator. The phase error estimator is configured to estimate the phase difference between the estimated excitation voltage and a synchronization cycle generated by the phase reference generator. The phase error estimator is implemented in fixed elements of the digital signal processor once for each synchronization cycle generated by the phase reference generator. The phase reference generator further comprises a compensator configured to adjust a frequency of the synchronization cycle to move the synchronization cycle toward a synchronous phase with the estimated excitation voltage. To accomplish this, the compensator either increases the frequency of the synchronization cycle when the synchronization cycle is delayed from the estimated excitation voltage or decreases the frequency of the synchronization cycle when the synchronization cycle is ahead of the estimated excitation voltage. The phase reference generator may further include a quadrant generator. The dial generator is configured to provide an indication of a current quadrant of the synchronization cycle. According to another embodiment of the invention, a welding control is provided for a resistance welding system. The welding control comprises a phase reference generator configured to provide an estimated excitation voltage of a supplied voltage and generate a signal to trip a thyristor of the welding system during a welding operation. Welding control also includes a voltmeter function coupled to the phase reference generator and an input line to provide sampled values of the input line voltage and a current meter function coupled to the phase reference generator and the line input to provide sampled values of the line current. The phase reference generator may comprise a digital signal processor. The digital signal processor may include fixed elements and / or programming elements configured to function as a digital volt-time area generator, a digital time-current area and a current-time-difference-area generator, an estimator of line impedance and a volt-area estimator of impeller point. The digital volt-time area generator generates an estimated value of the input line voltage based on the sampled values of the input line voltage. The digital current-time area generator and current-time-difference generates an estimated value of the line current and the difference of the line current from the sampled values of the line current.

The digital signal processor also includes a line impedance estimator. The line impedance estimator is configured to generate an estimated value of the line resistance and line reactance based on the measured input line voltage, the measured line current and the first calculated difference of the line current. The digital signal processor also includes an impulse point volt-time area estimator. The impulse point volt-time area estimator is configured to provide an estimated value of the impulse point volt-time area based on the estimated value of the input line voltage, the estimated value of the line current and the difference of line current, line resistance and line reactance. The digital signal processor further includes a quadrant generator to provide a timing cycle of the phase reference generator having a frequency. Additionally, the digital signal processor includes a phase error estimator for estimating the phase error between the excitation voltage estimate value and the internal system timing cycle. Based on the estimated phase error, the digital signal processor uses a compensator to adjust the frequency of the timing cycle to bring the timing cycle in synchronization with the voltage of the excitation voltage.

According to a further embodiment of the invention, a digital phase reference generator for use in a welding control is disclosed. The digital phase reference generator comprises an interval timer configured to trigger an analog-to-digital conversion of a sampled input line voltage and an input line current sampled on a recurring basis. The input and current line voltage are from an energy distribution system. The digital phase reference generator further comprises a digital signal processor configured to execute an interrupt routine initiated by each consummation of the analog-to-digital conversion of a sampled input line voltage and a sampled input line current wherein a The default number of interrupt routines defines a timing cycle, the digital signal processor is further configured to generate an estimated value of the volt-time of the input line voltage, an estimated value of the current-time area of the line current input and an estimated value of the current-difference-time area of the input line current and an estimated line impedance value. The digital signal processor is configured to provide an estimated value of the impulse point volt-time area of the input line voltage. The estimated value of area volts-time point The impeller is used as the basis for calculating the error between the timing of the phase reference generator and the excitation voltage. The phase reference generator is used as the timing basis for the firing of thyristors of a resistance welding system. Unlike a prior art system in which the timing period of the phase reference generator is kept constant for the first few welding cycles, while the system determines the phase error caused by the excitation voltage distortion due to the line impedance, a system embodying the invention disclosed herein may continue to track the excitation voltage even under rapidly varying welding current conditions. Other elements and advantages of the invention will be apparent from the following specification taken in conjunction with the following figures.

BRIEF DESCRIPTION OF THE FIGURES In order to understand the present invention, it will now be described by way of example, with reference to the attached figures in which: Figure 1 is a block diagram of a phase reference generator according to an embodiment of the present invention; Fig. 2 is a diagram defining the quadrants of a phase reference generator cycle, when the phase reference generator is properly synchronized with the observed line voltage waveform; Fig. 3 is a block diagram of a phase reference generator compensator control system used in the phase reference generator of Fig. 1; Figure 4 is a flow chart of a quadrant generator; Fig. 5 is a block diagram of a digital volt-time area generator used in the phase reference generator of Fig. 1; Figure 6 is a block diagram of a digital current-time area generator used in the phase reference generator of Figure 1; Fig. 7 is a block diagram of a driving point volt-time area estimator used in the phase reference generator of Fig. 1; Fig. 8 is a block diagram of a line impedance estimator used in the phase reference generator of Fig. 1; Fig. 9 is a block diagram of a self-regressive run-to-run filter (R2R) used in the line impedance estimator of Fig. 9; Fig. 10 is a logic flow diagram of a line impedance monitor used in the phase reference generator of Fig. 1; Fig. 11 is a block diagram of a phase error estimator used in the phase reference generator of Fig. 1; Fig. 12 is a state diagram of a phase reference generator state machine; Figure 13 is a table showing adjustments of the phase reference generator for a resistance welding control; Figure 14 is a quadrant diagram of a phase reference generator cycle showing the relationship between the PRG and the input voltage sinusoid where the PRG is synchronized with the input voltage sinusoid; Figure 15 is a quadrant diagram of a phase reference generator cycle showing the relationship between the PRG and an input voltage sinusoid where the PRG is not synchronized with the input voltage sinusoid; Figure 16 is a table of parametric values of a sampled data system; Figure 17 is a derivation graph showing sample values of the voltage waveform for parametric values in the table of Figure 16; Figure 18 is a circuit diagram of an ideal circuit model for a welding control; Fig. 19 is a circuit diagram for a system model of a line impedance welding control; Figure 20 is a table of parametric values for the circuit of Figure 19; Figure 21 shows waveforms of the source volts, observed volts and welding current showing the distortion caused by the presence of line impedance; Figure '22 is a contaminated parameter circuit diagram of a resistance welding control and associated power distribution system; Figure 23 is a line voltage waveform as a function of time and a line voltage waveform as a function of the angle of observation; Figure 24 is a simplified model of a welding circuit that assumes no line impedance; Figure 25 is a voltage waveform resulting from the tripping of a thyristor with respect to time and a voltage waveform resulting from the tripping of a thyristor with respect to an observed angle; Figure 26 is a current waveform resulting from applying the parametric values of the table Figure 27 to a welding current equation; and Figure 27 is a table of parametric values for a welding current equation.

DETAILED DESCRIPTION OF THE INVENTION While the present invention is susceptible to embodiments in many different forms, they are shown in the figures and will be described in detail in the present preferred embodiments of the invention, with the understanding that the present disclosure will be considered as an exemplification of the principles of the invention and is not intended to limit the broad aspect of the invention to the illustrated embodiments. Referring to Fig. 1, a block diagram of the components of a phase reference generator ("PRG") 10 is disclosed to provide improved tracking of a line voltage to create more accurate firing points of a welding device by resistance. The present invention is preferably implemented in connection with a resistance welding control, such as the EQ5400 AC resistance welding control, sold by the Square D Company, to create a PRG timing cycle to match or match the voltage of excitation of a power supply and distribution system. The EQ5400 AC resistance welding control may be modified to include the elements herein as described below in the I presented . In a mode using an EQ5400 AC resistance welding control, a commercially available digital signal processor (DSP), preferably Model TMS320F2407A, manufactured by Texas Instruments, is used to perform an analog-to-digital conversion of voltage and current signals. external, digital signal processing, and timing generation. In this mode, the PRG timing is controlled by a physical element interval timer included in the DSP, the interval from which it can be adjusted under the control of programming elements. When the timer period expires, it starts timing a new period and simultaneously triggers the analog-to-digital conversion of a selected signal sequence, independent of the present processing that is performed by the DSP. This includes signals sensitive to the instantaneous welding current and the voltage observed at the input terminals of the welding control. The completion of the analog-to-digital conversion sequence triggers an interruption in the DSP, which then suspends processing for a time and executes a routine of interrupting fixed elements. In this way, critical operations can be carried out in a timely manner and at regular intervals. One aspect of the particular DSP used is that the interval timer is "overshadowed", which means that when a new period is provided to the interval timer, this new period is applied at the expiration of the present interval. In the implementation of the resistance welding control of EQ5400 AC, the PRG cycle is defined as the range covered by 128 interrupts generated by the DSP according to the above description. Each cycle of PRG is divided into four quadrants, marked as ql, q2, q3 and q4 in figure 2. Each quadrant represents a range of 32 DSP interruptions. From the above discussion, it is clear that the time period of a PRG cycle is variable and it is this element that allows the PRG cycle to synchronize with a sinusoidal waveform observed as shown in Figure 2 and is discussed later in the present. As the system is designed, the interruption interval is constant within a PRG cycle. The objective of the PRG 10 is to synchronize the internal quadrants with the observed voltage source in such a way that if the PRG cycle is synchronized with a purely sinusoidal voltage of constant magnitude, the quadrants correspond to the following ones (shown visually in Figure 2). ): Quadrant 1 represents the interval between the zero crossing from positive to negative of the sinusoid and the positive peak of the sinusoid; Quadrant 2 represents the interval between the positive peak of the sinusoid and the positive zero crossing to negative of the sinusoid; Quadrant 3 represents the interval between the positive and negative zero crossing of the sinusoid and the negative peak of the sinusoid; and Quadrant 4 represents the interval between the negative peak of the sinusoid and the zero crossing from negative to sinusoid. Fig. 1 is a higher-level block diagram showing the closed-loop system of the present invention for modeling, estimating and tracking the excitation voltage. The various components shown may be implemented in the fixed elements and / or programming elements of the DSP and may additionally include the use of additional circuits and are sometimes referred to herein as functions of the PRG. The index "n", which appears in various quantities, refers to the nth cycle of PRG after a reference cycle, usually the first cycle after the system is turned on. It should be understood that this index, n, is a mathematical entity, incorporated to make use of difference equations in a standard mathematical format. The value of the interruption period, Ts (n + 1), for the next PRG cycle is supplied by a compensator 1 of the PRG. The inputs to the compensator 1 of the PRG are the phase error sequence e (n), generated by a phase 2 error estimator and the "state" of the PRG, marked PRGState (n), generated by a PRG state machine 3. PRG Compensator 1 is executed once per PRG cycle, sometimes in the interval of quadrant 4 in figure 2, when all the inputs require that the PRG compensator be run for the present PRG cycle are available. The interruption period Ts (n + 1), generated by the compensator of PRG 1, is provided to a quadrant generator 4 which is a resident function in the fixed elements of the DSP. The quad generator 4 is executed once per interruption. Declares to the system the present quadrant value, q, in the set. { ql, q2, q3, q4} . It also provides a universal logical semaphore, NQ, indicating the beginning of a new quadrant when it is set to TRUE. The value of this logical semaphore is universally known for all the functions in the PRG system. The quad generator 4 also handles the timing of the application of the new interruption period, adjusting it in the transition between q4 of the present PRG cycle and ql of the next PRG cycle. The PRG quadrant value q is an input to the PRG 3 state machine, a digital volt-time area generator 5, marked as digital VTA in Fig. 1 and a current-time and current-difference generator 6 -digital time, marked digital ITA generator in figure 1. The digital VTA generator 5 is executed once by DSP interruption and generates an estimated value of the observed volt-time area, VwcTA (q, n) for each quadrant from the digitized samples quantified in the form continuous analog line voltage waveform Vwc (t) generated by the analog to digital converter function of the DSP. The digital VTA generator 5 also generates an estimated value of the observed absolute time-volt area, AVwcTA (q, n) in a manner that will be described subsequently. The digital ITA generator 6 is also executed once by DSP interruption and generates estimated values of quadrant current-time in quadrant ITA (q, n) and estimated values of the area of the first difference of the current AITA (q, n ), of the digitized, quantized samples of the instantaneous current generated by the analog to digital converter function of the DSP. The VTA estimator function 7 of impulse point is executed once per quadrant and uses the values of VwcTA (q, n) provided by the function of the digital VTA generator 5 and the values ITA (q, n) and AITA (q) , n) provided by the function 6 of the digital ITA generator, together with estimated values of the line resistance, R * line (m) YX * teq / provided by a line impedance estimator function 8 to generate estimated values of Volt-area time-point of driving point, VdpTA (q, n). The meaning of the index "m" in R * line (m) and X * teq (m) will be discussed subsequently. The estimated values of quadrant VdpTA (q, n) are fed to a function 2 of the phase error estimator, executed once per PRG cycle when the Volt-time area values of driving point are available from quadrants 2 and 3. The phase error estimator 2 calculates an estimated value of the phase error between the estimated open circuit voltage source voltage waveform and the present timing of the PRG quadrants. The output of the phase error estimator 2 is a sequence of phase error values, e (n), one per PRG cycle, which feeds the compensator 1 of PRG, closing the loop. As described above, the estimated line resistance sequences, R * line Y reactance X * teq (m) are provided by function 8 of the line impedance estimator. This line impedance estimator function uses the outputs provided by the digital VTA function 5 and the digital ITA function 6, together with an external knowledge of when to calculate a new estimated line impedance value provided by a digital supervisor function. line impedance 9 to be described subsequently herein. In the block diagram of Figure 1, the line impedance supervisor function 9 provides a semaphore command of programming elements, LI_COMPUTE to line impedance estimator function 8 to determine in which cycle of PRG to calculate a new estimated value of line impedance parameters R * line) YX * teq (ro) · The index "m" in the values of the line impedance parameter it refers to the mth of such updating of line impedance parameters from the initialization of the system since power was first supplied. Figure 3 shows a block diagram description of the system of the function 1 of the PRG compensator of figure 1. In the resistance welding control AC EQ5400, this function is fully implemented in the fixed elements of the DSP. Function 1 of the PRG compensator is executed once per PRG cycle, at a time when the most recent phase error estimate value, e (n) is available, after quadrant q3 and in time for quadrant generator 4 to establish the speed of elementary samples for the next line cycle of PRG, Ts (n + 1). PRG Compensator 1 attempts to drive the estimated phase error between the PRG timing cycle and the estimated excitation voltage signal by slightly increasing the internal PRG frequency to "match" with the estimated excitation voltage signal if the phase of the PRG timing cycle is delayed from the estimated excitation voltage signal or the internal PRG frequency decreases to allow the estimated excitation voltage signal to "catch" or match the PRG timing if the estimated phase error shows that the PRG timing cycle is ahead of the external excitation voltage signal.

Mathematically, there are three internal state variables maintained by the compensator function of PRG 1, marked ?? (n), xl (n) and x2 (n) in figure 3. The state variable x2 (n) represents the cumulative sum of the phase error since the PRG compensator 1 has been initialized in a way to be described Subsequently. The state variables xO (n) and x (n) are incorporated to allow the response of the system to be completely controlled, compensating for the fact that the phase error is estimated at a point that is at the center of a present PRG cycle, while the consequent adjustment in timing is made in the quadrant transition between q4 of the present cycle and ql of the next cycle. Using well-understood techniques of modern linear control theory, it can be shown that when coupled to the system, such a system is completely controllable in one direction of the control system, and that the response of the system can be adjusted to any desired reasonable value. In matrix format, the shape of the state difference equations that describe function 1 of the PRG compensator are: with the output Ts (n + 1) given by: where kxO, kxl, ki, kp and K2 are parameters of the control system and the value Tsn0m represents an expected elementary sample period. The specific values of these constants are dependent on the state of the PRG generator 10, provided by the state machine PRG 3 in the state variable PRGState (n + 1). The discussion of the actual parametric values used as a function of the state of the system is deferred to the description of the PRG state machine. The quad generator 4 is also implemented in fixed elements of DSP and is executed in each DSP interruption of the system. Figure 4 is a flow diagram showing the process of the quadrant generator 4. The quad generator 4 maintains an internal counter, SC, of DSP interrupts from the beginning of the present PRG quadrant. At the input 401 on the kth DSP interrupt from the beginning of this PRG quadrant, the quad generator 4 first increments the value of the SC counter in process block 402. In decision block 403, the DSP compares the value of the SC counter with a constant value SPQ, indicating the number of DSP interrupts per quadrant. In the implementation of the resistance welding control AC EQ5400, SPQ is 32. If the value of SC is not greater than or equal to SPQ, control passes to control block 404, in which the new quadrant traffic light, NQ is set to FALSE, indicating that this elementary sample does not represent the beginning of a new quadrant. The value of this traffic light is universally known for the system. Once the NQ traffic light has been set to FALSE at 404, the system sets the present quadrant value, q (k) to the previous value, q (kl) in process block 405, since the quadrant has not changed . In decision block 406, quadrant generator 4 searches for the specific condition for the last DSP interrupt in quadrant q4. This condition is indicated by both of the following certain conditions: q. { k) =? (3) Y SC = SPQ ~ l (4) If either one or the other of these conditions is FALSE, the routine normally exists at 408. If both of these conditions are true, the quadrant generator 4 first loads the interval counter of physical elements of the DSP with the value Ts (n + 1) obtained from the compensator of PRG 1. This occurs in process block 407, before leaving normally at 408. As discussed previously, this new set point value will be loaded to set the DSP interruption period the next time the interval counter reaches its set point value, which is the correct time to set the DSP interruption period for the next PRG cycle. Referring again to decision block 403, if the sample count SC is greater than or equal to the constant value SPQ, it is time to make a transition to a new quadrant and the process blocks 409, 410 and 411 are executed sequentially. In process block 409, the SC counter is reset to zero. In process block 410, the value of the quadrant, q (k) is increased. In process block 411, the value of the new quadrant semaphore, NQ is set to TRUE, indicating to the rest of the PRG functions that this DSP interruption represents the first DSP interruption of a new quadrant. The control then passes to decision block 412 in which the quadrant value q (k), incremented in process block 410 is compared to determine whether the value of the new quadrant falls within the range. { ql, q2, q3, q4). If so, the routine normally comes out at 408. If not, the quadrant value q (k) is set to ql, indicating the start of a new PRG cycle. The control then normally goes to 408.

Figure 5 is a block diagram of the digital VTA generator 5. The digital VTA generator 5 generates estimated values of the volt-time area of the line voltage at the observed line input of the welding control for each quadrant q e. { ql / q2, q3, q} of the PRG, marked VwcTA (q, n) in figure 1, also as an amount AVwcTA (q, n) for each quadrant, formed by first taking the observed absolute value of welding voltage and generating a trapezoidal accumulation. In the AC EQ5400 resistance welding control, the digital VTA generator function is implemented in a combination of analog electronic circuits, digital electronic circuits and digital signal processing fixed elements. The unprocessed analog voltage line voltage input signal, Vwc (t), is that signal that appears at the power input of the welding control. This is a power line voltage signal, commonly with a nominal value of 480 Volts R S in an automotive body shop in the United States of America. The power system is also capable of supplying very large currents to anything connected to it. Thus, both to reduce the voltage observed by the system to the levels those digital electronic elements and low voltage analogs can handle while simultaneously limiting the potential current that can flow to the digital VTA function to safe levels, an attenuator circuit of voltage 21 is incorporated in the design. In the AC EQ5400 resistance welding control, the voltage attenuator circuit comprises two commercially available high-precision high voltage voltage divider networks, based on thick film technology. The output of the voltage attenuator circuit 21 is a signal Vwca (t), sensitive to Vwc (t), but attenuated by a factor of approximately 125: 1, such that a sinusoidal voltage signal of 480 V RMS at the input appears as a sinusoidal signal of approximately 3.84 V RMS at the output of the attenuator. The analog signal Vwca (t) is fed to an anti-alias filter 23, which serves to band-limit the signal that is fed to the A / D converter function 25. It is well understood in the study of sampled data systems that faithfully represent an analogous signal as a sequence of digital samples, the sampled signal must be limited in band to no more than half the frequency of sampling or the phenomenon commonly called alias will result, confusing the result. In the resistance welding control of AC EQ5400, a six-pole elliptical filter is implemented in similar physical elements to limit the sampled signal in band. The limited, attenuated band representation of the line voltage signal is marked Vwcf (t) in Figure 5. The analog to digital converter function 25 is integral to the DSP and takes samples of the Vwcf signal. { t), sensitive to Vwc (t) once due to DSP interruption. The sample period for a given PRG cycle is Ts (n), calculated by the compensator PRG 1 and adjusted by the quadrant generator 4. The analog-to-digital converter quantizes each sample to a number of 10 bits in a way that can be used by the DSP. This numerical sequence is marked Vwcs (k) in Figure 5. In the resistance welding control of AC EQ5400, 128 such samples are taken per PRG cycle. The sampled and quantized sequence Vwcs (k) generated by the A / D converter function of the DSP is fed to a trapezoidal integrator / accumulator 27 marked by functional blocks in figure 5. This function is implemented in fixed DSP elements and estimates the area of volt-time of each quadrant when accumulating samples on the quadrant using the trapezoidal integration rule: where the index j refers to the elementary samples Vwcs (k), but referred to the beginning of the nth cycle of PRG. This function creates four estimated values per PRG cycle. Estimated values of previous quadrants are complete and a new estimate value will begin to receive the new NQ universal quadrant semaphore of the generator quadrant 4. To generate the sequence AVwcTA (q, n), supplied by the digital VTA function and used by the state machine of PRG 3, the mathematical absolute value of the sequence VwcgTA (k) is taken first (shown by the reference 28). The output of this absolute value function, marked AVwcsTA (k) is fed to another trapezoidal integrator 29 which operates identically to that which generates the sequence VwcsTA (k). The output of the trapezoidal integrator 29 is the sequence AVwcTA (q, n), shown in Figure 1. Figure 6 shows a block diagram of the digital ITA generator function 6 of the PRG 10 system, to estimate the area of current-time (ITA) and the time-difference current area (????) of each quadrant of PRG. As was the case with the function of the digital VTA generator function 5, this function is implemented in a combination of electronic physical elements and fixed elements of DSP. In the resistance welding control of AC EQ5400, a welding current is passed through a commercially available passive AC current transformer 31 with an associated load resistor. The current transformer 31 generates a secondary current proportional to the main welding current passing through its opening. When this current passes through the resistor charged through the transformer secondary, a voltage Vct (t) is generated. As in the function of digital VTA generator, voltage Vc (t) is filtered by an anti-alias 6 elliptical filter 32 analogue poles 32. The resulting band-limited signal is marked Vctf (t) in Figure 6. The band-limited signal Vctf ( t), sensitive to the instantaneous welding current, is sampled by the analog to digital converter DSP 33, which is an analog to digital channel separate from that of the function 5 of the digital VTA generator 5, but which operates in an identical manner and is sampled essentially at the same time as that of the function 5 of the digital VTA generator, at the speed Ts (n) established by the compensator 1 of PRG and the quadrant generator 4. The sequence of numbers resulting from this sampling and quantization process is marked i (k) in figure 6. The sequence i (k) directly feeds the trapezoidal integrator / accumulator 35, which operates identically to that described in function 5 of the digital VTA generator, producing values quadrant estimates of the current-time area ITA (q, n), with q e. { ql, q2, q3, q4} , one per quadrant of PRG. The sequence i (k) also feeds a current difference function 37, which generates the sequence? (k), in accordance with: ?? (*) =? { *) -? (* -?) (6) This signal is fed to another trapezoidal integrator / accumulator 39, which also operates identically to that described in function 5 of the digital VTA generator, producing quadrant estimates of the area of current-difference-time, AITA (q, n) with q ec. { ql, q2, q3, q4} , one per quadrant of PRG cycle. Figure 7 is a block diagram description of the operation of the function 5 of the driving point VTA estimator. This function is executed once per quadrant in the transition from one quadrant to another to produce VdPTA (q, n) of open circuit VTA estimates used by the phase error estimator 2. Once all the data is available, the system executes the mathematics of Figure 7, which implements the equation: Fig. 8 is a block diagram of the line impedance estimator function 8, which provides the line impedance impedance estimators R * line (m) and X * ieq (m) to the point VTA estimator 7 driving. The function 8 of the line impedance estimator is executed conditionally at certain times, to update the estimated values of the line resistance and reactance. The command to perform an update is represented by the logical assertion of a LI_CALCULAR signal, which is asserted at times to be discussed subsequently by the line impedance supervisor function 9. The index m in the values R * line (m) and x * ieq (m) refers to the mth of such ordered update of line impedance values. In the implementation of the resistance welding control of AC EQ5400, the line impedance estimator 8 continuously maintains a memory of the previous value of the estimated VTA values observed for quadrants 2 and 3. These signals are represented in figure 8 as the outputs of unit delay blocks 81 and 82 and are marked VWCTA (q2, n-1) and VwcTA (q3, nl) respectively. In the command, the line impedance estimator 8 generates a new estimated value of the line impedance values * line (m) and X * ieq (m), as determined by the assertion of the LI_CALCULAR signal. In this nth line cycle, when the LI_CALCULAR signal is asserted, the values ITA (q2, n), ITA (q3, n), AITA (q2, n) and AITA (q3, n), all provided by the digital ITA generator 6, also as the values VwcTA (q2, n) and VwcTA (q3, n), provided by the digital VTA generator 5 and the delayed volt-time area values VWCTA (q2, n-1) ) and VWCTA (q3, n-1) described above feed the estimator array 83. The estimator array 83 produces results R (m) and X (m) according to the equation: where R (m) and X (m) are the estimated values instantaneous resistance and inductive reactance respectively for the mth estimated value. The mathematics behind this matrix equation will be derived subsequently. The assumptions made in calculating the line impedance estimate value are: 1) there is one and only one device that loads the main welding line at the same time and 2) the excitation voltage is a sinusoid and remains constant in the interval in which the calculation is based. However, it is recognized that an individual welding control does not have a priori knowledge of the presence or affinity of other devices that may be drawing current from the main welding energy distribution line and the instantaneous estimating value realized using equation (8). ) above may be in error if another equipment is loading the main welding distribution line in the line cycles in which the estimate value is made, violating one or both of the previous assumptions. To help alleviate this condition, each of the values R (m) and X (m) are filtered using run-to-run filters (R2R) 85 and 87. A block diagram of the shape of these identical filters is shown in Figure 9. Filters are auto-regressive filters that have the general form: .t (m + l) = (í -ü: /) ^ (m) + ^ / M (w) > 0 = K = l and (m) = x (m + l) where u (m) is the filter input (R (m) or X (m) in Figure 8), x (m) is the internal state variable, Kf is the filter constant, 0 < Kf = 1 ey (m) is the filter output, Riinean (m) * or Xeq (m) * respectively in figure 8. Run-to-run filters tend to "smooth" the errors that could be made in the values individual impedance estimates and result in a more consistent estimate than that which would result from using the individual estimate values R (m) and X (m). In practice, using the individual unverified estimating values R (m) and X (m) directly (which can be done by adjusting Kf = 1) has produced excellent results - run-to-run filters are not necessary for the invention work and should not be considered as a limitation of the invention. However, for operation in a noisy environment such as in an automotive body shop, it has been found experimentally that the inclusion of these run-to-run filters with Kf = 0.25 provides an additional measure of noise immunity against the condition in which previous assumptions have been violated. The line impedance supervisor function 9 is to determine in which cycles of the PRG to estimate function 8 of line impedance estimator. In the present embodiment, the objective is to execute the line impedance estimator 8 in the first cycle in which the current is flowing, followed by several cycles in which the current has not been flowing. In a typical automotive application, a resistance welding control is normally inactive for several seconds, while a part or all of an automobile is moved to the position to be welded. During this period, where there is no current flowing, the PRG 10 can acquire the excitation voltage waveform without distorting the energy system. If it is assumed that the voltage waveform of the power source does not vary much from one cycle to another, then it can be assumed that the voltage waveform in the last line cycle before welding is representative of the shape of excitation voltage wave of the power source in the first cycle in which the welding has begun. The function 9 of the line impedance suppressor is to monitor the system for this condition and trigger the execution of the line impedance estimator function 8 when the appropriate condition is detected. Fig. 10 is a flow chart of the line impedance monitor function 9, which is a fixed element entity of DSP executed once per PRG cycle. Integral to function 9 of the online impedance supervisor is a static IDLE counter, used by the function 9 of the line impedance monitor to determine when the system has been inactive for a sufficient period to ensure that the PRG is solidly tracking the voltage waveform of the power source. Referring to FIG. 10, at the input to the fixed element logic at 1401 during the line cycle n, the function 9 of the line impedance monitor determines first- in the decision block 1403 whether the system is welding during the duty cycle. line n. Assuming that the system is not welding during line cycle n, the flow is transferred to process block 1405, where an integral IDLE counter is incremented by the DSP. Once the counter is incremented, in decision block 1407 the resulting count is compared against an integer NLI, which is a design parameter that indicates the minimum number of seamless cycles required to ensure that the PRG is tracking exactly to the voltage of the power source. If the value in the inactive counter is greater than Nu, then the prerequisite number of the seamless cycle has been satisfied and the value in the count is set to NLI in the process block 1409. The flow is transferred to the process block 1411 in which the semaphore LI_CALCULAR is set to a logical FALSE value, indicating to the line impedance estimator 7 that no update of the impedance of the line must be made. line . If in the decision block 1407 the line impedance monitor function 9 determines that the value in the INACTIVE counter is less than or equal to NLI, the control is transferred directly to the process block 1411 and the semaphore LI_CALCULAR is set to a value FALSE logical as before. Once the process block 1411 is executed, the routine exits at 1413 until it is again executed in the next PRG cycle. Referring again to decision block 1403, if it is determined that the welding current is flowing in welding cycle n, control passes to decision block 1415, in which the value in the INACTIVE counter is compared against the value NLi. . If it is determined that the value in the INACTIVE counter is not exactly NLi, then an insufficient number of seamless cycles were detected to characterize a new estimated value of the line impedance. This condition exists when a pause between individual solders of less than NLI line cycles occurred or simply because the system is currently halfway through the execution of a weld. Either in one case or another, if an insufficient number of seamless cycles are detected by the routine, the semaphore LI_CALCULAR is set to a false logical state in the process block 1417 and the value of the OFF counter is set to zero in the process block 1419. If, in decision block 1415, the value of the INACTIVE counter is equal to NLi, then the conditions for executing and updating the estimated value of the line impedance are satisfied. The control passes to process block 1421, in which the semaphore LI_CALCULAR is set to TRUE. Once this has occurred, control passes to process block 1419, where the value of the INACTIVE counter is set to zero as before. Once process block 1419 is executed, the routine exits as before at 1413 until it is again executed in the next PRG cycle. Figure 11 is a detailed block diagram description of the phase error estimator 2 of the RPG system. This function is implemented in fixed elements of DSP and is executed once per PRG cycle, during quadrant q4, after the excitation voltage estimating values VdpTA (q2, n) and VdPTA (q3, n) of quadrants 2 and 3 have been made by the excitation voltage estimator 7. For each line cycle, n, this block uses the open circuit volt-time estimate values of quadrants 2 and 3, VdPTA (q2, n) and VdPTA (q3, n), provided by the voltage estimator 7 excitation to estimate the error between the internal time base (that is, PRG timing cycle) and estimated excitation voltage. The block diagram in figure 11 implements the expression math : As this expression approximates the error it will be discussed subsequently in the present. The PRG state machine 3 determines the state of the PRG and guidance to the PRG through the initialization process, when nothing is known with respect to the relationship between the PRG timing and the actual timing of the power system, to the point where the PRG is declared "synchronized" by the system of energy and welding can start. Figure 12 shows a system state diagram of the state machine of PRG 3. The output of the state machine of PRG 3 is the state variable of PRG PRGState (n), which takes a value in the set. { NOSYNC, SYNCING, SYNC} . The state machine of PRG 3 is implemented in fixed elements of DSP and is executed when the PRG is in quadrant q4, after the error estimator of phase 2 has been executed for the present cycle of PRG. From the on state, marked PON in Figure 12, the state of the system is immediately set to NOSYNC. When the system is in the NOSYNC state, nothing is assumed with respect to the relationship between the PRG quadrants and the observed line voltage waveform. The objective of PRG 10 in the state of NOSYNC is to observe the line voltage Vwc (t) and align the PRG quadrants in such a way that the zero cross from positive to negative Vwc (t) occurs near the transition from quadrant q2 to quadrant q3. That this condition exists is determined by satisfying the following three conditions: Condition 1: The sum of the absolute volt-time areas of the quadrant of the previous line cycle, AVwcTA (q, n-1), q = 1,2,3 , 4, hereinafter referred to as AVTA (nl) is greater than a minimum value. This condition is required to ensure that the system is of course tracking a real voltage fed by the power system of a minimum value and not just random noise as a result of an open circuit condition in the power system. In the actual design of the AC EQ5400 resistance welding control, the minimum AVTA required to satisfy this condition is the theoretical value that would be obtained by applying a sinusoidal voltage input of 30 volts RMS, when the line voltage is properly synchronized with the PRG (however, other voltages can be used). Condition 2: The value VdpTA (q2, n) is positive and the value VdpTA (q3, n) is negative. This indicates that the zero crossing of the energy waveform to be "followed" occurs somewhere between the present quadrants q2 and q3. Condition 3: The error value calculated by the Phase error estimator, e (n) is "small enough" to allow the PRG to begin the closed loop acquisition. In the resistance welding control of AC EQ5400, this value is approximately 22.5 degrees. When in the NOSY C state, the AC EQ5400 resistance welding control is not allowed to conduct current. A planned consequence of this is that the excitation voltage is identical to that observed by the system at the input terminals of the AC EQ5400 resistance welding control. To effect the nominal alignment between the PRG 10 and the input sinusoid, the constants of the PRG compensator kxO, kxl, ki, kp and K2, shown in figure 3 are set to zero and the values of the state variables ?? (n), xl (n) and x2 (n) forced and maintained at zero when the system is in the NOSYNC state, such that the PRG 10 does not modify the interruption sampling period of a nominal value TSnom. This results in a fixed PRG cycle frequency as long as it is in the NOSYNC mode. The nominal operating line frequency voltage of the welding control system is assumed a priori known. For example, it is known that a system planned to operate in the United States of America operates at a nominal line frequency of 60 Hz and that the frequency will be regulated quite accurately by the power generating plant that generates the energy - usually within +/- 0.2 Hz. When in NOSYNC mode, the AC EQ5400 resistance welding control uses a TSnom value that will generate a PRG frequency of 1 Hz. Less than the expected operating frequency. For example, for a system designed to operate at 60 Hz, TSn0m is set at 132 microseconds, which results in a PRG cycle frequency of approximately 59 Hz. Thus, for a condition in which the crossing from positive to negative zero of the actual observed line voltage occurs outside quadrants q2 or q3, in each subsequent PRG cycle, the zero crossing of the line voltage will occur earlier in the PRG cycle that in the previous PRG cycle and optionally "will be wrapped" to the next PRG cycle. Eventually, zero crossing will occur near the transition between q2 and q3 of the PRG. For the given conditions, assuming that the line frequency is the nominal value, the estimated phase error must change by only 6 degrees per PRG cycle, ensuring that if condition 1 can be obtained and assuming that the observed waveform is Actually sinusoidal by nature, the remaining conditions can be satisfied in the course of 1/3 seconds under normal conditions. For a system that operates nominally at 50 Hz, TSnom is selected in such a way that the nominal PRG cycle frequency is approximately 49 Hz. Once the above conditions have been satisfied, the PRG state machine declares that the PRG is in the SYNCO state. In this state, the value of TSn0m remains fixed in the NOSYNC setting, but the constants kxO, kxl, ki, kp and K2 are adjusted to their operating values. The table in Figure 13 provides the parametric values of the PRG 1 compensator currently used in the AC EQ5400 resistance welding control for 60 Hz operation. The values of the state variables xO (n), xl (n) and x2 (n), shown in Figure 3 are explicitly initialized to zero, when the state of SYNCO is first entered. Unlike the state of NOSYNC, however, they are not maintained at zero, but they are allowed to assume values according to the operation of the PRG 1 compensator discussed previously. When put into operation as a closed loop according to the PRG system 10 described herein, the chosen parametric values provide an excellent system response with good alteration rejection, driving the estimated phase error sequence, e ( n), to zero in response to reasonable power system line voltage and establishing a relationship between the PRG and the observed energy voltage waveform desired in Figure 2. Once the PRG constant values have been established and the state variables initialized to zero, allows PRG 10 to operate in the SYNCO state, calculating corrections to the interruption period, Ts (n + 1) until one of three events occurs: (1) The observed error e (n) is less than a threshold value fixed by more than one fixed number of consecutive PRG cycles. (2) The observed error, e (n) is greater than the fixed threshold value for greater than a fixed number of consecutive PRG cycles. In the resistance welding control of AC EQ5400, this fixed number is 30 for both previous cases. (3) The total AVTA observed for the previous line cycle is less than the minimum value given in the description of the previous NOSYNC status. In the AC EQ5400 resistance welding control, the error threshold set for the SYNCO state is approximately 11.25 degrees. If condition 1 is satisfied first, the PRG transitions to the state of SYNC. If either an other condition 2 or 3 is satisfied first, the PRG transitions back to the NOSYNC state. It will be noted that under "normal" operating circumstances, which require that the error threshold condition be satisfied for 30 consecutive cycles, it establishes a very small phase error by the time the transition to "SYNC" is performed. For a system operating at 60 Hz, this corresponds After the transition from the state of SYNCO to SYNC, the values of the state variables ?? (n), xl (n) and x2 (n) shown in Figure 3 are initialized to zero and the value TSnom is set to TS (n), the last value of the interrupt period generated from the SYNCO state. Under normal conditions, this new TSn0m value generates a PRG cycle period very close to that of the line voltage, so that the system now only needs to make minor corrections to the interruption sample period for the PRG to maintain synchronization with the line voltage. In the SYNC state, the AC EQ5400 resistance welding control is allowed to weld. Once in the SYNC state, the PRG remains in that state until one of two conditions occurs: Condition 1: The magnitude of the estimated error value, e (n), exceeds approximately 22 degrees for more than 5 consecutive PRG cycles , in which case the system transitions back to the SYNCO state. This allows the PRG to travel through any minor disturbance that may occur in the power system, while disabling welding and attempting to reacquire synchronization with the line voltage if the disturbance is large. Condition 2: The total AVTA observed over the previous line cycle is less than the minimum AVTA described in the NOSYNC state discussed above. If this occurs, the PRG immediately falls back to the NOSYNC state and the system is initialized and operates according to the state description of NOSYNC above. The phase reference generator 10 in the welding timer provides the basis for timing for tripping the thyristors. It also triggers the timing of the function of the RMS voltage estimator (digital voltmeter), as well as the function of the RMS current estimator (digital current meter). The method of estimating phase error is based on integrating portions of the input line voltage observed to the system. The following discussion explores the mathematics that is useful for understanding the operation of the present invention in an AC resistance welding application. In a mathematical circuit model of the power distribution system, it is assumed that the voltage generated by the power generation and distribution system can be modeled as an ideal driver voltage source Vdp (t) of the form: where f is the frequency, F is the phase of the sinusoid in relation to a reference time t = 0, Vra (t) is the peak voltage, denoted as a function of time. At this point in the discussion, it is recognized that Vm (t) is a modulation term that varies with time. Assumptions in the behavior of Vm (t) will be made subsequently that They will simplify the analysis. The objective of the phase reference generator 10 of the present invention is to generate an internal time base that can continuously track the excitation voltage Vdp (t), so that the following two conditions are maintained: Condition 1: The period fundamental of the phase reference generator, T, corresponds to af in equation (0.11), this is f = l / T; and Condition 2: The phase error observed between the PRG and the voltage source VdP (t) is zero at the positive to negative zero crossing of the sinusoidal waveform. Referring to equation (11), a fundamental assumption in the present analysis is that the source of input power to the weld control is a sinusoidal source of fixed frequency and closely known, but unknown and fixed phase in relation to the generator of internal phase reference 10. It is also assumed that the voltage modulation term, Vm (t) in (11) above varies slowly and is effectively constant in the interval in which the calculations are based. The phase reference generator 10 does not generate a per-se waveform, but the PRG timing can be visualized as a square wave of frequency twice that of the fundamental period of the sinusoid that is being tracked. In this representation, a PRG cycle comprises two cycles of the square wave. This visualization is used because in the actual implementation of the PRG in a digital signal processor or DSP it is possible for the DSP to generate the square wave as a result or output, in such a way that it can be observed in relation to the sinusoid using an oscilloscope. Figure 14 shows such a representation, together with the input sinusoid, assuming that the phase reference generator is in full timing with the sinusoid. In this visualization, four "transitions" of the phase reference generator can be observed for each cycle of the sinusoid, dividing the sinusoid into quadrants, marked ql, q2, q3 and q4 in figure 14. It is important in what follows to have in that the "quadrants" are defined in relation to the PRG that may or may not be synchronized with the sinusoid. A digital-to-digital converter function of the AC EQ5400 resistance welding control is, by design, synchronized with the PRG and takes a constant number of equally spaced samples of line voltage waveform per internal PRG line cycle. In the actual design of the AC EQ5400 resistance welding control, the analog to digital converter generates 128 such digitized voltage samples per PRG cycle or 32 samples per quadrant. Suppose there is a resident function in the system capable of generating the true mathematical integral of voltage in each quadrant of the PRG. Of interest in this analysis is the volt-time area over quadrants q2 and q3, which represent the shaded areas VTA2 and VTA3 in Figure 14. Because a sinusoid has an odd symmetry about the 180 degree point, it can be see from figure 14, that when the PRG is synchronized with the sinusoid, the volt-time areas VTA2 and VTA3 are of equal, but opposite sign, such that if they are added, the net sum of the volt-time area It is zero. This is not the case when the PRG is not synchronized. Figure 15 shows a condition in which the positive-to-negative zero crossing of the voltage input retards the transition from q2 to q3 of the PRG by an angle e. In this case, it is easily seen that the volt-time areas represented by VTA2 and VTA3 are not of equal magnitude. Comparing Figure 15 with Figure 14, it can be seen that when the PRG is ahead of the input voltage, the calculated magnitude of VTA2 will be greater than that when the PRG is synchronized, and the calculated magnitude VTA3 will be smaller than when it is synchronized. . Thus, when VTA2 and VTA3 are added as quantities with signs with positive VTA2 and negative VTA3, the result is a positive quantity, indicating the front characteristic of the PRG with respect to the input voltage. Similarly, it can be contemplated that if the PRG delays the input voltage, the sum of VTA2 and VTA3 will be an amount negative, indicating a condition of delay. It will now be shown that for small values of the phase error, e, between the PRG and the input voltage sinusoid, a normalized sum of VTA2 and VTA3 provides a very good direct estimate of the phase error. With respect to Figure 15, the equation describing the input voltage waveform, VdP (t), with time referred to the PRG is (12) where Vm is the fixed amplitude of the voltage sinusoid, f is the frequency of the sinusoid and e is the phase error between the sinusoid and the PRG. To re-iterate, it is proposed that the frequency is known and that all three of these values are constant. As indicated above, e positive indicates that the sinusoid delays the PRG or equivalently, the PRG is ahead of the sinusoid. The fundamental period of the PRG is denoted by T and if it is assumed that the PRG and sinusoid have the same fundamental frequency, T is related to f by: In Figure 15, the interval q2 is represented as the closed time interval [T / 4, T / 2]. The interval q3 is represented by the closed interval [T / 2.3T / 4]. With these defined intervals, the integral of the sinusoid on q2, denoted VTA2, is Using the plane geometry relationship eos (a-b) = eos (a) eos (b) + sin (a) sin (b) equation (14) becomes simply IT VTA2 = - [cos (r) ~ sin (e)] Similarly, VTA3 is given by: T tf adding VTA2 and VTA3 produces: VTAQ2 + VTAQ3 = - sen (e) (18) while subtracting VTA3 from VTA2 results in: VTA2-VTA3 = - ~ cost) (19) Now, the quantity E is defined by: VTA2 + VTA3 VTA2-VTA3 Substituting (16) and (17) for VTA2 and VTA3 and simplifying fields: E-um (e) (21) which, for small values of the phase error e, becomes an approximation: £ = tan (5) = e '(22) Thus, for small values of phase error, the quantity E, calculated by taking the volt-time areas, provides a good estimate of the phase error (in radians) under the given assumptions. This estimate of phase error can be used in a closed-loop feedback system to drive the PRG in synchronization with the line voltage. As mentioned above, the AC EQ5400 resistance welding control is a sampled data system in which the samples of the external continuous time signals are taken at discrete, fixed time intervals using an analog to digital converter. These samples are, by design, synchronized with the timing of the PRG and, in effect, a period of PRG is defined as the time required to obtain 128 of such samples in the preferred embodiment. A continuous time signal, x (t) is approximated in a system of data sampled by a sequence of discrete sample points, x (k) according to: »(*) - * MU (23) where Ts is the elemental sample period of the system - the DSP interruption interval in the case of resistance welding control of AC EQ5400. In what follows, the value of x (k) refers to the kth elementary sample of the entity x (t). For example, applying this to the observed voltage waveform of (11) gives the sequence: *) eV n (2 ./ftrt+*), * s °, l.- < 24 > As an example of such a sequence, be the parametric values in (24) those given in the table shown in Figure 16. This corresponds to the sampling of a waveform of 480 VRMS, 60 Hz to 128 samples per cycle of line. The corresponding samples are shown as a derivation graph in Figure 17. In the AC EQ5400 resistance welding control, the voltage is sampled at discrete intervals as described above and a trapezoidal approximation to the volt-time area integral It is done. If the number of samples taken by the digital voltmeter function in a period of internal PRG is Ns, then there are Ng / 4 samples taken on a quadrant. The estimated values of the volt-time area of quadrants 2 and 3, hereinafter denoted as VwcTA (q2) and VwcTA (q3) are generated using: Here, the index "j" refers to the jth sample of the voltage waveform (DSP interruption) within a PRG cycle as defined above. In a resistance welding application, in which large currents are extracted for short periods, the presence of line impedance corrupts the "shape" of the observed voltage, so that it is no longer sinusoidal. The following develops the current equation for an AC phase controller, such as a resistance welder and explores the effects of the line impedance on the observed sinusoid. The mathematical solution is developed in two parts. First, the current equation of a rigid excitation voltage source that drives a charge that has both reactive and inductive components is explored. Right away, The resistive and inductive line impedance elements are introduced in series between the excitation voltage source and the point at which the voltage is actually observed and the relationship between the excitation voltage and the actual voltage observed by the welding control are explored. Figure 18 shows an ideal circuit model for an AC phase control, such as a resistance welder, that drives an inductive load. An ideal voltage source, marked as VdP (t), provides the source voltage for the system. A switch, marked SW1, closes and opens on demand and represents the thyristors that form the solid state switching elements of the phase control. The load comprises a resistor, marked Rcarga and an inductor, marked Lcarga. The flowing current is marked as i (t) and the voltage applied to the load is marked as Vload (t). As before, in this first scenario, Vdp (t) is a sinusoidal voltage source of the form: (27) where ? is the frequency in radians of the sinusoid, related to the frequency in Hz by: ? -2p / (28) When a semiconductor switch such as a SCR is used as the switching device, a simple model for this device is a switch that closes at a commanded time t of the zero crossing of the sinusoidal voltage source. Once the switch is closed and the current begins to flow, it continues to flow until the current naturally extinguishes by itself, at which time the switch blocks the voltage. Under this condition, the current flowing in the circuit is given as a function of time by: The ** - sen. { ü) T- [M (/ - r) - «(/ - (r + T))] (29) where f is referred to as the "angle of delay", related are the resistance and inductance by: and T is the driving time, that is, the time elapsed from the trigger ti until the current naturally extends itself, expressed mathematically concise by: T-min (/ -¾-) (31) The function u (t) is the "unitary stage function" commonly known, mathematically defined by: The origin of equation (29) and its derivation will be discussed subsequently. In general, equation (29) can not be resolved in closed form by driving time, but iterative methods can be used to derive approximations. Equation (29) can be normalized to be independent of frequency and therefore independent of time. Is the trigger angle a, driving angle? and impedance Z charge of the phase control by: =? t (33) Y ^ úfT (34) and and let T be the angle of observation, that is, the angle after the zero crossing of the sinusoid. Then (29) it becomes: This is the "normalized" form of the phase control equation. Next, consider a more complex circuit model of the contaminated parameter system that forms the mathematical basis for the present invention. In this model, shown in Figure 19, the source of the welding energy is not assumed to be "rigid" as in the previous discussion, but contains three contaminated circuit elements, ie: the original "rigid" excitation voltage source VdP (t), identical to the previous one and a line resistance contaminated in series, marked line and contaminated line inductance marked Line inserted between the source of excitation voltage and the control of welding. This polluted parameter model of the power source combines the resistance of all sources between the assumed rigid voltage source and the input terminals of the welding control. It includes the winding resistance of the distribution transformer, the inductance of the transformer, the resistance and inductance of the power distribution system, such as wires, main distribution lines, switch contacts, etc. This line impedance can be significant with respect to the load impedance. In Figure 19, the voltage observed by the weld control is marked Vwc (t) and, under conditions in which the weld control is firing under the load, differs from Vdp (t) by virtue of the current flowing through Riínea and lamea- Referring to figure 19, several things are evident: both the line impedance and the load impedance are factors to determine the current of welding, i (t); when there is no current flowing and hence no voltage drop across the line impedance, the voltage observed by the welding control, Vwc (t), is equal to the source voltage, Vdp (t). However, when the current is flowing in the circuit, the voltage observed by the welding control is not that of the voltage source, Vdp (t), due to the voltage drop across the line resistance and inductance of the voltage. line. From analysis of the elementary circuit, you can write for the current (37) where R •, eq and L ', eq are in this case, the equivalent series resistance and inductance given by: (38) (39) and f, and? they are calculated according to the equations that describe the simple model of Figure 18, but using the previous equivalent values. The voltage Vwc (t), observed by the welding control, is related to the ideal voltage source modeled by VdP (t) by: The voltage observed by the voltmeter function of the welding control becomes quite complex and it is difficult to visualize the effect. However, Figure 21 shows the simulation results showing the effect of the line resistance and line inductance on the observed voltage for the parametric values of the circuit in Figure 19, provided in the table shown in Figure 20. simulation and presented graphs were generated using MATLAB, a package of commercially available programming elements appropriate for the task. Comparing the voltage waveform of the excitation voltage source of Figure 21 (upper) with the voltage waveform that would be observed by the function of voltmeter of the welding control in figure 21 (mean), the observed voltage waveform is a significantly distorted version of source voltage. Under load, the welding control can not directly observe the excitation voltage source, V < jP (t), because it is strictly a mathematical construction and as such there is no specific point at which to apply connections to measure voltage. Even if an appropriate point could be found in the power distribution system to monitor the actual source voltage, the monitor point would probably be located at some distance from the welding control and it is desirable to have the welding control a localized autonomous equity. The AC EQ5400 resistance welding control observes the voltage at the input terminals. The voltage distortion shown in Figure 21 limits the performance of an AC resistance welding control in two ways without the benefit of the present invention. The first limitation is that the application of the phase estimation method discussed in detail above to the distorted waveform of Figure 21 (mean) generates an incorrect estimate of the phase relative to the excitation voltage source. For the previous example, using the phase error estimation method provided above, it can be shown that if the phase reference generator was originally "locked" on the line voltage source Vdp (t) (the term "locked" is quoted zero phase error generated before welding), applying the same method to the observed welding control voltage Vwc (t) of Figure 21 (average ) As long as it is released, the phase error estimator gives a phase error of approximately -7.7 degrees. If the PRG is allowed to react to this estimated error as long as it is soldered, the system timing will be incorrect and the system will generate the incorrect trigger points so that the thyristors obtain a target welding current. Even if the closed loop control is used to modify the trigger points to obtain a constant current, the reaction to the phase error generated above would cause at least one alteration in the welding current. Since resistance welds are commonly short (in the order of ten total line cycles), such alteration could have an effect on the welding metallurgy. The second limitation is that the RMS voltage measured by the welding control in Figure 21 is less than that of the excitation voltage source model Vdp (t). In the given example, while the RMS value of the voltage source is 480 Volts, the RMS voltage of the waveform in Figure 21 (average) is 453 volts. That is, the waveform that is observed directly by the welding control. One aspect of some prior art welding controls is the ability to automatically compensate for variations in the observed voltage, trying to keep the current constant. From the above development of the welding current equation of a system with line resistance and reactance, it is clear that the current delivered for a given tripping point of the thyristor is dependent on the excitation voltage and the equivalent contaminated resistance and inductance, which include the load and line values. Thus, using the observed line voltage (which differs from the excitation voltage when the current is flowing) as the basis for voltage compensation presents a limitation to welding control performance. Conversely, the ability to use the estimated excitation voltage described in the present invention as the basis for line voltage compensation provides a significant improvement in this regard. The effectiveness of a welding control based on the circuit model of Figure 19 to generate appropriate thyristor trip points (timing) is dependent on the accuracy of which the PRG can estimate the relative phase error between itself and the mathematical model of voltage source of impulse point. As discussed, the same act of conducting current in a resistance weld distorts the voltage waveform observed by the weld control and the application directly of the method discussed above to the observed voltage will cause errors in the timing of the firing of the thyristors. Assume, however, that the parametric values of line resistance and line reactance (inductance) can be estimated. If this is so, then from equation (40) and an observation of the welding control voltage Vwc (t) at the input of the welding control, the load current i (t) and the charge current derivative, di (t) / dt, an estimate value of the ideal open-circuit voltage source, V * dp (t), can be made, using: Applying the above mathematics to estimate the voltage source V * dp (t) and subsequently using this estimated voltage to calculate the phase error in the PRG must provide a more accurate timing of the PRG and hence the trigger points of the thyristors and would further facilitate the use of the model of Figure 19 in a forward feed control scheme. Thus, an element of the present invention is a means for estimating the line resistance and line reactance of the power distribution system. To proceed in the development of mathematics, we can solve equation (40) for VdP (t) to obtain: w = ^ (+ * ww + (¾ Note that this relationship is independent of the values of the load impedance elements, Rload and Load-As discussed above, the weld control includes a digital voltage sampling function (analog-to-digital converter) that can estimate (measure) Vwc (t), a discrete intervals and a digital current sampling function that can similarly estimate the value of i (t) at discrete intervals. If the Line and Line values can be estimated, equation (42) indicates that the instantaneous excitation voltage, Vdp (t) can also be estimated. As stated previously, the EQ5400 AC resistance welding control operates as a sampled data system, sampling the representative voltage and current signals at discrete intervals, to the sequence of points (tk), defined by: tk = kTs in where Ts is the interval of elementary sampling. Applying this to equation (42) produces a sequence of points, Vdp (k), with the kth sample in the sequence given by: From now on in the present, it will be understood that whenever the index "k" appears, the corresponding time of the sample is t = kT, k = 0, l, 2, ... s. With this understanding, the nomenclature in equation (43) above is Simplified to produce: Welding control provides sampling functions that provide estimates of the voltage sequence Vwc (k) and the current i (k), but not the derivative sequence di (k) / dt at each point. However, an approximation to the derivative sequence can be made by defining the first difference backwards ?? (k): and approaching the derivative using: substituting (46) to (44) gives: Now, Xieq is defined by: ¾ where Ts is the known sample period of the system. Substituting this gives: »V (*) = VL (*) + i? Aj (*) + jr < lfAi (*) (** o.v »(49) some methods to estimate the constant values The assumptions of Riínea and Xieq are now explored. To carry out this, the development will begin with a general procedure and preferred method detached. Examining equation (49), a given sample, k, there are three quantities that can be "known" to the system via measurements, ie 1) Vwc (k) that can be measured using the digital voltmeter function, 2) i (k), which can also be measured using the digital current meter function and 3) ?? (k) that can be calculated from a knowledge of i (k) and i (k-l) according to equation (45). There are also three unknowns in the equation, namely Vdp (k), line and Xieq. None of these are directly observable when the current is flowing and the sequence Vdp (k) is not necessarily constant. There are several ways in which one can proceed to generate an estimating value of line Y Xieq / but in each case some assumptions must be made regarding the nature of VdP (k) that is not directly observable either. A possible method to estimate the constant values of Riínea Y Xieq is to suppose that the system has obtained observations of the measurable quantities in sample times other than kO, kl and k2 (not necessarily in monotonic incremented order) and assuming that there is a mathematical relationship known constant between the values of Vdp (kl), Vdp (k2) and Vdp (k3) that can be expressed as: where ?? and M2 are known constants. With this established, you can write the following matrix equation for the three samples: which is of the form V - A * U (52) where V is the matrix of measured voltage points: U is the matrix of unobservable quantities (two of which, Riínea and Xieq are the object of this estimate): and A is a matrix of observable and known quantities related to V and U according to (51): If the matrix A is non-singular, the mathematical inverse of A exists and can be solved (51) to obtain: and thus obtain an estimated value of Riine and Xieq- Equation (56) will also produce the value of Vdp (kO), but the most important amounts of the present invention are the line resistance and reactance. An interesting variation in this method is to suppose that the sequence Vdp (k) is periodic in k with an integer period Ns, in such a way that: For values of p in the set of natural numbers, this is. { 1,2, ....}. . This is interesting from the perspective of the present invention because 1) it is already assumed that the excitation voltage is periodic and 2) as already discussed before a period of PRG comprises Ns samples (DSP interruptions). Thus, if the PRG is already synchronized with the excitation voltage this periodic relationship exists and known If kO, kl and k2 are related by With pl and p2 both numbers noticed, then of (57) this produces ?? = 1 and M2 = 1 in equation (56). Practically, this method implies that the samples are taken in the same relative "place" in different PRG cycles. Of course, being able to adjust ?? and M2 = 1 in equation (56) does not guarantee that the matrix is non-singular and can be inverted, so that this method may not work in a general case. In particular, if the system employing such a method is operating in the "steady state", so that the current and current difference taken at each sample point, the matrix will definitely be singular and the method will not produce estimated values. useful of Runea and To explore a different and more practical means to estimate Riínea and Xi.eq / equation (49) is rewritten in the form: (59) Now, you can write in matrix form for the three data samples: The significant simplification can be done in the previous mathematics if it is assumed that during one of the samples, ie kO, the current and current difference are both zero. If this is the case, from equation (60), you can write directly. and if (57) still applies, you can write (62) ? . (* 0) -. (* 2)] [i (k2) ?? (* 2) Which can be solved for line reactance resistance; This also assumes that the current and current difference matrix is non-singular, but it is only a 2x2 matrix. The assumption that a line cycle can be found in which the current does not flow and has not been flowing (such that the current and difference of current are both zero at point kl) is a reasonable one in a resistance welding application in which the application of welding current is normally preceded by a period in which the current does not flow while the welding "tips" mechanics drive the metal to be joined together. In addition, once the current begins to flow, it can be reasonably certain that the current flowing in the first cycle of the welding line will differ from subsequent line cycles of current because this metal pulse is not normally together perfectly and the Stable state will not be reached until the metal really begins to melt. To continue with the evaluation, it is assumed that the samples can be taken in a PRG cycle in which the current is known to be not flowing and in other PRG cycles in which it is known that the current is flowing, there is no need to restrict all samples by equation (57), provided that the samples can be taken in pairs (ka, kb), so that (64) In particular, it is assumed that there are two pairs of data points ( k0i, ki) and (k02, k2), in such a way that: Y Furthermore, k0i and k02 are samples taken from cycles of PRG in which the current is not flowing and ki and k2 are taken from cycles of PRG in which the current is flowing and also suppose that (57) is applied for each pair ( k0i, ki) and (k02 and k2). Then you can write by inspection: assuming again that the matrix inverse in (67) exists. This method allows (but does not require) the estimation of Riínea and Xieq to be made from different DSP samples within two line cycles, one in which the current is not flowing and one in which the current flows. Allowing this greatly improves the probability that the inverse matrix in (67) will exist. In a factory environment, the magnitude of the actual excitation voltage does not change over time and such a change is a factor that can affect the accuracy of the line resistance and line reactance estimates. The farther in time the line cycles are chosen in the above discussion and the more likely the excitation voltage magnitude will differ significantly. By Accordingly, in the preferred embodiment of the invention disclosed herein, adjacent line cycles are chosen in such a manner that the line cycle in which the current flows and is measured is adjacent to a sequence of line cycles in which the current has not been flowing for a substantial number of line cycles. It is understood in the following that this particular embodiment does not limit the utility of the invention and in particular, one can easily contemplate a mode in which the line resistance and line reactance are calculated using a sequence in which the current is flowing in a particular line cycle and does not flow in a subsequent line cycle. The embodiment of the invention disclosed herein is preferred because if the current has not been flowing through a significant number of line cycles before driving current, the PRG must be synchronized exactly with the excitation voltage when the current starts to flow. Because there is a natural delay in response to a line cycle in the disclosed PRG implementation, the current samples taken from the first line cycle at which the current flows after a long interval at which the current is not flowing It can not affect the PRG until the measurements are taken. This is the ideal condition in which samples can be obtained. Proceeding again, the following are made suppositions: (1) the system has not been for a period of time, such that the observed welding control voltage, Vwc (t) is identical to that of the voltage source voltage, Vdp (t), that is. (68) and (2) between the period of any two line cycles, the modulation term of the excitation voltage, Vm (t) is constant and can be represented as: like before. Consider two sample points taken exactly one period apart under these conditions: one in which the welding current is not flowing and another, exactly a separate PRG period in which the current flows. Recall again from the above that there are Ng samples (DSP interruptions) per PRG period. Under the previous assumptions, you can write: Applying this to equation (49) you can write: Vw (k-N,) - Vm n = 0.1, ·· * (71) for the particular case in which the current does not flow during a line cycle and does not flow in the subsequent line cycle. If two sets of samples of adjacent line cycles can be selected, ie in the samples kl and k2 (kl not equal to k2) in which the current and current difference values are not zeros and are distinctly different from each other, it can be written in the form of a matrix: which can be resolved in the form of a matrix to obtain: provided that the inverse matrix is non-singular. Equation (73) provides a means in which the line impedance parameters could be estimated. One potential limitation with the use of individual points to perform the estimated values of line impedance parameters is that the signals observed are generally "noisy", especially in a factory environment where there is a lot of on and off control and power circuits and other switching elements. The calculated values of line resistance and line reactance are sensitive to the actual values of current and voltage used in equation (73). Now a more robust means to estimate the parameters is presented. As summarized above, the system generates for each quadrant the VTA with trapezoidal integration used to give the estimated quadrant value. It is well known in the study of stochastic processes that if the signals are corrupted by uncorrelated mean zero noise, taking the advantage over a sum of many samples reduces the variance of the estimated value. The volt-time area, current-time area, and current-difference area can be used to calculate such an estimate value. For a general sequence x (k), define the general "X-time area", XTA (q, n) of x (k) on quadrant q, q = ql, q2, q3, q4, and cycle PRG line n by: where j is the index of the sequence x (k) but indexed from the beginning of the PRG cycle, that is, j = 0 corresponds to the transition from q4 to ql of the PRG 10 function. With this definition, the area of volts-estimated time of the welding voltage observed on quadrant 1, VwcTA (q, n) is which is exactly the sum used to calculate the volt-time area of the quadrants used in the PRG 10 function. Now, exactly analogously, is defined VdpTA (q, n), ITA (q, n) and ?? ?? (q, n) by: Next, note that equation (49) is a linear equation that, for each sample n, relates the excitation voltage sample Vdp (k) to the observed weld voltage sample, Vwc (k), current sample i (k) ) and first current difference Ai (k). Since it is a linear relationship, the relation also applies equally to the quantities XTA (q): with line and Xieq supposed constant parameters. Selecting q2 and q3 as the quadrants to be used to estimate the parameters, we obtain (in the form of a matrix): where the nomenclature R * line and X * ieq refers to the estimated values of the resistance and inductance of the power distribution system respectively and the indices (q2, n) and (q3, n) mean the estimates of quadrant 2 and 3 of the current line cycle in which the current is flowing and (q2, nl) and (q3, nl) designate quadrants 2 and 3 of the previous line cycle, in which the current is not flowing. Again, the estimated parameters can be solved to obtain: (81) This important result is the method used in estimating the line impedance parameter in the EQ5400 AC resistance welding control to calculate the R * line (m) and X * ieq (m) values in Figure 8 above. A closed-form solution to the welding current fed by an AC resistance welding control is now developed using Laplace transform techniques. The analysis involves a source of rigid excitation voltage and ideal thyristor switches. The results are presented both as a function of time as well as an observation angle. The conditions that determine the time or conduction angle of the thyristor as a function of the firing point and load impedance are also presented. Figure 22 is a simplified polluted parameter circuit model for a resistance welding controller and associated power distribution system and welding load, which will be used to derive the mathematics of the welding controller. The contaminated parameter model comprises a welding power source 11, the welding controller 20 and the welding load impedance 30. The welding power source 11 is modeled as two circuit elements, a voltage source Vs (t ) 12, which is supposed to be an ideal voltage source that does not have series impedance and a contaminated line impedance connected in series, line / which is assumed to be ideal and linear and which generates a voltage drop between the ideal voltage source and the welding control proportional to the welding charge current. The welding timer 20 is able to observe the charging current I load via a current transformer 24 and the applied voltage at its input terminals, Vwc (t). Using solid state tirisitor switches 22, the welding timer generates a welding voltage V load (t) at its output terminals, by a corresponding welding current I load (t). The welding load impedance 44 comprises the welding transformer 20, workpiece, tooling 22, accessories and other sources of impedance. To simplify the mathematics, the impedance of all these elements are grouped in a single amount of impedance reflected in the output terminals of the welding control as Zcarga. When the welding control applies the voltage V load (t) on the load impedance, the resulting current is I load (t). In what follows, it is assumed that the line impedance Line is zero and it is considered that the voltage source Vs (t) is an ideal source of the form: where V is the magnitude of the line voltage and f is the line frequency (in Hz) of the line voltage source. This sinusoidal waveform as a function of time is shown in Figure 23 (upper part). Note that the zero crossings of this waveform occur at points for which the following holds: To remove the dependence on frequency, the timing in the resistance welding application is usually expressed as angles instead of time. In this analysis, the observation angle (corresponding to time) is designated as T. Figure 23 (background) shows the voltage waveform as a function of the observation angle, with zero degrees referring to a cross from zero to negative of the sinusoid. Note that in this case, the zero crossings of the sinusoid were in the angles: 0 = 18? * ?, «= 0.1, ··· (84) It is assumed that the thyristor switches are ideal switches that do not have any voltage drop. The load impedance, reflected to the primary side of the welding transformer, can be reasonably modeled as an accumulated load resistance, R load Y a load inductance in series, Load as shown in Fig. 24.

The effect of firing the solid state thyristor welding contactor is to close the switch in Fig. 24 at a time t = x (or at an angle a) with respect to the zero crossing of the voltage source as shown in Fig. 23 Figure 25 shows the voltage waveform resulting from the tripping of the thyristor. Once the switch is thrown and the current begins to flow in the load, the switch remains closed until the current is again zero at a time t = t + tcond as shown in figure 25 (top) or at an angle? = +? as shown in figure 25 (background). The real value of tcond or? It is dependent on the trigger point and the load circuit parameters and will be derived in the present. Mathematically, the voltage applied to the load is of the form: where u (t) is the unit stage function. The purpose of this analysis is to develop the closed-form solution for the welding current resulting from the tripping of the thyristor switch at time t with respect to the zero crossing of source voltage vs (t) as given in (82) above and shown in Figure 23. Additionally, the current waveform will be developed which is a function of the observation angle, T as described in figure 23 (background). Another important amount is the driving time resulting, tcond or its equivalent conduction angle,?, which is defined as the angle over which the thyristor conducts or alternatively, the angle over which the current flows as a result of firing the thyristor. The following assumptions are made to simplify the analysis of the welding current: 1. It is assumed that the voltage source, vs (t) is ideal and hence "rigid". There is no line impedance. 2. The frequency of the voltage source remains constant. 3. It is assumed that the thyristor switches are ideal, they do not have voltage drop. Once fired, a thyristor conducts until the current flowing through it is exactly zero. 4. The load impedance, which comprises a load resistance and load inductance, reflected to the primary, is assumed constant throughout the weld. This results in a linear system, not variant in time. Under these assumptions, the solution in closed form to the charging current ICarga (t) resulting from the tripping of the thyristor at time t with respect to the zero crossing of the sinusoidal input voltage is: (86) where V is the magnitude of the sinusoidal input voltage. R is the resistance of the welding transformer, gun and tooling reflected to the primary of the welding transformer; L is the inductance of the welding transformer, gun and tooling reflected to the primary of the welding transformer; co is the frequency in radians of the line voltage source; f is the delay angle of the load impedance, defined by: ú) L P-tan? (87) and t is the time in which the thyristor is fired in relation to the zero crossing of the line voltage as shown in Fig. 25. Expressed in terms of the observation angle T, the load current i (T) is: e-a) (88) where: T is the observation angle, measured from the negative to positive zero crossing of the sinusoidal voltage source; f is the delay angle of the load impedance as given by equation (87) above; a is the firing angle, related to t by and | Zcarga | is the magnitude of the impedance given by: The driving time, tcond and analogous driving angle,? are those values for which the following holds: y = min ($ -a) (92) Assuming a rigid welding source allows a simple presentation of the voltage waveform presented to the load. Referring to Fig. 22, when there is no line impedance present, the voltage Vwc observed by the weld control is identical to that of the voltage source, Vs. If line impedance is present, the voltage of line observed by the welding control, Vwc will be reduced from that of Vs by the current flowing through the line impedance. For purposes of analyzing the effect of the line impedance on the welding current, the line impedance and load impedance can be easily grouped into a single entity. Assuming that the line impedance is also inductive in nature (ignoring the capacitance of the distribution system), the equivalent resistance and inductance can be defined by: (93) and If these values are substituted for the various previous equations, the resulting current would be an accurate estimate of what is actually transpiring in the weld control. A line frequency in radians fixed? it is required to make the assumption that the system is linear and invariant in time. Without this assumption, the use of Laplace transform techniques would not be possible. Fortunately, this assumption is made to a very high degree in application. An ideal thyristor is assumed for simplicity. A A model of a thyristor comprising a fixed voltage drop or any linear model for the tirisitor could also have been employed. If a model incorporating a fixed voltage drop is used, it would be modeled as a DC voltage source. In a linear system model, the resulting weld current could be expressed as the superposition of the response to the sinusoid, as expressed in the above equations and a DC voltage source printed on the system at the time of firing. A constant load impedance is required to allow the analysis of the grouped parameter model as an invariant linear time system. The inductance is determined mainly by the geometry of the tool and the work piece and as such can change as the geometry of the tools change. An example of this is that leads and cables have a tendency to "jump" at the start of a weld. The resistance is usually very constant in the course of a half cycle. Caution must be exercised that during the exclusion, a phenomenon in which molten metal is expelled from welding tips and is usually observed as the sparks of sparks emanating from the weld tips when too much heat is applied, the resistance can change very rapidly . In this case, the shape of the welding current will probably not follow the previous equations either.

The basic shape of the welding current can be derived as discussed below. Writing the loop equation for the circuit of Figure 24 gives: Taking the Laplace transform of the equation (0-67) gives O Vca ^) ^ ^ - [ssen (T) + cos. { to} )] (97) From figure 24, you can write ¾ar, a. { s) = I (s) (Itcara-i-sLcar, a) (98) which, when solved for I (s) results '? R' canja 4s "" L-load (99) To obtain the Laplace transform of the charge current, equation (99) is multiplied by equation (97) to obtain: See '1 (100) which can be written in the form: - (jr) [jsén (fi> r) + cos (< m-)] (101) "fall with F (s) given by: (102) Now, notice that the following properties of the Laplace transform: 1. The term e "st implies a time delay, that is: 2. The Laplace transform of the derivative of a function is of the form: ^} = * 4 / < < > } - / < or > (104) Examining equation (101) in light of (1039 and (104), if the inverse Laplace transform of F (s) is f (t), the load current i (t) can be written as: Thus, if f (t) can be found from (102), equation (105) shows how to derive the welding current. F (s) can be expanded to a partial fraction representation of the formula: (106) Multiplying cross-wise and gathering the terms in (106) results in: (107) Equation (107) is a polynomial in "s". To satisfy (107) in all values of s, the coefficients of each term of the polynomial must be zero. This gives the following relationships between a, b and c: a + b = 0 (108) Solving for "a" in (106) da: (111) From (108), "b" is found to be: Solving (109) for "c" produces Substituting (111) and simplifying it has as result • ^ load Substituting (111), (112) and (114) back to (106) gives: Taking the inverse Laplace transform of (115) gives: Taking the derivative of (116) da (? 7) Substituting (116) and (117) in (105) gives: (118) Rearranging the terms given: Two trigonometric identities that can be used to simplify (119) are: (Á) C0S (B) ± COs (Á) sin (B). (120) CO $. { A ± B) = cos (A) c s (B)? sen (A) .sen (5) (121) Applying these identities to (119) results in (122) A fundamental concept of the AC circuit analysis is that of the delay angle of an R-L circuit, denoted by f and defined as: ^ =? 3?, () (123) of which the following relationships can be written: cos () =. (125) J /? 2 + (ftlL) - * To facilitate the use of these relationships, first multiply through (122) by the amount L / L = l and the terms are re-arranged to give: Now, applying (124) and (125) produces Applying (120) to (127) da (12S) Equation (128) is the normal way for the welding current equation as a function of time for parametric values of the trip time, t, with respect to the zero crossing of the line voltage, the line frequency in radians? and the equivalent load resistance R and load inductance L reflected to the primary of the welding transformer. The point at which the tirisitor switch is triggered is usually expressed in terms of a firing angle,, instead of a firing time. The firing angle,, is related to the firing time, t and the line frequency in radians? by: a =? t (129) Similarly, the angle of observation can be defined, T by 0 = Wt (130) With these two quantities defined, you can rewrite the exponential (128) as g charge - g ** Hload (131) Applying (123), (130) and (129) to (131) gives /? load (i-r) | • load (132) Also, the magnitude of the AC load impedance of the R-L circuit is recognized as: (133) Substituting (133), (132), (129) and (130) to (128) gives: as an expression of the welding current in terms of the firing angle, a, delay angle of the circuit, f and observation angle T. Figure 26 is a graph of the current waveform resulting from the application of the parametric values shown in Figure 27 to Equation (134). Once the thyristor trips and the current begins to conduct, the thyristor continues to conduct current until the current naturally extinguishes by itself at a zero crossing. Using equation (128), the time in which the thyristor shuts off satisfies: where i (t) is given by (128) above. The equation (135) is the mathematically rigorous statement that the conduction time is the interval between the trip of the thyristor (at t = t), and the first time that the welding current passes again through zero. There is no closed form solution for tcond, but the equation (128) it can be resolved iteratively to a high degree of precision. Similarly, the conduction angle,?, Is that angle that satisfies: ? = rain (? -) (136) A closed-form solution for the welding current can be found by assuming a linear cumulative parameter model of the welding circuit. While the analysis presented here makes many major assumptions, some of which may be considered suspect in a real welding application, the results presented have generally been accepted as "the solution" for welding current and have been repeatedly referred to in the literature. A more accurate modeling of the system can be easily obtained by incorporating a model for the source impedance presented by the welding voltage source and the effects of the thyristor can also be easily explored by assuming linear models for each. While the specific embodiments have been illustrated and numerous modifications described come to mind without significantly deviating from the spirit of the invention and the scope of protection is only limited by the scope of the appended claims.

Claims (41)

1. CLAIMS 1. A phase reference generator for tracking the excitation voltage of a power distribution system for use in a resistance welding control, characterized in that it comprises: a digital signal processor configured to include: an area generator of volts-digital time to generate a volt-time area of an observed voltage; a current-time area generator and digital current-difference-time generator to generate a current-time area of an observed current and time-difference-time area of the observed current; a line impedance estimator; and, an excitation voltage area estimator configured to receive values from the digital volt-time area generator, the digital time-current area generator and the current-difference-time area generator and the line impedance estimator. and generates estimated values of the excitation voltage.
2. 2. The phase reference generator according to claim 1, characterized in that it further comprises an analog to digital converter to convert each of the observed voltage and the observed current from a signal analog signal to a digital signal.
3. 3. The phase reference generator according to claim 2, characterized in that it further comprises an interval timer, wherein the interval timer triggers an analogous to digital conversion of the observed voltage and the observed current.
4. The phase reference generator according to claim 3, characterized in that it further comprises a phase error estimator configured to estimate the phase difference between the estimated excitation voltage and a timing cycle generated by the reference generator of phase.
5. 5. The phase reference generator according to claim 4, characterized in that the phase error estimator is implemented in fixed elements of the digital signal processor once for each cycle of timing generated by the phase reference generator.
6. 6. The phase reference generator according to claim 4, characterized in that it further comprises a compensator configured to adjust the frequency of the timing cycle to move the timing cycle toward a synchronous phase with the estimated excitation voltage.
7. 7. The phase reference generator according to claim 6, characterized in that the compensator increases the frequency of the timing cycle when the timing cycle is delayed to the excitation voltage. estimated and decreases the frequency of the timing cycle when the timing cycle is ahead of the estimated excitation voltage.
8. The phase reference generator according to claim 4, characterized in that it further comprises a quadrant generator configured to provide an indication of a current quadrant of the timing cycle.
9. 9. The phase reference generator according to claim 1, characterized in that it further comprises an output to provide a signal for firing a welder by resistance.
10. 10. A welding control for a resistance welding system, characterized in that it comprises: a phase reference generator configured to provide an estimated excitation voltage of a supplied voltage and generate a signal to trigger a thyristor of the welding system during a welding operation; a voltmeter coupled to the phase reference generator and an input line to provide sampled values of the input line voltage; and, a current meter coupled to the phase reference generator and the input line to provide sampled values of the line current.
11. 11. The welding control in accordance with the claim 10, characterized in that the phase reference generator comprises: a digital signal processor configured to include a digital volt-time area generator, a current-time area generator and digital current-difference-time area generator, a impedance estimator and a volt-area estimator of the excitation voltage.
12. 12. The welding control according to claim 11, characterized in that the digital volt-time area generator generates an estimated value of the input line voltage based on the sampled values of the input line voltage.
13. 13. The welding control according to claim 12, characterized in that the current-time area generator and the digital current-difference-time generator generate an estimated value of the line current and the difference of the line current of the line. the sampled values of the line current.
14. 14. The welding control according to claim 13, characterized in that the digital signal processor further includes a line impedance estimator configured to generate a line resistance and a line reactance based on the estimated line voltage of the line. input and the estimated value of the line current and the difference of the line current.
15. 15. The welding control according to claim 14, characterized in that the digital signal processor further includes an estimator of the impulse point volt-time area configured to provide an estimated value of the impulse point volt-time area in the estimated value of the input line voltage, the estimated value of the line current and the difference of line current, line resistance and line reactance.
16. 16. The welding control according to claim 15, characterized in that the digital signal processor further includes a quadrant generator to provide a timing cycle of the phase reference generator having a frequency.
17. 17. The welding control according to claim 16, characterized in that the digital signal processor further includes a phase error estimator for estimating the phase error between the excitation voltage and the timing cycle.
18. 18. The welding control according to claim 17, characterized in that the digital signal processor further includes a compensator for adjusting the frequency of the timing cycle to bring the timing cycle in synchronization with the driving voltage.
19. 19. A digital phase reference generator for use in a welding control, characterized in that it comprises: an interval timer configured to trigger an analog-to-digital conversion of a sampled input line voltage and an input line current sampled on a recurring basis; a digital signal processor configured to execute an interrupt routine initiated by each consummation of the analog-to-digital conversion of a sampled input line voltage and a sampled input line current where a predetermined number of interrupt routines defines a cycle of timing, the digital signal processor is further configured to generate an estimated value of the volt-time area of the input line voltage, an estimated value of the current-time area of the input line current and an estimated value of the current-difference-time area of the input line current and an estimated value of the line impedance.
20. The digital phase reference generator according to claim 19, characterized in that the digital signal processor is further configured to provide an estimated value of volt-area driving point of the input line voltage.
21. 21. A method for estimating an excitation voltage of a resistance welding system, characterized in that it comprises the steps of: periodically sampling a supplied voltage and a current supplied from a system to obtain sets of a sampled voltage value and a sampled current value; take a first set of a sampled voltage value and a sampled current value; take a second set of a sampled voltage value and a sampled current value; take a third set of a sampled voltage value and a sampled current value; calculate a current difference value for each of the first set, second set and third set, and create an estimated line resistance and an estimated line reactance of the system based on the first set of a sampled voltage value, a value of sampled current and calculated current difference value, the second set of a sampled voltage value, a sampled current value and calculated current difference value and the third set of a sampled voltage value, a sampled current value and value of calculated current difference.
22. The method according to claim 21, characterized in that the step of taking a first set of a sampled voltage value and a current value Sampling comprises: determining if the current is one that flows or does not flow, and taking voltage samples when the current is not flowing.
23. The method according to claim 21, characterized in that it further comprises the steps of: creating a volt-time area of the sampled voltage; create a current-time area of the sampled stream; and, create a current-difference-time area of the sampled current, using the volt-time area of the sampled voltage, the current-time area of the sampled current, the current-difference-time area of the sampled current , the estimated line resistance and the estimated line reactance to create an estimated impulse point voltage-time area.
24. The method according to claim 23, characterized in that it further comprises the step of: using the estimated impulse point voltage-time area to drive the firing of a thyristor of a resistance welding device.
25. 25. The method according to claim 23, characterized in that the steps of creating an area of Volt-time of the sampled voltage, create a current-time area of the sampled current and create a current-time-difference area of the sampled current is done on a quadrant quadrant basis.
26. 26. The method of compliance with the claim 25, characterized in that the step of periodically sampling a supplied voltage and a supplied current from a system comprises taking samples of supplied voltage and current supplied an established number of times per quadrant.
27. The method according to claim 23, characterized in that it further comprises the step of: using the estimated impulse point voltage-time area to calculate a phase error between the supplied voltage and an internal phase reference.
28. The method according to claim 27, characterized in that it further comprises the step of: using the phase error calculated in the step of: using the volt-time area of the sampled voltage, the current-time area of the current sampled, the current-difference-time area of the sampled current, the estimated line resistance, and the estimated line reactance to create an estimated impulse-point voltage area.
29. 29. A system for estimating an excitation voltage of a resistance welding control, characterized in that it comprises: circuits for periodically sampling a supplied voltage and a supplied current of a system to obtain a plurality of sets of a sampled voltage value and a sampled current value; circuits to create a volt-time area of the sampled voltage; circuits to create a current-time area of the sampled current; circuits to create a current-difference-time area of the sampled current; circuits to determine if current is one that flows or does not flow; circuits to take a first set of a sampled voltage value and a sampled current value when the current is not flowing; circuits to take a second set of a sampled voltage value and a sampled current value when the current is flowing; and, circuits to create an estimated line resistance and an estimated line reactance of the system based on the first set of a sampled voltage value and a sampled current value and the second set of a sampled voltage value and a current value sampled
30. 30. The system according to claim 29, characterized in that it also comprises: circuits for using the volt-time area of the sampled voltage, the current-time area of the sampled current, the current-difference-time area of the sampled current , the estimated line resistance and the estimated line reactance to create an estimated impulse point voltage-time area.
31. 31. The system according to claim 30, characterized in that it further comprises: circuits for using the estimated impulse point voltage-time area to drive the firing of a thyristor of a resistance welding device.
32. 32. The system according to claim 30, characterized in that the system comprises a digital signal processor.
33. The system according to claim 29, characterized in that the circuits to create a volt-time area of the sampled voltage, create a current-time area of the sampled current and create a current-time-difference-area of the Sampled current comprises circuits to effect the creation of a volt-time area of the sampled voltage, create a current-time area of the sampled current and create a current-time-difference area of the current sampled in a dial quadrant base.
34. 34. The system according to claim 32, characterized in that the circuits for periodically sampling a supplied voltage and a supplied current of a system comprise circuits for sampling voltage supplied and the current supplied an established number of times for each quadrant. .
35. 35. A method for estimating the excitation voltage for timing the firing elements of a resistance welding device, characterized in that it comprises the steps of: measuring a supplied voltage and a supplied current of a power distribution system to a plurality of predetermined intervals; estimate a line resistance and a line reactance based on the measured values of the supplied voltage and the current supplied; estimate the excitation voltage based on the measured values of the supplied voltage and the current supplied and the line resistance and line reactance estimated.
36. 36. The method according to claim 35, characterized in that it further comprises the steps of: calculating a voltage-time area of the supplied voltage from the measured values of the voltage supplied; calculating a current-time area of the supplied current of the measured values of the supplied current; and, calculate a current-time-difference area of the supplied current from the measured values of the supplied current, where the voltage-time area, the current-time area and the current-time-difference area they are used to estimate the excitation voltage.
37. 37. The method according to the claim 35, characterized in that the step of estimating a line resistance and a line reactance comprises the steps of: measuring a first set of a sampled voltage value and a sampled current value when the current is not flowing; measuring a second set of a sampled voltage value and a sampled current value when the current is flowing; and, creating an estimated line resistance and an estimated line reactance of the system based on the first set of a sampled voltage value and a sampled current value and the second set of a sampled voltage value and a sampled current value.
38. 38. The method according to claim 37, characterized in that it also comprises the step of: determining whether the current is one that flows or does not flow for each of the plurality of predetermined intervals.
39. 39. The method according to claim 38, characterized in that it further comprises the step of: providing a trigger signal to a thyristor of a resistance welding device based on the estimated excitation voltage.
40. 40. The method according to claim 35, characterized in that it further comprises the step of: estimating a phase error between the supplied voltage and the estimated excitation voltage.
41. 41. The method according to claim 40, characterized in that it further comprises the step of: using the phase error estimated as feedback for additional calculations of the estimated excitation voltage.