KR20080082820A - Organic light emitting diode display and driving method thereof - Google Patents

Abstract

An OLED display device and a method for driving the same are provided to enhance the image quality and reliability of the image quality by processing a difference voltage between gate and source voltages of a driving transistor as data voltage. Plural data lines supply data voltages. Plural gate line pairs include first and second gate lines for supplying first and second scan pulses having opposing phase each other. A high voltage source(VDD) supplies a high driving voltage. A base voltage source supplies a base voltage. An OLED(Organic Light Emitting Diode)(OLED) is illuminated by a current between the high voltage source and the base voltage. A driving element(DR) controls a current flowing in the OLED according to a gate-source voltage. A storage capacitor(Cst) is implemented between first and second nodes. A switch circuit adjusts a voltage of the first node by turning on a current path between a source electrode of the driving element and the second node using a voltage which a source voltage of the driving element is added to the data voltage.

Description

Organic Light Emitting Diode Display And Driving Method Thereof}

1 is a diagram illustrating a light emission principle of a general organic light emitting diode display.

Fig. 2 is a circuit diagram equivalently showing one pixel in a conventional active matrix organic light emitting diode display.

3 is a graph illustrating current-voltage characteristics of a general organic light emitting diode.

4 is a graph illustrating a change in driving current according to a change in saturation current of a conventional organic light emitting diode.

5 is a graph illustrating a change in driving current according to a change in a conventional high potential driving voltage.

6 is a block diagram illustrating an organic light emitting diode display device according to an exemplary embodiment of the present invention.

7 is a timing diagram of a driving signal supplied to the pixels of FIG. 6.

8 is an equivalent circuit diagram of a pixel included in an organic light emitting diode display according to a first exemplary embodiment of the present invention.

9 is an equivalent circuit diagram of a pixel 122 for the address period A of FIG.

FIG. 10 is an equivalent circuit diagram of a pixel 122 for the light emitting period B of FIG.

FIG. 11 shows the voltage Vg (Vst +) applied to the first node n1 and the voltage Vst− applied to the second node n2 in the address period A and the light emission period B of FIG. And a simulation result showing the transient state of the source voltage Vs (Voled) of the driving TFT DR, the voltage Vst stored in the storage capacitor Cst, and the driving current Ioled.

12A and 12B are graphs for explaining that even when the saturation current Is of the organic light emitting diode is changed, the difference voltage Vgs and the driving current Ioled of the gate voltage and the source voltage of the driving TFT DR are not affected. .

13A and 13B are graphs for explaining that even when the high potential driving voltage VDD is changed, the difference voltage Vgs and the driving current Ioled of the gate voltage and the source voltage of the driving TFT DR are not affected.

14 is a block diagram illustrating an organic light emitting diode display according to a second exemplary embodiment of the present invention.

FIG. 15 is an equivalent circuit diagram illustrating a pixel included in an organic light emitting diode display according to a second exemplary embodiment of the present invention. FIG.

FIG. 16 is an equivalent circuit diagram of a pixel 222 for the address period A of FIG.

FIG. 17 is an equivalent circuit diagram of a pixel 222 for the light emitting period B of FIG.

<Description of Symbols for Main Parts of Drawings>

116: display panel 118: gate driving circuit

120: data driving circuit 122,222: pixels

124: timing controller 130, 230: organic light emitting diode driving circuit

S1 [k]: First scan pulse S2 [k]: Second scan pulse

SW1: first switch TFT SW2: second switch TFT

SW3: Third switch TFT Cst: Storage capacitor Vdata, VDD-Vdata: Data voltage DR: Driving TFT

The present invention relates to an organic light emitting diode display, and more particularly, to an organic light emitting diode display and a driving method thereof capable of improving display quality.

Recently, various flat panel displays (FPDs) that can reduce weight and volume, which are disadvantages of cathode ray tubes, have been developed. Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (FEDs), plasma display panels (hereinafter referred to as "PDPs") and electric fields. Light emitting devices; and the like.

PDP is attracting attention as a display device that is light and small and is most advantageous for large screen because of its simple structure and manufacturing process. However, PDP has low luminous efficiency, low luminance and high power consumption. TFT LCDs with thin film transistors (hereinafter referred to as "TFTs") as switching devices are the most widely used flat panel display devices, but they have a narrow viewing angle and low response speed because they are non-light emitting devices. In contrast, electroluminescent devices are classified into inorganic light emitting diode display devices and organic light emitting diode display devices according to the material of the light emitting layer, and are self-light emitting devices that emit light by themselves, and have fast response speed, high luminous efficiency, luminance, and viewing angle.

The organic light emitting diode display has an organic light emitting diode as shown in FIG. 1. The organic light emitting diode includes an organic compound layer (HIL, HTL, EML, ETL, EIL) formed between the anode electrode and the cathode electrode.

The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL).

When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the emission layer EML to form excitons, and as a result, the emission layer EML becomes Causes visible light to emanate.

The organic light emitting diode display device arranges the pixels having the organic light emitting diodes in a matrix form as shown in FIG.

Such an organic light emitting diode display is divided into a passive matrix type or an active matrix type display device using a TFT as a switching element.

The active matrix method selectively turns on the active TFT, selects a pixel, and maintains light emission of the pixel at a voltage maintained in a storage capacitor.

2 is an equivalent circuit diagram of one pixel in an active matrix organic light emitting diode display.

Referring to FIG. 2, a pixel of an organic light emitting diode display of an active matrix type includes an organic light emitting diode OLED, a data line DL and a gate line GL, a switch TFT SW, and a driving TFT DR that cross each other. ), And a storage capacitor Cst. The switch TFT (SW) and the driving TFT (DR) are implemented with an N-type MOS-FET.

The switch TFT SW is turned on in response to a scan pulse from the gate line GL to conduct a current path between its source electrode and drain electrode. During the on-time period of the switch TFT SW, the data voltage from the data line DL is applied to the gate electrode and the storage capacitor Cst of the driving TFT DR via the source electrode and the drain electrode of the switch TFT SW. Is approved.

The driving TFT DR controls the current flowing through the organic light emitting diode OLED according to the gate voltage Vg supplied to its gate electrode, that is, the data voltage.

The storage capacitor Cst stores the difference voltage between the data voltage and the high potential power voltage VDD to maintain a constant voltage applied to the gate electrode of the driving TFT DR for one frame period.

The organic light emitting diode OLED is implemented in the structure shown in FIG. 1. This organic light emitting diode OLED is connected between the source electrode of the driving TFT DR and a low potential power supply voltage source.

The brightness of the pixel as shown in FIG. 2 is proportional to the current flowing in the organic light emitting diode OLED, and the current is controlled by the gate voltage of the driving TFT DR.

The current Ioled of the organic light emitting diode OLED controlled by the driving TFT DR is expressed by Equation 1 below.

Here, 'Vgs' is a difference voltage between the gate voltage Vg and the source voltage Vs of the driving TFT DR, 'Vdata' is a data voltage, 'Voled' is a voltage across both ends of the organic light emitting diode OLED, Vth 'denotes a threshold voltage of the driving TFT DR, and' k 'denotes a constant value determined by mobility and parasitic capacitance of the driving TFT DR, respectively.

As shown in Equation 1, the current Ioled of the organic light emitting diode OLED is the threshold voltage Vgs between the gate voltage Vg and the source voltage Vs of the driving TFT DR and the threshold of the driving TFT DR. It is influenced by the voltage Vth.

However, in the above-described conventional bottom anode type organic light emitting diode display device, the difference voltage Vgs between the gate voltage Vg and the source voltage Vs of the driving TFT DR is in addition to the gate voltage Vg. It also varies depending on the source voltage Vs. This is because the source voltage Vs is equivalently the voltage across both ends of the organic light emitting diode OLED, and is greatly influenced by the current-voltage characteristics of the organic light emitting diode OLED shown in FIG. 3. In FIG. 3, the horizontal axis represents a voltage applied to the organic light emitting diode OLED, and the vertical axis represents a current flowing through the organic light emitting diode OLED, and Is represents a saturation current of the organic light emitting diode OLED. In addition, the current-voltage characteristic of the organic light emitting diode (OLED) includes an OLED resistance characteristic and a saturation current characteristic Is. As the driving time becomes longer, the saturation current Is tends to decrease, and the OLED resistance tends to increase to keep the current flowing through the organic light emitting diode OLED constant. In other words, when the organic light emitting diode OLED is deteriorated by long time driving, the saturation current Is decreases as shown in FIG. 3 (2.0 → 0.5), and the OLED resistance increases, thereby increasing both ends of the organic light emitting diode OLED. Voltage Voled is increased. In Equation 1, an increase in the voltage across the organic light emitting diode OLED results in a decrease in the current Ioled of the organic light emitting diode OLED. As a result, the voltage of both ends of the organic light emitting diode OLED is changed by the change in the saturation current Is of the organic light emitting diode OLED, so that even if the same data voltage Vdata is applied, as shown in FIG. 4. The current Ioled flowing in the organic light emitting diode OLED decreases in proportion to the decrease in the saturation current Is. In FIG. 4, the horizontal axis represents the saturation current Is of the organic light emitting diode OLED, and the vertical axis represents the current Ioled flowing through the organic light emitting diode OLED.

In addition, since the source voltage Vs is the voltage across the organic light emitting diode OLED, even if the same data voltage is applied, the driving current Ioled flowing through the organic light emitting diode OLED is a high potential driving voltage as shown in FIG. 5. Sensitively fluctuates with changes in (VDD). In general, the high potential driving voltage VDD is slightly different depending on the arrangement position of the pixels. This is because the line resistance due to the parasitic capacitance present in the driving voltage supply line (not shown) varies depending on the arrangement position of the pixels. In FIG. 5, the horizontal axis represents the high potential driving voltage VDD supplied to the pixel, and the vertical axis represents the driving current Ioled flowing through the organic light emitting diode OLED.

As described above, the conventional bottom anode type organic light emitting diode display includes a current of the organic light emitting diode OLED by including a voltage of both ends of the organic light emitting diode OLED as a factor in a driving current function. The display quality is deteriorated due to the voltage characteristics and the voltage variation of the high potential driving voltage (VDD) line.

Accordingly, an object of the present invention is to provide an organic light emitting diode display device and a method of driving the same, which improve the display quality by preventing the driving current from being affected by the current-voltage characteristic variation of the organic light emitting diode and the voltage variation of the high potential driving voltage line. There is.

In order to achieve the above object, the organic light emitting diode display according to the embodiment of the present invention comprises a plurality of data lines supplied with a data voltage; A plurality of gate line pairs each including a first gate line to which a first scan pulse is supplied and a second gate line to which a second scan pulse generated in antiphase with respect to the first scan pulse is supplied; A high potential drive voltage source for generating a high potential drive voltage; A base voltage source for generating a base voltage; An organic light emitting diode emitting light by a current flowing between the high potential driving voltage source and the base voltage source; A driving element controlling a current flowing through the organic light emitting diode according to a gate electrode connected to a first node and a gate-source voltage Vgs applied between the source electrode; A storage capacitor formed between the first node and the second node; And conducting a current path between the source electrode of the driving device and the second node during the light emitting period of the organic light emitting diode to adjust the voltage of the first node to a voltage obtained by adding the data voltage to the source voltage of the driving device. A switch circuit is provided.

The switch circuit initializes the first node and the second node to different voltages during the address period preceding the light emission period.

The address period is a period in which a period between the rising edge of the first scan pulse and the falling edge of the first scan pulse and the period between the falling edge of the second scan pulse and the rising edge of the second scan pulse overlap each other. Wherein the light emission period is a low logic period of the first scan pulse starting from a falling edge of the first scan pulse and a high logic period of the second scan pulse starting from a rising edge of the second scan pulse. It is defined as a period overlapping each other.

In the organic light emitting diode display according to the first embodiment of the present invention, the voltage initialized at the first node during the address period is the data voltage, and the voltage initialized at the second node is the base voltage.

The switch circuit may include: a first switch element forming a current path between the data line and the first node in response to the first scan pulse; A second switch element forming a current path between the base voltage source and the second node in response to the first scan pulse; And a third switch device forming a current path between the source electrode of the driving device and the second node in response to the second scan pulse.

The driving device may include a gate electrode connected to the first node; A drain electrode connected to the high potential driving voltage source; And a source electrode commonly connected to the anode electrode of the organic light emitting diode and the drain electrode of the third switch element.

The first switch element may include a gate electrode connected to the first gate line; A drain electrode connected to the data line; And a source electrode connected to the first node.

The second switch element may include a gate electrode connected to the first gate line; A drain electrode connected to the base voltage source; And a source electrode connected to the second node.

The third switch device may include a gate electrode connected to the second gate line; A drain electrode commonly connected to the source electrode of the driving device and the anode electrode of the organic light emitting diode; And a source electrode connected to the second node.

In the organic light emitting diode display according to the second embodiment of the present invention, the voltage initialized to the first node during the address period is the high potential driving voltage, and the voltage initialized to the second node is equal to the high potential driving voltage. The difference voltage of the data voltage.

The switch circuit may include: a first switch element forming a current path between the high potential driving voltage source and the first node in response to the first scan pulse; A second switch element forming a current path between the data line and the second node in response to the first scan pulse; And a third switch device forming a current path between the source electrode of the driving device and the second node in response to the second scan pulse.

The driving device may include a gate electrode connected to the first node; A drain electrode commonly connected to the high potential driving voltage source and the drain electrode of the first switch element; And a source electrode commonly connected to the anode electrode of the organic light emitting diode and the drain electrode of the third switch element.

The first switch element may include a gate electrode connected to the first gate line; A drain electrode commonly connected to the high potential driving voltage source and the drain electrode of the driving element; And a source electrode connected to the first node.

The second switch element may include a gate electrode connected to the first gate line; A drain electrode connected to the data line; And a source electrode connected to the second node.

The third switch device may include a gate electrode connected to the second gate line; A drain electrode commonly connected to the source electrode of the driving device and the anode electrode of the organic light emitting diode; And a source electrode connected to the second node.

The current Ioled flowing through the organic light emitting diode during the light emitting period is expressed by the following equation.

Here, k is a constant value determined by mobility and parasitic capacitance of the driving device, Vgs is a gate-source voltage of the driving device, Vth is a threshold voltage of the driving device, and Vdata is the data voltage.

The driving device and the first to third switch devices are implemented with an N-type electron metal oxide semiconductor field effect transistor.

The driving device includes a semiconductor layer formed of an amorphous silicon layer.

In order to achieve the above object, a plurality of data lines to which a data voltage is supplied, a first gate line to which one scan pulse is supplied, and a second scan pulse generated out of phase with respect to the first scan pulse, according to an embodiment of the present invention, A plurality of gate line pairs each including a second gate line supplied with a high voltage, a high potential driving voltage source for generating a potential driving voltage, a base voltage source for generating a low voltage, and light emission by a current flowing between the high potential driving voltage source and the base voltage source An organic light emitting diode, a gate electrode connected to a first node, and a driving element controlling a current flowing through the organic light emitting diode according to a gate-source voltage Vgs applied between a source electrode, the first node, and a second node A method of driving an organic light emitting diode display device having a storage capacitor formed between nodes and a switch circuit includes the organic light emitting diode. During the address period of the diode comprising: initializing the second node to the first node in a different voltage; And conducting a current path between the source electrode of the driving device and the second node during the light emitting period of the organic light emitting diode to adjust the voltage of the first node to a voltage obtained by adding the data voltage to the source voltage of the driving device. Steps.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 17.

6 to 13b show a first embodiment of the present invention.

FIG. 6 is a block diagram illustrating an organic light emitting diode display according to a first exemplary embodiment of the present invention. FIG. 7 is a diagram illustrating first and second scan pulses S1 [k], which are supplied to the pixels 122 of FIG. A timing diagram of S2 [k]).

6 and 7, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 116 on which m × n pixels 122 are formed, and data lines DL [1] to. The data driving circuit 120 supplying the analog data voltage to DL [m] and the first scan pulse S1 [k] are sequentially applied to the first gate lines GL1 [1] to GL1 [n]. A gate driving circuit 118 for sequentially supplying the second scan pulse S2 [k] to the second gate lines GL2 [1] to GL2 [n], a data driving circuit 120 and A timing controller 124 for controlling the driving timing of the gate driving circuit 118 is provided.

The display panel 116 is a pixel defined by the intersection of the gate lines GL [1] to GL [n] and GL2 [1] to GL2 [n] and the data lines DL [1] to DL [m]. Pixels 122 formed in the regions are provided. The display panel 116 is provided with signal wirings for supplying a high potential driving voltage to each of the pixels 122 and signal wirings for supplying a low potential driving voltage.

The data driving circuit 120 converts the digital video data RGB into an analog data voltage in response to the control signal DDC from the timing controller 124, and then converts the analog data voltage (hereinafter, referred to as data voltage) into data. To the lines DL [1] to DL [m]. This data voltage is supplied to the pixels 122 through the data lines DL [1] to DL [m].

The gate driving circuit 118 receives the first and second scan pulses S1 [k] and S2 [k] shown in FIG. 7 in response to the control signal GDC from the timing controller 124. Two gate lines GL1 [1] through GL1 [n] and GL2 [1] through GL2 [n] are sequentially supplied. The first and second scan pulses S1 [k] and S2 [k] are used to separate the first and second gate lines GL1 [1] to GL1 [n] and GL2 [1] to GL2 [n]. Are supplied to the pixels 122 through.

The timing controller 124 supplies digital video data RGB to the data driving circuit 120 and operates timings of the gate driving circuit 118 and the data driving circuit 120 using vertical / horizontal synchronization signals and clock signals. It generates a control signal (DDC, GDC) to control.

In the timing diagram of FIG. 7, A indicates an address period and B indicates a light emission period. The first scan pulse S1 [k] and the second scan pulse S2 [k] indicate the scan pulses supplied through the k-th gate lines GL1 [k] and GL2 [k], respectively.

The address period A is a period between the rising edge of the first scan pulse S1 [k] and the falling edge of the first scan pulse S1 [k] and the falling edge of the second scan pulse S2 [k]. And a period between the rising edges of the second scan pulse S2 [k] are defined as overlapping periods. The light emission period B is a low logic period of the first scan pulse S1 [k] and a rising edge of the second scan pulse S2 [k] starting from the falling edge of the first scan pulse S1 [k]. The high logic period of the second scan pulse S2 [k] starting from is overlapped with each other. Here, the second scan pulse S2 [k] is generated to have a logic value opposite to that of the first scan pulse S1 [k]. That is, the falling edge of the second scan pulse S2 [k] is synchronized with the rising edge of the first scan pulse S1 [k], and the rising edge of the second scan pulse S2 [k] is the first scan. It is synchronized with the falling edge of the pulse S1 [k]. The address period A is set to satisfy approximately one horizontal period 1H. The operation of the pixels 122 in the address period A and the light emission period B will be described in detail with reference to FIGS. 9 and 10.

Meanwhile, the display panel 116 has a high potential driving voltage source VDD for supplying a high potential driving voltage VDD to the pixels 122, and a low potential driving voltage source VSS for supplying a low potential driving voltage VSS. Is connected. The low potential drive voltage VSS is usually set to a base voltage.

Each of the pixels 122 includes an organic light emitting diode OLED, one driving TFT DR, three switch TFTs SW1 to SW3, and one capacitor Cst as shown in FIG. 8.

8 is an equivalent circuit diagram illustrating a pixel 122 included in an organic light emitting diode display according to a first exemplary embodiment of the present invention.

Referring to FIG. 8, the pixel 122 according to the first exemplary embodiment of the present invention is supplied from the data lines DL [1] to DL [m] and the gate lines GL [1] to GL [n]. An organic light emitting diode driving circuit 130 for driving the organic light emitting diode OLED in response to the driving signals Vdata, S1 [k], S2 [k], an organic light emitting diode driving circuit 130, and a low potential driving voltage source And an organic light emitting diode OLED, which is connected between the VSSs and whose light emission amount is adjusted according to the driving current generated by the drive signal.

The organic light emitting diode driving circuit 130 includes a driving TFT DR for controlling a driving current flowing in the organic light emitting diode OLED, and a data voltage (V) at the first node n1: gate G of the driving TFT DR. Source electrode of the first switch TFT SW1 for supplying Vdata, the second switch TFT SW2 for supplying the base voltage to the second node n2, the second node n2, and the driving TFT DR. A storage capacitor which stores the data voltage Vdata charged in the third switch TFT SW3 and the first node n1 and the base voltage charged in the second node n2, which switches the current path between (S) ( Cst). Here, the TFTs are implemented with an N-type electron metal oxide semiconductor field effect transistor (MOSFET, MetAl-Oxide SemiConduCtor Field EffeCt TrAnsistor). In particular, the semiconductor layers of the TFTs are formed of an amorphous silicon layer so that the amount of change in the threshold voltage between the driving TFTs DR due to the same gate bias stress is almost the same.

The gate electrode G of the driving TFT DR is connected to the first node n1, the drain electrode D of the driving TFT DR is connected to the high potential driving voltage source VDD, and the driving TFT DR. The source electrode S is connected in common to the anode electrode of the organic light emitting diode OLED and the drain electrode D of the third switch TFT SW3. The driving TFT DR controls the amount of current flowing through the organic light emitting diode OLED according to the difference voltage Vgs between the gate voltage applied to the gate electrode G and the source voltage applied to the source electrode S. FIG.

The gate electrode G of the first switch TFT SW1 is connected to the k-th first gate line GL1 [k], and the drain electrode D of the first switch TFT SW1 is connected to the data line DL. The source electrode S of the first switch TFT SW1 is connected to the first node n1. The first switch TFT SW1 is turned on in response to the first scan pulse S1 [k] from the k-th first gate line GL1 [k], thereby providing a data voltage from the data line DL. Causes Vdata to be supplied to the first node n1. The data voltage Vdata is applied to one side of the storage capacitor Cst through the first node n1.

The gate electrode G of the second switch TFT SW2 is commonly connected to the gate electrode G of the first switch TFT SW1 and the k-th first gate line GL1 [k], and the second switch TFT ( The drain electrode D of SW2 is connected to the low potential driving voltage source VSS, and the source electrode S of the second switch TFT SW2 is connected to the second node n2. The second switch TFT SW2 is turned on in response to the first scan pulse S1 [k] from the k-th first gate line GL1 [k], and thus, from the low potential driving voltage source VSS. The base voltage is supplied to the second node n2. The base voltage is applied to the other side of the storage capacitor Cst through the second node n2.

The gate electrode G of the third switch TFT SW3 is connected to the k-th second gate line GL2 [k], and the drain electrode D of the third switch TFT SW3 is connected to the driving TFT DR. Commonly connected to the source electrode S and the anode electrode of the organic light emitting diode OLED, the source electrode S of the third switch TFT SW3 is connected to the second node n2. The third switch TFT SW3 is turned on in response to the second scan pulse S2 [k] from the k-th second gate line GL2 [k], whereby the source voltage of the driving TFT DR is increased. To be supplied to the second node n2. The source voltage is applied to the other side of the storage capacitor Cst through the second node n2.

One side of the storage capacitor Cst is connected to the first node n1, and the other side of the storage capacitor Cst is connected to the second node n2. The storage capacitor Cst has the voltage of the first node n1 as the data voltage Vdata during the high logic period (A section in FIG. 7) of the first scan pulse S1 [k] and the first scan pulse ( During the low logic period (B section in FIG. 7) of S1 [k]), the compensation voltage is maintained. Here, the compensation voltage refers to the sum of the data voltage Vdata and the driving TFT DR source voltage.

The anode of the organic light emitting diode OLED is commonly connected to the source electrode S of the driving TFT DR and the drain electrode D of the third switch TFT SW3, and the cathode is connected to the low potential driving voltage source VSS. do. The organic light emitting diode OLED has the structure as shown in FIG. 1, and the amount of light emitted is controlled depending on the change in the data voltage Vdata without being affected by the change in its own current-voltage characteristic or the change in the high potential driving voltage. Here, the anode electrode of the organic light emitting diode OLED is formed on the same substrate as the driving TFT DR. Accordingly, the pixels 122 emit light according to a bottom emission method.

The operation of the pixels 122 will be described below with reference to FIGS. 9 and 10.

FIG. 9 is an equivalent circuit diagram of the pixel 122 for the address period A of FIG.

Referring to FIG. 9, during the address period A, the first scan pulse S1 [k] is generated at a high logic voltage to turn on the first switch TFT and the second switch TFTs SW1 and SW2 and to turn on the second. The scan pulse S2 [k] is generated at a low logic voltage to turn off the third switch TFT SW3. Accordingly, the data voltage Vdata is applied to the first node n1 connected to the gate electrode G of the driving TFT DR, and is opposite to the first node n1 with the storage capacitor Cst interposed therebetween. The ground voltage (0 V) is applied to the second node n2 located at.

As a result, the data voltage Vdata is stored in the storage capacitor Cst during the address period A as shown in Equation 2 below.

Here, 'Vst' represents the voltage across the storage capacitor Cst.

FIG. 10 is an equivalent circuit diagram of the pixel 122 for the light emission period B of FIG. 7.

Referring to FIG. 10, during the light emission period B, the first scan pulse S1 [k] is inverted to a low logic voltage to turn off the first switch TFT and the second switch TFTs SW1 and SW2. The second scan pulse S2 [k] is inverted to a high logic voltage to turn on the third switch TFT SW3.

Accordingly, the potential of the second node n2 rises from the base voltage (0 V) to the source voltage Vs of the driving TFT DR. Due to the potential rise of the second node n2, the relative potential of the first node n1 with respect to the second node n2 also increases by the source voltage Vs. Since the potential of the first node n1 is increased by the source voltage Vs, the gate voltage Vg of the driving TFT DR becomes the compensation voltage Vs + Vdata.

Therefore, the difference voltage Vgs between the gate voltage Vg of the driving TFT DR and the source voltage Vs during the light emission period B is equal to the voltage Vst between the both ends of the storage capacitor Cst as shown in Equation 3 below. Therefore, the data voltage is Vdata.

As shown in Equation 3, since the difference voltage Vgs between the gate voltage Vg of the driving TFT DR and the source voltage Vs converges to the data voltage Vdata, the organic light emitting diode OLED is emitted during the light emission period B. The driving current Ioled flowing in Equation 4 is expressed by Equation 4 below.

Referring to Equation 4, the driving current Ioled flowing in the organic light emitting diode OLED is not influenced at all by the voltages of both ends of the organic light emitting diode OLED, which are the source voltage Vs of the driving TFT DR. Accordingly, even if the current-voltage characteristic of the organic light emitting diode OLED is changed or the high potential power voltage VDD is changed due to the line resistance, the driving current Ioled flowing to the organic light emitting diode OLED is completely unchanged. By not being affected, the display quality can be improved.

FIG. 11 shows the voltage Vg (Vst +) applied to the first node n1 and the voltage Vst− applied to the second node n2 in the address period A and the light emission period B of FIG. , A simulation result showing the transient state of the source voltage Vs (Voled) of the driving TFT DR, the voltage Vst stored in the storage capacitor Cst, and the driving current Ioled.

Referring to FIG. 11, during the light emitting period B, the potential Vst + of the first node n1, which is the gate voltage Vg of the driving TFT DR, is the organic light emission of the source voltage Vs of the driving TFT DR. Since the data voltage Vdata is higher than the voltage across the diode OLED, the difference voltage Vgs between the gate voltage and the source voltage of the driving TFT DR results in the data voltage Vdata as shown in Equation 3 below. Able to know.

12A and 12B illustrate that the difference voltage Vgs and the drive current Ioled between the gate voltage and the source voltage of the driving TFT DR are not affected even when the saturation current Is of the organic light emitting diode OLED is changed. It is a graph for this.

In FIG. 12A, even when the saturation current Is of the current-voltage characteristic of the organic light emitting diode OLED is changed from 0.5 to 2, the difference voltage Vgs between the gate voltage and the source voltage of the driving TFT DR is the data voltage Vdata. Since it is a function of only, it is changed only by the data voltage Vdata.

Since the difference voltage Vgs between the gate voltage and the source voltage of the driving TFT DR is a function of the data voltage Vdata only, the driving current Ioled is the organic light emitting diode OLED at the same data voltage Vdata as shown in FIG. 12B. It remains constant without being affected by the change of saturation current Is.

13A and 13B are graphs for explaining that even when the high potential driving voltage VDD is changed, the difference voltage Vgs and the driving current Ioled of the gate voltage and the source voltage of the driving TFT DR are not affected.

In FIG. 13A, even when the high potential driving voltage VDD is changed from -10% to + 10%, that is, 13.5V to 16.5V due to the line resistance, the difference voltage Vgs between the gate voltage and the source voltage of the driving TFT DR is maintained. Since it is a function of the data voltage Vdata only, it is changed only by the data voltage Vdata.

Since the difference voltage Vgs between the gate voltage and the source voltage of the driving TFT DR is a function of only the data voltage Vdata, as shown in FIG. 13B, the driving current Ioled is the high potential driving voltage VDD at the same data voltage Vdata. It remains constant and unaffected by changes.

14 to 17 show a second embodiment of the present invention.

14 is a block diagram illustrating an organic light emitting diode display according to a second exemplary embodiment of the present invention.

Referring to FIG. 14, in the organic light emitting diode display according to the second embodiment of the present invention, constituent means performing substantially the same function as the first embodiment of the present invention are denoted by the same reference numerals as those of the first embodiment. And detailed description thereof will be omitted. The second embodiment of the present invention simplifies the circuit configuration in the TFT backplane by removing one of two power supply lines supplying the low potential power voltage VSS to the unit pixel 222. Further, in the second embodiment of the present invention, the compensation data voltage set to the difference voltage VDD-Vdata of the high potential driving voltage VDD and the data voltage Vdata is supplied to the pixels 222 through the data line. .

Each of the pixels 122 includes an organic light emitting diode OLED, one driving TFT DR, three switch TFTs SW1 to SW3, and one capacitor Cst as shown in FIG. 15.

FIG. 15 is an equivalent circuit diagram illustrating a pixel 222 included in an organic light emitting diode display according to a second exemplary embodiment of the present invention.

Referring to FIG. 15, the pixel 122 according to the second exemplary embodiment of the present invention is supplied from the data lines DL [1] to DL [m] and the gate lines GL [1] to GL [n]. The organic light emitting diode driving circuit 230 for driving the organic light emitting diode OLED in response to the driving signals VDD-Vdata, S1 [k], S2 [k], the organic light emitting diode driving circuit 230 and the low potential An organic light emitting diode OLED is connected between the driving voltage sources VSS and the light emission amount is adjusted according to the driving current generated by the driving signal. The first and second scan pulses S1 [k] and S2 [k] are supplied in the same manner as in FIG.

The organic light emitting diode driving circuit 230 drives a high potential to the driving TFT DR for controlling the driving current flowing through the organic light emitting diode OLED, and the first node n1: the gate G of the driving TFT DR. The first switch TFT SW1 for supplying the voltage VDD, the second switch TFT SW2 for supplying the compensation data voltage VDD-Vdata to the second node n2, and the second node n2; At the high potential driving voltage VDD and the second node n2 charged in the third switch TFT SW3 and the first node n1 for switching the current path between the source electrode S of the driving TFT DR. The storage capacitor Cst stores the charged compensation data voltages VDD-Vdata. Here, the TFTs are implemented with an N-type electron metal oxide semiconductor field effect transistor (MOSFET, MetAl-Oxide SemiConduCtor Field EffeCt TrAnsistor). In particular, the semiconductor layers of the TFTs are formed of an amorphous silicon layer so that the amount of change in the threshold voltage between the driving TFTs DR due to the same gate bias stress is almost the same.

The gate electrode G of the driving TFT DR is connected to the first node n1, and the drain electrode D of the driving TFT DR is connected to the high potential driving voltage source VDD and the first switch TFT SW1. Commonly connected to the drain electrode D, the source electrode S of the driving TFT DR is commonly connected to the anode electrode of the organic light emitting diode OLED and the drain electrode D of the third switch TFT SW3. The driving TFT DR controls the amount of current flowing through the organic light emitting diode OLED according to the difference voltage Vgs between the gate voltage applied to the gate electrode G and the source voltage applied to the source electrode S. FIG.

The gate electrode G of the first switch TFT SW1 is connected to the k-th first gate line GL1 [k], and the drain electrode D of the first switch TFT SW1 is the high potential driving voltage source VDD. ) Is connected to the drain electrode D of the driving TFT DR, and the source electrode S of the first switch TFT SW1 is connected to the first node n1. The first switch TFT SW1 is turned on in response to the first scan pulse S1 [k] from the k-th first gate line GL1 [k], whereby the high potential driving voltage VDD is applied to the first switch TFT SW1. To be supplied to one node n1. The high potential driving voltage VDD is applied to one side of the storage capacitor Cst through the first node n1.

The gate electrode G of the second switch TFT SW2 is commonly connected to the gate electrode G of the first switch TFT SW1 and the k-th first gate line GL1 [k], and the second switch TFT ( The drain electrode D of SW2 is connected to the data line DL, and the source electrode S of the second switch TFT SW2 is connected to the second node n2. The second switch TFT SW2 is turned on in response to the first scan pulse S1 [k] from the k-th first gate line GL1 [k], thereby compensating data from the data line DL. The voltage VDD-Vdata is supplied to the second node n2. The compensation data voltages VDD-Vdata are applied to the other side of the storage capacitor Cst through the second node n2.

The gate electrode G of the third switch TFT SW3 is connected to the k-th second gate line GL2 [k], and the drain electrode D of the third switch TFT SW3 is connected to the driving TFT DR. Commonly connected to the source electrode S and the anode electrode of the organic light emitting diode OLED, the source electrode S of the third switch TFT SW3 is connected to the second node n2. The third switch TFT SW3 is turned on in response to the second scan pulse S1 [k] from the k-th second gate line GL2 [k], whereby the source voltage of the driving TFT DR is increased. To be supplied to the second node n2. The source voltage is applied to the other side of the storage capacitor Cst through the second node n2.

One side of the storage capacitor Cst is connected to the first node n1, and the other side of the storage capacitor Cst is connected to the second node n2. The storage capacitor Cst maintains the potential of the first node n1 with respect to the second node n2 at the data voltage Vdata during the address period A and the light emission period B of FIG. 7.

The anode of the organic light emitting diode OLED is commonly connected to the source electrode S of the driving TFT DR and the drain electrode D of the third switch TFT SW3, and the cathode is connected to the low potential driving voltage source VSS. do. The organic light emitting diode OLED has the structure as shown in FIG. 1, and the amount of light emitted is controlled depending on the change in the data voltage Vdata without being affected by the change in its own current-voltage characteristic or the change in the high potential driving voltage. Here, the anode electrode of the organic light emitting diode OLED is formed on the same substrate as the driving TFT DR. Accordingly, the pixels 222 emit light according to a bottom emission method.

The operation of the pixels 222 will be described below with reference to FIGS. 16 and 17.

FIG. 16 is an equivalent circuit diagram of the pixel 222 for the address period A of FIG.

Referring to FIG. 16, during the address period A, the first scan pulse S1 [k] is generated at a high logic voltage to turn on the first switch TFT and the second switch TFTs SW1 and SW2, and the second scan pulse S1 [k]. The scan pulse S2 [k] is generated at a low logic voltage to turn off the third switch TFT SW3. Accordingly, the high potential driving voltage VDD is applied to the first node n1 connected to the gate electrode G of the driving TFT DR, and the first node n1 is interposed with the storage capacitor Cst interposed therebetween. The compensation data voltage VDD-Vdata is applied to the second node n2 located opposite to.

As a result, the data voltage Vdata is stored in the storage capacitor Cst as shown in Equation 2 during the address period A. FIG.

FIG. 17 is an equivalent circuit diagram of the pixel 222 for the light emitting period B of FIG. 7.

Referring to FIG. 17, during the light emission period B, the first scan pulse S1 [k] is inverted to a low logic voltage to turn off the first and second switch TFTs SW1 and SW2. The second scan pulse S2 [k] is inverted to a high logic voltage to turn on the third switch TFT SW3.

Accordingly, the potential of the second node n2 converges to the source voltage Vs of the driving TFT DR. Since the potential of the first node n1 with respect to the second node n2 fluctuates by the width as much as the fluctuation width of the second node n2, the gate voltage Vg of the driving TFT DR during the light emission period B. ) And the difference voltage Vgs between the source voltage Vs are maintained as the data voltage Vdata, which is the voltage Vst between the storage capacitor Cst.

As shown in Equation 3, since the difference voltage Vgs between the gate voltage Vg and the source voltage Vs of the driving TFT DR is maintained as the data voltage Vdata, the organic light emitting diode OLED is emitted during the light emitting period B. The driving current Ioled flowing in Equation 4 is expressed by Equation 4.

As shown in Equation 4, the driving current Ioled flowing in the organic light emitting diode OLED is not influenced at all by the voltages of both ends of the organic light emitting diode OLED, which are the source voltage Vs of the driving TFT DR. Accordingly, even if the current-voltage characteristic of the organic light emitting diode OLED is changed or the high potential power voltage VDD is changed due to the line resistance, the driving current Ioled flowing to the organic light emitting diode OLED is completely unchanged. By not being affected, the display quality can be improved.

As described above, the organic light emitting diode display and the driving method thereof according to the present invention are characterized in that the current-voltage characteristics and high potential driving of the organic light emitting diode are achieved by making the difference voltage between the gate voltage and the source voltage of the driving TFT become a data voltage. Even if the voltage changes, the current flowing through the organic light emitting diode is not affected, thereby improving display quality and improving image quality reliability.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (23)

A plurality of data lines supplied with data voltages; A plurality of gate line pairs each including a first gate line to which a first scan pulse is supplied and a second gate line to which a second scan pulse generated in antiphase with respect to the first scan pulse is supplied; A high potential drive voltage source for generating a high potential drive voltage; A base voltage source for generating a base voltage; An organic light emitting diode emitting light by a current flowing between the high potential driving voltage source and the base voltage source; A driving element controlling a current flowing through the organic light emitting diode according to a gate electrode connected to a first node and a gate-source voltage Vgs applied between the source electrode; A storage capacitor formed between the first node and the second node; And A switch for conducting a current path between the source electrode of the driving device and the second node during the light emitting period of the organic light emitting diode to adjust the voltage of the first node to a voltage obtained by adding the data voltage to the source voltage of the driving device; An organic light emitting diode display device comprising a circuit. The method of claim 1, The switch circuit, And the first node and the second node are initialized to different voltages during the address period preceding the light emitting period. The method of claim 2, The address period is a period in which a period between the rising edge of the first scan pulse and the falling edge of the first scan pulse and the period between the falling edge of the second scan pulse and the rising edge of the second scan pulse overlap each other. Wherein the light emission period is a low logic period of the first scan pulse starting from a falling edge of the first scan pulse and a high logic period of the second scan pulse starting from a rising edge of the second scan pulse. An organic light emitting diode display, characterized in that it is defined as a period overlapping each other. The method of claim 2, And a voltage initialized to the first node during the address period is the data voltage, and a voltage initialized to the second node is the base voltage. The method of claim 4, wherein The switch circuit, A first switch element forming a current path between the data line and the first node in response to the first scan pulse; A second switch element forming a current path between the base voltage source and the second node in response to the first scan pulse; And And a third switch device for forming a current path between the source electrode of the driving device and the second node in response to the second scan pulse. The method of claim 5, wherein The driving device, A gate electrode connected to the first node; A drain electrode connected to the high potential driving voltage source; And And a source electrode commonly connected to the anode electrode of the organic light emitting diode and the drain electrode of the third switch element. The method of claim 5, wherein The first switch device, A gate electrode connected to the first gate line; A drain electrode connected to the data line; And And a source electrode connected to the first node. The method of claim 5, wherein The second switch device, A gate electrode connected to the first gate line; A drain electrode connected to the base voltage source; And And a source electrode connected to the second node. The method of claim 5, wherein The third switch device, A gate electrode connected to the second gate line; A drain electrode commonly connected to the source electrode of the driving device and the anode electrode of the organic light emitting diode; And And a source electrode connected to the second node. The method of claim 2, Wherein the voltage initialized to the first node during the address period is the high potential driving voltage, and the voltage initialized to the second node is a difference voltage between the high potential driving voltage and the data voltage. Display. The method of claim 10, The switch circuit, A first switch element forming a current path between the high potential driving voltage source and the first node in response to the first scan pulse; A second switch element forming a current path between the data line and the second node in response to the first scan pulse; And And a third switch device for forming a current path between the source electrode of the driving device and the second node in response to the second scan pulse. The method of claim 11, The driving device, A gate electrode connected to the first node; A drain electrode commonly connected to the high potential driving voltage source and the drain electrode of the first switch element; And And a source electrode commonly connected to the anode electrode of the organic light emitting diode and the drain electrode of the third switch element. The method of claim 11, The first switch device, A gate electrode connected to the first gate line; A drain electrode commonly connected to the high potential driving voltage source and the drain electrode of the driving element; And An organic light emitting diode display device comprising: a source electrode connected to the first node. The method of claim 11, The second switch device, A gate electrode connected to the first gate line; A drain electrode connected to the data line; And And a source electrode connected to the second node. The method of claim 11, The third switch device, A gate electrode connected to the second gate line; A drain electrode commonly connected to the source electrode of the driving device and the anode electrode of the organic light emitting diode; And And a source electrode connected to the second node. The method of claim 3, wherein An organic light emitting diode display device, wherein the current Ioled flowing through the organic light emitting diode during the light emitting period is as follows.

Here, k is a constant value determined by mobility and parasitic capacitance of the driving device, Vgs is a gate-source voltage of the driving device, Vth is a threshold voltage of the driving device, and Vdata is the data voltage. The method of claim 5 or 11, And the driving elements and the first to third switch elements are N-type electron metal oxide semiconductor field effect transistors. The method of claim 1, And the driving device includes a semiconductor layer formed of an amorphous silicon layer. A plurality of gates each including a plurality of data lines supplied with a data voltage, a first gate line supplied with one scan pulse, and a second gate line supplied with a second scan pulse generated out of phase with respect to the first scan pulse; A pair of lines, a high potential driving voltage source for generating a potential driving voltage, a base voltage source for generating a low voltage, an organic light emitting diode emitting light by a current flowing between the high potential driving voltage source and the base voltage source, and a gate electrode connected to the first node And a driving device controlling a current flowing through the organic light emitting diode according to a gate-source voltage Vgs applied between the source electrodes, a storage capacitor formed between the first node and the second node, and a plurality of switch devices. A driving method of an organic light emitting diode display device having a switch circuit having: Initializing the first node and the second node to different voltages during an address period of the organic light emitting diode; And Conducting a current path between the source electrode of the driving device and the second node during the light emitting period of the organic light emitting diode to adjust the voltage of the first node to a voltage obtained by adding the data voltage to the source voltage of the driving device; Method of driving an organic light emitting diode display device comprising a. The method of claim 19, The address period is a period in which the period between the rising edge of the first scan pulse and the falling edge of the first scan pulse and the period between the falling edge of the second scan pulse and the rising edge of the second scan pulse overlap each other. Wherein the light emission period is a low logic period of the first scan pulse starting from a falling edge of the first scan pulse and a high logic period of the second scan pulse starting from a rising edge of the second scan pulse. A method of driving an organic light emitting diode display device, characterized in that it is defined as a period overlapping each other. The method of claim 20, And a voltage initialized to the first node during the address period is the data voltage, and a voltage initialized to the second node is the base voltage. The method of claim 20, The voltage initialized at the first node during the address period is the high potential driving voltage, and the voltage initialized at the second node is a difference voltage between the high potential driving voltage and the data voltage. Method of driving the device. The method of claim 20, A method of driving an organic light emitting diode display device according to claim 1, wherein a current Ioled flowing through the organic light emitting diode device during the light emitting period is as follows.

Here, k is a constant value determined by mobility and parasitic capacitance of the driving device, Vgs is a gate-source voltage of the driving device, Vth is a threshold voltage of the driving device, and Vdata is the data voltage.

Images