KR20080082431A - Non-volatile dram device, the method of manufacturing and driving thereof - Google Patents

Abstract

A nonvolatile DRAM device, a manufacturing method thereof, and a driving method thereof are provided to implement high integration by removing a capacitor. A dielectric layer(101) is formed on a substrate(100). A floating body cell(102) is formed on the dielectric layer. A source(103) and a drain(104) are formed on the left and right of the floating body cell. Nonvolatile gate structures(105,106,107,108) are formed on a surface of the floating body cell. A back gate is formed on a lower portion of the substrate. The floating body cell is formed in a fin structure. The nonvolatile gate structure is formed at a side of the floating body cell. The back gate is formed at the other side of the fin structure. The nonvolatile gate structure includes a tunneling dielectric, a floating gate, a control dielectric, and a gate. The floating gate is a nitride layer, an amorphous silicon layer, a metal oxide layer, a silicon nitride layer, a silicon nano crystal layer, a metal nano crystal layer, or a metal oxide nano crystal layer for forming an SONOS(Silicon-Oxide-Nitride-Oxide-Silicon) or MNOS(Metal-Nitride-Oxide-Silicon) structure.

Description

Nonvolatile DRAM device, method for manufacturing same, and method for driving same. {NON-VOLATILE DRAM DEVICE, THE METHOD OF MANUFACTURING AND DRIVING THEREOF}

The present invention relates to a nonvolatile DRAM device, a method of manufacturing the same, and a method of driving the same.

DRAM has a unit cell composed of one MOSFET and one capacitor, and is widely used as a system memory device because its configuration is simple and operates at high speed when power is supplied. However, there is a problem that it is difficult to scale down the capacitor area with respect to the entire area of the unit cell when the device is scaled down for high integration, and the stored data is not maintained when the power supply is stopped.

On the other hand, unlike DRAM, one of the proposed flash memory devices for storing nonvolatile information is also difficult to scale down the tunneling insulating layer, a long time for writing / erasing information, and a high voltage required for writing / erasing information. Has a problem.

The present invention for solving these problems can maintain the data stored with the nonvolatile memory device even if the power supply is interrupted, non-volatile DRAM device that can operate at a high speed, such as DRAM at the time of power supply, a manufacturing method and a driving method thereof To provide a task to solve.

In addition, an object of the present invention is to solve the problem of providing a nonvolatile DRAM device, a method for manufacturing the same, and a method for driving the same, which can achieve high integration by removing a capacitor.

The nonvolatile DRAM device according to an embodiment of the present invention for achieving the above technical problem, the insulating layer formed on the substrate, the floating body formed on the insulating layer, the source and drain formed on the left and right sides of the floating body and the floating And a nonvolatile gate structure formed on the body cell surface.

Here, the substrate may further include a back gate formed under the substrate. Here, the floating body may be formed of a fin structure.

Here, the nonvolatile gate structure may be formed on one side of the floating body, and a back gate may be formed on the other side of the floating body.

The nonvolatile gate structure may be formed on one side of the floating body, and the nonvolatile gate structure may be formed on the other side of the floating body.

Here, the nonvolatile gate structure includes a tunneling insulating film, a floating gate, a control insulating film and a gate.

Here, the floating gate may include a polysilicon layer, a nitride layer, an amorphous silicon layer, a metal oxide layer, or a silicon nitride layer forming a silicon-oxide-nitride-oxide-silicon (SONOS) or metal-nitride-oxide-silicon (MNOS) structure. It is preferable that it is a layer, a silicon nanocrystal layer, a metal nanocrystal layer, or a metal oxide nanocrystal layer.

A nonvolatile DRAM device according to another embodiment of the present invention includes an ion implantation layer formed on a substrate, a floating body cell formed on the ion implantation layer, a source and a drain formed on the left and right sides of the floating body cell, and a surface of the floating body cell. And a nonvolatile gate structure formed.

Here, the ion implantation layer is preferably germanium (Ge) or a high-dose P-type impurity ion implantation layer.

Here, the floating body may be formed in a vertical fin (Fin) structure.

Here, the nonvolatile gate structure may be formed on one side of the floating body, and a back gate may be formed on the other side of the floating body.

The nonvolatile gate structure may be formed on one side of the floating body, and the nonvolatile gate structure may be formed on the other side of the floating body.

Here, the nonvolatile gate structure includes a tunneling insulating film, a floating gate, a control insulating film and a gate.

The floating gate may include a polysilicon layer, a nitride layer, an amorphous silicon layer, a metal oxide layer, and a silicon nitride layer forming a silicon-oxide-nitride-oxide-silicon (SONOS) or metal-nitride-oxide-silicon (MNOS) structure. It is preferable that it is a layer, a silicon nanocrystal layer, a metal nanocrystal layer, or a metal oxide nanocrystal layer.

The nonvolatile gate structure may include a tunneling insulating film formed on the floating body, a carbon nanotube formed vertically on the tunneling insulating film, an insulating film formed on the tunneling insulating film by filling the carbon nanotubes; It is preferable to include a blocking insulating film formed on the insulating film and a gate formed on the blocking insulating film.

Here, the carbon nanotubes are preferably single-stranded single-walled carbon nanotubes or single-stranded multi-walled carbon nanotubes.

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile DRAM device, including (a) forming a floating body capable of accumulating holes in a substrate, and (b) forming an electron on the surface of the floating body. Forming a non-volatile gate structure that can be injected and (c) forming a source and a drain in the floating body.

Here, step (a) may form the floating body by forming an insulating layer in the substrate.

Here, in the step (a), germanium (Ge) or high-dose P-type impurity ions may be implanted into the substrate to form the floating body.

The step (b) may include forming a tunneling insulating film on the surface of the floating body cell, forming a floating gate on the tunneling insulating film, forming a control insulating film on the floating gate and the tunneling insulating film; Forming a gate on the control insulating film.

Here, the floating gate may include a polysilicon layer, a nitride layer, an amorphous silicon layer, a metal oxide layer, or a silicon nitride layer forming a silicon-oxide-nitride-oxide-silicon (SONOS) or metal-nitride-oxide-silicon (MNOS) structure. Layer, silicon nanocrystal layer, metal nanocrystal layer, or metal oxide nanocrystal layer.

The method may further include forming a back gate under the substrate.

Here, the step (a) is a step of forming a germanium or high-doped P-type impurity ion implantation layer in the substrate and by patterning the upper portion of the substrate divided by the ion implantation layer of the vertical fin (Fin) structure It may comprise the step of forming the floating body.

Here, step (b) may include forming the nonvolatile gate structure on one side of the floating body and forming a back gate on the other side of the floating body.

Here, the step (b) may include forming the nonvolatile gate structure on one side of the floating body and forming the nonvolatile gate structure on the other side of the floating body.

A method of driving a nonvolatile DRAM device according to another embodiment of the present invention includes a DRAM mode step of accumulating or evicting holes in the floating body, and a non-injecting or erasing electron in a floating gate formed in the nonvolatile gate structure. Volatile memory mode step.

Here, the DRAM mode step may accumulate or expel holes in the floating body by a gate induced drain leakage effect.

As described in detail above, according to the present invention, a nonvolatile DRAM device capable of maintaining data stored in a unit cell even when the power supply is interrupted and capable of operating at a high speed such as a DRAM at the time of power supply, and a manufacturing method thereof are provided. There is.

In addition, according to the present invention, there is an effect of providing a nonvolatile DRAM device capable of realizing high integration by removing the capacitor and a method of manufacturing the same.

1 is a three-dimensional view of a nonvolatile DRAM device according to an embodiment of the present invention. As shown in the figure, the nonvolatile DRAM device according to an embodiment of the present invention, the insulating layer 101 formed on the substrate 100, the floating body 102 formed on the insulating layer 101, floating body The cell 102 includes a source 103, a drain 104, and nonvolatile gate structures 105, 106, 107, and 108 formed on the cell 102 spaced apart from each other by channel lengths.

The substrate 100 uses a P-type semiconductor substrate in one embodiment of the present invention. However, the semiconductor substrate herein refers to a general material and may be made of any one of a silicon substrate, silicon germanium, tensile silicon, or tensile silicon germanium.

The insulating layer 101 refers to a layer made of a common oxide.

The floating body 102 may accumulate or expel holes in an area adjacent to the insulating layer 101, and may be adjacent to the upper portion of the floating body 102, that is, the nonvolatile gate structures 105, 106, 107, and 108. Channels between the source 103 and the drain 104 may be formed in the region.

The insulating layer 101 and the floating body 102 may be sequentially formed on the substrate 100, and the insulating layer 101 is formed inside the substrate so that the substrate is divided into three parts, that is, the substrate 100 and the insulating layer. It can be divided into 101 and the floating body (102). Here, the substrate on which the insulating layer 101 is formed is referred to as a silicon on insulator (SOI) substrate. Types of SOI substrates include PD Partially Depleted Silicon On Insulator (SOI) and Fully Depleted Silicon On Insulator (FD SOI) substrates. In one embodiment of the present invention, a PDSOI (Partially Depleted Silicon On Insulator) substrate is used in which the thickness of the floating body 102 is thicker than the maximum depletion width of the channel. The PD SOI substrate 100, 101, 102 is to provide a floating body 102 for accumulating holes.

Here, an ion implantation layer 101 made of germanium or a high dose P-type impurity ion may be formed in the substrate 100 instead of the insulating layer 101. The ion injection layer 101 may provide a floating body 102 capable of accumulating holes in an energy band. Because germanium has a narrower energy band gap and nearly the same conduction band than silicon, holes in the valence band may accumulate in the region adjacent to the germanium ion implantation layer in the floating body 102, and may have a high dose. In the case of high-dose P-type impurities, holes may accumulate in the region adjacent to the high-dose P-type impurity ion implantation layer even inside the floating body 102.

The nonvolatile gate structures 105, 106, 107, and 108 refer to gate structures including a control gate and a floating gate that traps electrons in the nonvolatile memory device. The nonvolatile gate structures 105, 106, 107, and 108 according to the embodiment of the present invention may include a tunneling insulating film 105 formed on the floating body 102 and a nanocrystal 106 formed on the tunneling insulating film 105. And a control insulating film 107 formed on the tunneling insulating film 105 and a gate 108 formed on the control insulating film 107. Nanocrystal 106 serves as a non-volatile electronic storage medium and the same as a conventional floating gate. The floating gate is not limited to the nanocrystal 106 layer, and any nanostructure in which the tunneling insulating film 105 and the control insulating film 107 formed by a subsequent process can be electrically distinguished is possible, and silicon oxide nitride oxide (SONOS) One of a nitride layer, a polysilicon layer, an amorphous silicon layer, a metal oxide layer, a silicon nitride layer, a silicon nanocrystalline layer, a metal nanocrystalline layer, or a metal oxide nanocrystalline layer forming a silicon or metal nitride oxide silicon (MMOS) structure Can be done. The tunneling insulating film 105 and the control insulating film 107 may be formed of any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a high-k metal oxide film.

According to an embodiment of the present invention, a method of manufacturing a nonvolatile DRAM device may include (a) forming a floating body capable of accumulating holes in a substrate, and (b) injecting electrons into a surface of the floating body. Forming a nonvolatile gate structure and (c) forming a source and a drain in the floating body. Hereinafter, with reference to the accompanying drawings will be described in detail.

2A to 2F are views illustrating a manufacturing process of a nonvolatile DRAM device according to an embodiment of the present invention.

As shown in FIG. 2A, the substrate 200 may use a P-type semiconductor substrate. However, the semiconductor substrate herein refers to a general material and may be formed of one of a silicon substrate, silicon germanium, tensile silicon, or tensile silicon germanium.

As shown in FIG. 2B, an insulating layer 201 is formed in the substrate 200. Herein, the insulating layer 201 is formed in the substrate 200 such that the thickness of the floating body 202 becomes a PD SOI (PDially Depleted Silicon On Insulator) substrate thicker than the maximum depletion width of the channel. By forming the insulating layer 201, the substrate 200 is divided into three parts, and an upper region of the insulating layer 201 is defined as a floating body 202 capable of accumulating holes.

In addition, a floating body 202 capable of accumulating holes may be defined by forming a germanium (Ge) or a high-dose P-type impurity ion implantation layer in the substrate 200.

As shown in FIG. 2C, a tunneling insulating film 205 is formed on the floating body 202. The tunneling insulating layer 205 may be formed of any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a high-k metal oxide film.

As shown in FIG. 2D, the nanocrystals 206 are formed on the tunneling insulating film 205 by a known method. The nanocrystal layer 206 may be formed of any one of a polysilicon layer, an amorphous silicon layer, a metal oxide layer, a silicon nitride film layer, a silicon nanocrystal layer, a metal nanocrystal layer, a silicon oxide nanocrystal layer, or a metal oxide nanocrystal layer. Can be.

As shown in FIG. 2E, the nanocrystal 206 is embedded to form the control insulating film 207 on the tunneling insulating film 205. The control insulating layer 207 may be formed of any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a metal oxide film having a high dielectric constant.

As shown in FIG. 2F, the gate 208 is formed on the control insulating layer 207, and the source 203 and the drain 204 are separated from each other by the channel length in the floating body 202. It is formed using a diffusion or implant process and subsequent heat treatment.

The nonvolatile DRAM device according to an embodiment of the present invention has the following characteristics, which will be described with reference to FIG. 3.

3 is a view showing a method of driving a nonvolatile DRAM device according to an embodiment of the present invention. As shown in FIG. 3A, a method of driving a nonvolatile DRAM device according to an embodiment of the present invention is a DRAM having no capacitor when power is supplied, and holes are accumulated or evicted in the floating body 302. DRAM mode step 309, which operates as a volatile memory, and when a power supply is stopped, electrons are injected or removed from a floating gate including nanocrystals of the nonvolatile gate structure to operate as a high speed nonvolatile memory. Step 310 is included.

The DRAM mode step 309 for driving the unit cell in the DRAM mode will be described in detail below with reference to FIG. 3B.

A, which is the accumulation of holes in the floating body cell, the lower the threshold voltage in a DRAM mode _{(V T. L1, V T} . H1) status information "1" (311a, 312a) as shown in Figure 3 (b) Appears when the drain voltage is very high in the saturation mode of a MOSFET on a PD SOI substrate. The reason is that the carriers in the channel get enough energy in the high field region near the drain, whereby impact ionization occurs to form electron-hole pairs, while the electrons thus produced exit to the drain, This is because the generated holes are driven to a low potential region. The PD SOI substrate has a floating source because the source and the drain respectively correspond to the emitter and the collector of the bipolar transistor, whereas the floating body corresponding to the base cannot be biased. Holes gather in the low-potential area of the floating body. And because of the perfect insulation between the silicon film and the substrate, these holes cannot be removed quickly. Therefore, the holes are stored in the floating body, which leads to a gradual increase in body potential due to the floating body effect, thereby lowering the threshold voltage.

And expelled the hole is stored in the floating body cell in the DRAM mode, increasing the threshold voltage _{(V T. L0, V T} . H0) status information "0" (311b, 312b) is the gate of the negative to positive voltage and the drain voltage to the That is, by applying a forward bias to the PN junction between the floating body and the drain, the holes are removed to the drain and removed. This principle is more effective in N-channel MOSFETs of P-type substrates because the collision ionization rate of electrons is higher than that of holes.

Meanwhile, in addition to the hole accumulation method through impact ionization, hole accumulation may be performed by a gate induced drain leakage (GIDL) effect due to a bias. If the ground voltage or negative voltage is applied to the gate, the ground voltage is applied to the source, and the positive voltage is applied to the drain, holes generated due to the interband tunneling due to the GIDL effect are concentrated and accumulated in the low potential region of the floating body. Applying a positive voltage to the gate, a ground voltage to the source, and a negative voltage to the drain deplete the holes in the low potential region of the floating body.

Here, the state of information "1" and the state of information "0" are sense amplification through a current sensing scheme having a high sensitivity since the difference ΔI _d of the amount of current to be sensed is minute. sense amplifier) is required.

Next, the nonvolatile memory mode step 310 of driving the unit cell in the nonvolatile memory mode will be described in detail with reference to FIG.

As shown in (b) of FIG. 3, when the power supply is stopped, the unit cell is operated by switching from the DRAM mode to the nonvolatile memory mode so that information is not lost.

A nonvolatile memory mode, applying a write voltage to the gate electrons are stored in the floating gate DRAM mode, as opposed to increasing the threshold voltage _{(V T. H0, V T} . H1) status information "0" (312a, 312b) and applying a voltage to the erase gates out the electrons stored in the floating gate escape divided into lowered the threshold voltage (V _{T. L0,} V _{T. L1)} state (311a, 311b) of the information "1". Here, the information "1" and information "0" state of the current change is larger than when operating in the DRAM mode, it is possible to sense amplification through a less sensitive current sensing scheme.

On the other hand, the floating body should be refreshed through a purge operation, in which the hole is in an information state through the reverse-bias leakage current of the PN junction between the floating body and the source / drain. Is generated in the floating body with information " 0 ". As a result, in order to keep the difference in the number of holes between the information " 1 " and the information " 0 ", the holes must be ejected from the floating body through the purge operation before all the write operations. To this end, a positive voltage is applied to the gate to lower the potential barrier, thereby eliminating holes accumulated in the floating body.

As described above, the nonvolatile DRAM device of the present invention may perform an operation of switching to one of the DRAM mode and the nonvolatile memory mode according to a power supply situation and a required operating speed.

 4 is a three-dimensional view of a nonvolatile DRAM device according to another embodiment of the present invention. As shown in the figure, the nonvolatile DRAM device according to another embodiment of the present invention has a thickness of the floating body 402 smaller than the maximum depletion width of the channel when compared to the nonvolatile DRAM device of FIG. 1 described above. The insulating layer 401 is formed in the substrate 400, and further includes a back gate 408b formed under the substrate 400. Here, the structure of the floating body 402 whose thickness is smaller than the maximum depletion width of the channel is referred to as FD SOI. In this FD SOI structure, the barrier at the junction of the source 403 and the floating body 402 prevents the accumulation of holes. As a result, the Floating Body Effect does not appear. However, when the back gate 408b is provided under the substrate 400 and a negative voltage is applied to the back gate 408b, a negative bias provides a potential well to accumulate holes in the floating body 402. On the other hand, applying a ground voltage or a positive voltage to the back gate 408b may reduce the depth of the potential well and thereby eject the hole.

The method of manufacturing the nonvolatile DRAM device according to another embodiment of the present invention is similar to the method of manufacturing the nonvolatile DRAM device illustrated in FIGS. 2A to 2F, and the difference is that of the floating body 402. The thickness of the FD SOI structure is smaller than the maximum depletion width of the channel, and the back gate 408b is further formed under the substrate 400.

Therefore, even if the nonvolatile DRAM device according to another embodiment of the present invention has an FD SOI structure, the DRAM mode operation through a hole accumulated / extracted in a floating body like the nonvolatile DRAM device according to an embodiment of the present invention described above. And nonvolatile memory mode operation through electrons injected into and erased from the nonvolatile gate structure.

5 is a three-dimensional view of a nonvolatile DRAM device according to another embodiment of the present invention. As shown in FIG. 5, the nonvolatile DRAM device according to another embodiment of the present invention has a floating structure in which the floating body 502 is not a planar structure when compared to the nonvolatile DRAM device of FIG. 1. It is formed of a fin structure (or a three-dimensional vertical structure), and the fin structure can improve the channel control capability of the gate 508 because the gate 508 surrounds the channel region three-dimensionally on three surfaces. have. Therefore, the short-channel effect, which is the limit of the planar device, can be effectively reduced, and the physical size of the device can be further reduced. In addition, as described above with reference to the nonvolatile DRAM device of FIG. 1, a DRAM mode operation and a nonvolatile memory mode operation through electrons injected / erased into the nonvolatile gate structure may be performed.

A method of manufacturing a nonvolatile DRAM device according to still another embodiment of the present invention will be described below with reference to FIG. 6.

6A to 6F are cross-sectional views illustrating a method of forming a nonvolatile DRAM device according to still another embodiment of the present invention according to a manufacturing process sequence. The direction of the cross section is the II 'direction in FIG. As shown in FIG. 6A, a P-type semiconductor substrate 600 was used as the substrate 600. However, the semiconductor substrate 600 refers to a general material, and may be formed using any one of a silicon substrate, silicon germanium (SiGe), strained silicon, or tensile silicon germanium.

As illustrated in FIG. 6B, a germanium (Ge) or high-dose P-type impurity ion implantation layer 601 is formed in the substrate 600. In addition, an insulating layer can be formed inside the substrate.

As shown in FIG. 6C, the floating body of the fin structure (three-dimensional vertical type) is patterned by patterning the upper region of the substrate 600 defined by the formation of the ion implantation layer 601. Cell 602 is formed. The floating body 602 has a top surface and a side surface, which are used as channel regions. The lower end of the outer side of the floating body 602 is surrounded by Shallow Trench Isolation (STI) 611 and insulated from other adjacent cells. Subsequently, a tunneling insulating film 605 is formed on the substrate 600 and the floating body 602. The tunneling insulating film 605 may be formed of any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a metal oxide film.

As shown in FIG. 6D, the nanocrystal layer 606 represented by the floating gate is formed on the tunneling insulating film 605 by using a known method. The nanocrystalline layer 606 may be any nanostructure that can be electrically distinguished from the tunneling insulating film 605 and the control insulating film 607 formed by a subsequent process, and may be polysilicon, amorphous silicon, metal oxide, silicon nitride, It can be formed of any one of silicon nanocrystals, metal nanocrystals, silicon oxide nanocrystals or metal oxide nanocrystals.

As shown in FIG. 6E, the control insulating film 607 is formed on the nanocrystal layer 606 and the tunneling insulating film 605. The control insulating layer 707 may be formed of any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a metal oxide film.

As shown in FIG. 6F, the control gate 608 is formed on the control insulating layer 607, and the control gate (eg, through a diffusion or implantation process of an N-type impurity ion or a subsequent heat treatment) is used. 608, a source (not shown) and a drain 604 spaced apart by the channel region are formed.

7 is a three-dimensional view of a nonvolatile DRAM device according to another embodiment of the present invention. As shown in the drawing, in the nonvolatile DRAM device according to another embodiment of the present invention, the thickness of the floating body 702 is smaller than the maximum depletion width of the channel when compared with the nonvolatile DRAM device of FIG. FD SOI structure), the gate structures 705, 706, 707, and 708a are formed at one side of the floating body 702, not at the top, and the back gate 708b is formed at the other side. Like the nonvolatile DRAM device of FIG. 5 described above, the DRAM mode operation through accumulation / ejection of holes by the back gate 708b and the nonvolatile memory mode operation through electrons injected / erased into the nonvolatile gate structure are performed. It is possible.

The manufacturing method of the nonvolatile DRAM device according to another exemplary embodiment of the present invention is similar to the manufacturing method of FIGS. 6A to 6F. The difference is that the thickness of the floating body 702 forms an FD SOI structure that is thinner than the maximum depletion width of the channel. The floating gate 706 and the control insulating film 707, including the tunneling insulating film 705, which are electron storage structures, are floating. It is formed on one side of the body cell 702 and the back gate 708b is formed on the other side of the floating body 702. Although not shown, the unit cell is surrounded by Shallow Trench Isolation (STI) to insulate the adjacent cell.

8 is a three-dimensional view of a nonvolatile DRAM device according to another embodiment of the present invention. As shown in the drawing, the nonvolatile DRAM device of the present invention has the same gate structures 805b and 806b as those formed on one side instead of the back gate 708b on the other side, compared to the nonvolatile DRAM device of FIG. 807b and 808b) are formed. As shown in FIG. 8, the roles of the gate 708b on one side and the back gate 708b on the other side can be used interchangeably, and this structure is also injected into the DRAM mode operation and the nonvolatile gate structure. Nonvolatile memory mode operation via electronics is removed.

A method of manufacturing a nonvolatile DRAM device according to still another embodiment of the present invention is similar to the nonvolatile DRAM device illustrated in FIG. 7. The difference is the floating gates 806a and 806b, the control insulating films 807a and 807b and the gates 808a and 808b, including the tunneling insulating films 805a and 805b, which are nonvolatile gate structures, on one side and the other side of the floating body 802. ). Although not shown, the unit cell is surrounded by Shallow Trench Isolation (STI) to insulate the adjacent cell.

9 is a view for explaining a nonvolatile DRAM device according to another embodiment of the present invention. As shown in FIG. 9, in the nonvolatile DRAM device according to another embodiment of the present invention, the nonvolatile gate structure includes a tunneling insulating film 905, a carbon nanotube 906, an insulating film 907, and a blocking insulating film. 908 and gate 909.

The tunneling insulating film 905 is formed on the floating body 902.

Carbon nanotubes 906 are formed vertically on the tunneling insulating film 905. Here, the carbon nanotube 906 serves as a non-volatile electron storage medium and the same as a conventional floating gate. The carbon nanotube 906 is a carbon allotrope made of carbon present in a large amount on the earth, and is a material in which one carbon is combined with another carbon atom in a hexagonal honeycomb pattern to form a tube. And the diameter of the tube is a very small area of nanometer (nm = 1 billion meters). The shape of the carbon nanotubes 106 has a graphite sheet rounded to a nano size diameter and has a sp2 bonding structure. Depending on the angle and shape in which the graphite surface is curled, it exhibits the properties of a conductor or a semiconductor. The carbon nanotubes 906 are divided into single-walled nanotubes or multi-walled nanotubes according to the number of bonds forming a wall, and the single-walled nanotubes are clustered into several. The shape that is present is called a bundle nanotube. Since the carbon nanotubes 906 have excellent mechanical properties, electrical selectivity, excellent field emission characteristics, and high efficiency hydrogen storage medium characteristics, the carbon nanotubes 906 are used in various fields such as aerospace, biotechnology, environmental energy, materials industry, and pharmaceutical industry. The range of applications is widening. In particular, research is being actively conducted in the nanotechnology industry, which is a high-tech industry.

Here, by adopting one of the single-walled carbon nanotube (single-walled carbon nanotube) or the single-stranded multi-walled carbon nanotube to the carbon nanotube 906 trapping electrons, It may be formed perpendicular to the tunneling insulating film 906.

The insulating film 907 is formed on the tunneling insulating film 905 by filling the carbon nanotubes 906. The insulating film 907 prevents electrons trapped in the carbon nanotubes 906 from moving to other carbon nanotubes. The insulating film 907 is a silicon oxide (SIO _2), insulating material that does not show a memory characteristic, aluminum oxide (Al ₂ O _3), zirconium oxide (ZrO _2), zirconium silicates (Zr silicate), hafnium oxide (HfO ₂ ) Or hafnium silicate.

The blocking insulating film 908 is formed on the insulating film 907. This blocking insulating film 908 prevents charge supplied from the channel between the source 903 and the drain 904 from moving to the gate 909.

The gate 909 is formed on the blocking insulating film 908.

As described above, in the nonvolatile DRAM device according to another embodiment of the present invention, a plurality of carbon nanotubes that accumulate charge are formed on the tunneling insulating film 905 discretely. As the memory device shrinks, the loss of dielectric defects, which may occur due to the reduction in the thickness of the tunneling insulating film 905 or the insulating film 907, may be further reduced than in the conventional memory device. This reduction in dielectric defects can further reduce the size of the nonvolatile DRAM device.

In addition, since there is no dangling bond between the carbon nanotubes 906 and the insulating film 907, the surfaces have defect-free surface states, and thus the charge retention time is seen. It can be further extended than the nonvolatile DRAM device according to another embodiment of the present invention.

In addition, since the carbon nanotubes 906 are vertically formed on the tunneling insulating film 905, the maximum flat band voltage variation can be obtained. It can be lower than the operating voltage applied by the nonvolatile DRAM device according to.

In addition, it is possible to prevent a parallel hopping phenomenon that may occur in a memory device using a quantum dot as a charge storage unit. The parallel hopping phenomenon refers to one of the main mechanisms by which charge stored in a trapped memory device causes discharge.

As described above, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

1 is a three-dimensional view of a nonvolatile DRAM device according to an embodiment of the present invention.

2 is a view illustrating a manufacturing process of a nonvolatile DRAM device according to an embodiment of the present invention.

3 is a view for explaining a method of driving a nonvolatile DRAM device according to an embodiment of the present invention.

4 is a three-dimensional view of a nonvolatile DRAM device according to another embodiment of the present invention.

5 is a three-dimensional view of a nonvolatile DRAM device according to another embodiment of the present invention.

6 is a view illustrating a manufacturing process of a nonvolatile DRAM device according to another embodiment of the present invention.

7 is a three-dimensional view of a nonvolatile DRAM device according to another embodiment of the present invention.

8 is a three-dimensional view of a nonvolatile DRAM device according to another embodiment of the present invention.

9 is a cross-sectional view of a nonvolatile DRAM device according to still another embodiment of the present invention.

***** Description of the symbols for the main parts of the drawings *****

100: substrate

101: insulating layer or ion implantation layer

102: floating body

103: source

104: drain

105: tunneling insulating film

106: nanocrystal or floating gate

107: control insulating film

108: gate

Claims (22)

An insulating layer formed on the substrate; A floating body formed on the insulating layer; Source and drain formed on left and right sides of the floating body; And Nonvolatile gate structure formed on the surface of the floating body Non-volatile DRAM device comprising a. The method of claim 1, And a back gate formed under the substrate. An ion implantation layer formed on the substrate; A floating body cell formed on the ion implantation layer; Source and drain formed on left and right sides of the floating body; And Nonvolatile gate structure formed on the surface of the floating body Non-volatile DRAM device comprising a. The method of claim 3, wherein The ion implantation layer, A nonvolatile DRAM device which is a germanium (Ge) or high-dose P-type impurity ion implantation layer. The method according to claim 1 or 3, The floating body is a non-volatile DRAM device formed of a fin (Fin) structure. The method of claim 5, And a non-volatile gate structure formed on one side of the floating body, and a back gate formed on the other side of the fin structure. The method of claim 5, The nonvolatile gate structure is formed on one side of the floating body, the nonvolatile gate structure is formed on the other side of the fin structure. The method according to claim 1 or 3, The nonvolatile gate structure A nonvolatile DRAM device comprising a tunneling insulating film, a floating gate, a control insulating film, and a gate. The method of claim 8, The floating gate is Polysilicon layer, nitride layer, amorphous silicon layer, metal oxide layer, silicon nitride layer, silicon nanocrystal layer forming a silicon-oxide-nitride-oxide-silicon (SONOS) or metal-nitride-oxide-silicon (MNOS) structure Non-volatile DRAM device, a metal nanocrystalline layer or a metal oxide nanocrystalline layer. (a) forming a floating body capable of accumulating holes in the substrate; (b) forming a nonvolatile gate structure capable of injecting electrons into the surface of the floating body cell; And (c) forming a source and a drain in the floating body Method of manufacturing a nonvolatile DRAM device comprising a. The method of claim 10, In step (a), And forming the floating body by forming an insulating layer in the substrate. The method of claim 10, In step (a), A method of manufacturing a nonvolatile DRAM device in which germanium (Ge) or a high-dose P-type impurity is formed in the substrate to form an floating injection cell. The method of claim 10, In step (b), Forming a tunneling insulating layer on a surface of the floating body cell; Forming a floating gate on the tunneling insulating film; Forming a control insulating film on the floating gate and the tunneling insulating film; And Forming a gate on the control insulating film Method of manufacturing a nonvolatile DRAM device comprising a. The method of claim 13, The floating gate is Polysilicon layer, nitride layer, amorphous silicon layer, metal oxide layer, silicon nitride layer, silicon nanocrystal layer forming a silicon-oxide-nitride-oxide-silicon (SONOS) or metal-nitride-oxide-silicon (MNOS) structure Method for producing a nonvolatile DRAM device, which is a metal nanocrystalline layer or a metal oxide nanocrystalline layer. The method of claim 10, And forming a back gate under the substrate. The method of claim 10, Step (a) is Forming a germanium or high dose P-type impurity ion implantation layer in the substrate; And Patterning the upper portion of the substrate separated by the ion implantation layer to form the floating body having a fin structure Method of manufacturing a nonvolatile DRAM device comprising a. The method of claim 10, In step (b), Forming the nonvolatile gate structure on one side of the floating body; And Forming a back gate on the other side of the floating body Method of manufacturing a nonvolatile DRAM device comprising a. The method of claim 10, Step (b) is Forming the nonvolatile gate structure on one side of the floating body; And Forming the nonvolatile gate structure on the other side of the floating body Method of manufacturing a nonvolatile DRAM device comprising a. In the method of driving a nonvolatile DRAM device according to claim 1 or 3, A DRAM mode step of accumulating or extracting holes in the floating body; And A nonvolatile memory mode step of injecting or erasing electrons into the floating gate formed inside the nonvolatile gate structure A method of driving a nonvolatile DRAM device comprising a. The method of claim 19, The DRAM mode step A method of driving a nonvolatile DRAM device, wherein the holes are accumulated or expelled in the floating body by a gate induced drain leakage effect. The method according to claim 1 or 3, The nonvolatile gate structure, A tunneling insulating layer formed on the floating body; Carbon nanotubes vertically formed on the tunneling insulating layer; An insulating film formed on the tunneling insulating film by filling the carbon nanotubes; A blocking insulating film formed on the insulating film; And A gate formed on the blocking insulating layer Non-volatile DRAM device comprising a. The method of claim 21, The carbon nanotubes, Non-volatile DRAM device, which is a single-stranded single-walled carbon nanotube or a single-stranded multi-walled carbon nanotube.

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