KR20080081595A - Bake unit of semiconductor device manufacturing apparatus - Google Patents

Bake unit of semiconductor device manufacturing apparatus Download PDF

Info

Publication number
KR20080081595A
KR20080081595A KR1020070021843A KR20070021843A KR20080081595A KR 20080081595 A KR20080081595 A KR 20080081595A KR 1020070021843 A KR1020070021843 A KR 1020070021843A KR 20070021843 A KR20070021843 A KR 20070021843A KR 20080081595 A KR20080081595 A KR 20080081595A
Authority
KR
South Korea
Prior art keywords
unit
baking
wafer
bake
upper chamber
Prior art date
Application number
KR1020070021843A
Other languages
Korean (ko)
Inventor
정명화
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020070021843A priority Critical patent/KR20080081595A/en
Publication of KR20080081595A publication Critical patent/KR20080081595A/en

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/168—Finishing the coated layer, e.g. drying, baking, soaking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67248—Temperature monitoring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B1/00—Details of electric heating devices
    • H05B1/02—Automatic switching arrangements specially adapted to apparatus ; Control of heating devices
    • H05B1/0227—Applications
    • H05B1/023—Industrial applications
    • H05B1/0233—Industrial applications for semiconductors manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

The present invention relates to a baking unit applied to a photolithography process. In the present invention, in implementing the baking unit for baking the photoresist applied on the wafer, it is characterized in that the shutter unit is formed up / down by the driving unit in the baking unit. By closing the open space between the upper chamber and the lower chamber by using the shutter unit, it is possible to solve the level misalignment of the upper chamber to maintain a uniform temperature inside the baking unit. In addition, in the prior art, a large amount of particles were generated due to wear of the cylinder in the process of up / down the heavy chamber by using the cylinder. However, by sealing the inside of the baking unit using a light shutter as in the present invention, This particle generation problem can be minimized.

Description

Bake unit of semiconductor device manufacturing apparatus

1 shows an inline systemized photolithography apparatus to which a bake unit is applied according to an embodiment of the present invention.

2 shows a planar structure of a bake unit according to a preferred embodiment of the present invention.

3 and 4 show the cross-sectional structure of the baking unit.

5 shows a perspective structure of a shutter unit applied to a preferred embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100: bake unit 102: upper chamber

104: lower chamber 106: baking plate

108: guide pin 110: lift pin

112: lift 114: shutter unit

116: drive unit 118: heating wire

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing facility, and more particularly, to a baking unit for baking a photoresist on a wafer during a photolithography process.

In general, semiconductor devices are manufactured by depositing and patterning thin films that perform various functions on the wafer surface to form various circuit geometries. The unit process for manufacturing such a semiconductor device is mainly an impurity ion implantation process of implanting impurity ions of Group 3B (eg B) or 5B (eg P or As) into the semiconductor substrate, insulating or A thin film deposition process for forming a conductive material film, an etching process for forming a material film formed through the thin film deposition process in a predetermined pattern, and an interlayer insulating film, etc., are deposited on the semiconductor substrate and then polished in a batch to remove the step. It can be divided into several unit processes such as chemical mechanical polishing (CMP) process and cleaning process to remove contaminants in the process chamber including wafers.

On the other hand, with the recent rapid development of the information communication field and the rapid popularization of information media such as computers, semiconductor devices are also rapidly developing. As a result, it is required to operate at a high speed and have a large storage capacity in terms of its functional aspects, and thus the degree of integration of semiconductor devices is gradually increasing. In addition, as the degree of integration of semiconductor devices increases, the size of circuit patterns is further reduced. Thus, the management of various process parameters affecting the size of the fine pattern is becoming more stringent.

Among the various unit processes described above, the etching process is one of the most frequently performed processes for manufacturing semiconductor devices. In particular, the photolithography process is a representative example of an etching process that forms a pattern on a material film deposited on the wafer according to a mask image using a positive or negative photoresist. As a semiconductor device is increasingly integrated, it requires the highest precision. It is becoming. The photolithography process is a key process that directly affects the size of the fine pattern, and how sharp and fine the image of the reticle (photo mask) is formed, as well as the pattern of the material layer deposited on the wafer according to the image of the reticle. The capability of the process is assessed according to how well the patterned pattern has a good profile.

The photolithography process is roughly a photoresist coating step of applying a photoresist on a wafer, and aligning the wafer on which the photoresist is applied with a mask, and then passing light such as ultraviolet rays through a mask to mask the photoresist. And an exposure step of transferring the photoresist of the wafer on which the exposure step is completed, to form a pattern. In addition, in a conventional photolithography process, a bake process and a photolithography process for curing the photoresist before and after the exposure process together with a hexamethyl disilazane (HMDS) treatment process for improving adhesion between the photoresist and the wafer. A cooling process is further included to cool the completed wafer. Accordingly, the photolithography apparatus for performing the photolithography process is provided with a plurality of processing units for applying, baking, exposing, developing, and cooling the photoresist.

In particular, the baking process is performed through a chamber-type baking unit that loads the photoresist-coated wafer on a plate provided in the chamber, and then heats the plate to a predetermined temperature to bake the photoresist of the wafer. More specifically, the wafer on which the photoresist is applied is transferred onto the baking plate by the transfer robot. Then, the spin of the baking plate is raised to support the wafer. Subsequently, the spin is lowered to load the wafer on the baking plate, whereby the baking process proceeds.

At this time, in order to load the wafer onto the baking plate, the chamber is opened / closed by an up / down driving of the cylinder. However, there is a case where the level of the upper chamber is distorted due to the poor driving of the cylinder. The driving failure of the cylinder is intensified as the chamber weight of the bake unit increases, and as the size of the wafer has recently increased from 8 inches to 12 inches, the size of the bake unit increases to increase the size and weight of the chamber. have. Therefore, the load applied to the cylinder is increased, and as a result, the shaft is bent and the driving failure of the cylinder is intensified.

As such, when the level of the upper chamber is misaligned, the bake unit is not completely sealed and the temperature inside the bake unit is not kept uniform throughout. This prevents even heat treatment of the wafer loaded on the bake plate, resulting in undevelopment where the photoresist cannot be partially developed, or the characteristic of CD (Critical Demension) which indicates the width of the developing site after development. Is lowered.

At present, the above-described level failure of the upper chamber is resolved depending on the visual confirmation and manual work of the engineer. However, there is a limit to precise level control depending on the visual confirmation and manual work of the engineer, and there is a fear that a slight level defect cannot be caught by the engineer's naked eye. In addition, the individual differences between each engineer make it difficult to maintain the uniformity of the upper chamber level.

In addition, if the upper chamber of heavy load is forcibly up / down, the cylinder is worn and particles are generated. These particles not only contaminate the inside of the bake unit but also contaminate the wafer, resulting in a decrease in the reliability and productivity of the semiconductor device.

SUMMARY OF THE INVENTION An object of the present invention for solving the above conventional problems is to provide a bake unit of a semiconductor device manufacturing apparatus for maintaining the temperature inside the bake unit uniformly.

Another object of the present invention is to provide a baking unit of a semiconductor device manufacturing apparatus that can evenly bake the entire wafer area to eliminate undevelopment and CD characteristic degradation.

Another object of the present invention is to provide a baking unit of a semiconductor device manufacturing apparatus capable of minimizing particle generation.

Another object of the present invention is to provide a bake unit of a semiconductor device manufacturing apparatus which can prevent a decrease in reliability and productivity of a semiconductor semiconductor device.

The baking unit of the semiconductor device manufacturing apparatus according to the present invention for achieving the above objects, the wafer plate is loaded; A lower chamber in which the baking plate is formed; An upper chamber spaced apart from the lower chamber by an interval for wafer transfer; And a shutter configured to be lifted toward the upper chamber by an operation of the driving unit to seal a space between the lower chamber and the upper chamber.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. The present invention is not limited to the embodiments disclosed below, but can be embodied in other various forms without departing from the scope of the present invention, and only the embodiments allow the disclosure of the present invention to be complete and conventional It is provided to fully inform the knowledge of the scope of the invention.

The present invention relates to a baking unit that performs a baking process during a photolithography process, and FIG. 1 shows an inline systemized photolithography apparatus 10 to which a baking unit according to an embodiment of the present invention is applied.

Referring to FIG. 1, an exposure apparatus 12 in which an exposure process is performed and a spinner apparatus 16 in which a photoresist coating process and a developing process are performed are connected with an interface block 14 interposed therebetween.

The spinner device 16 includes several units, for example, a cassette for temporarily storing a wafer of a lot unit (25 wafers), a coater (or spinner) for applying photoresist on the wafer. spinner)), a post exposure bake (PEB) for first baking the exposed photoresist on the wafer, a developer for developing the exposed photoresist on the wafer, and the development is completed through the developer. Hard Bake (HB), which hardens the photoresist on the wafer, and a cooling plate (CP) for cooling the wafer heated at a high temperature (110 ° C.) at the post exposure bake and the hard bake at 23 ° C. Cool Plate) and a transfer robot (ROBOT) for transferring the wafer to the above-mentioned units.

Looking briefly at the photolithography process through the inline system, an engineer first loads a wafer on the spinner equipment 16 and then applies a photoresist on the wafer using the coater of the spinner equipment 16. When the photoresist coating process using the coater is completed, the wafer is transferred to the exposure equipment 12 via the interface block 14 while being seated on the transfer robot. Then, the wafer subjected to the exposure process through the exposure equipment 12 is transferred to the spinner device 16 via the interface block 14 in a state of being seated on the transfer robot again to proceed with the development process. As such, the wafer loaded into the photolithography apparatus 10 of the inline system structure is unloaded from the photolithography apparatus 10 after the application-exposure-development process is completed in turn.

In the present invention, in the inline systemized photolithography apparatus 10 as described above, in particular, the hard baking process or the soft baking process loads a photoresist-coated wafer on a baking plate provided in the process chamber, The bake plate is heated through a chamber baking unit for baking a photoresist of a wafer by heating to a predetermined temperature.

However, in sealing the inside of this baking unit, the upper chamber was conventionally used up / down using the cylinder. However, when the cylinder is used to up / down the upper chamber, the cylinder may cause a driving failure due to the load of the upper chamber. As a result, the level of the upper chamber is distorted, so that the temperature inside the baking unit is not kept uniform throughout. There was a problem that prevented. As such, when the level of the upper chamber is misaligned and the temperature inside the bake unit is not maintained uniformly, even heat treatment of the wafer loaded on the bake plate cannot be performed, resulting in a process failure.

Accordingly, the present invention has been derived a bake unit of improved structure that can solve the above-mentioned conventional problems. Then, the baking unit of the improved structure according to the present invention will be described in detail with reference to the following drawings.

2 shows a planar structure of the bake unit 100 according to a preferred embodiment of the present invention. 3 and 4 illustrate a cross-sectional structure of the baking unit 100.

First, referring to FIG. 2, a bake plate 106 in which a wafer is loaded is formed in the bake unit 100. In the center region of the bake plate 106, a wafer transferred through a transfer robot is supported to load the wafer on the bake plate 106 or to unload the wafer from which the baking process is completed from the bake plate 106. The lift pin 110 is formed. In addition, a guide pin 108 is formed in the edge region of the baking plate 106 to prevent sliding of the loaded wafer to prevent sliding. Although not shown in the drawings, a heat generating part for heating the bake plate to a predetermined temperature is built in the bake plate 106.

In addition, as a key component of the baking unit 100 according to the present invention, the shutter unit 114 is formed on the outer circumferential surface of the baking plate 106. The shutter unit 114 has a ring shape surrounding the bake plate 106. In addition, the shutter unit 114 performs a function of blocking the space between the bake plate 106 and the upper chamber of the bake unit 100 from the outside by being up / down by cylinder driving.

As such, in the present invention, the upper chamber of the baking unit 100 is fixed to the shutter unit 114 in the fixed state to block the baking unit 100 from the outside. Therefore, it is possible to solve the problem that the level of the upper chamber under heavy load is shifted and the temperature uniformity inside the bake unit is lowered, and the driving failure of the cylinder for up / down the upper chamber is solved.

3 and 4, the structure of the baking unit 100 and the driving process of the shutter unit 114 according to an exemplary embodiment of the present invention will be described in detail.

Referring to FIG. 3, the bake unit 100 is composed of an upper chamber 102 and a lower chamber 104. Here, the upper chamber and the lower chamber are separated from each other at predetermined intervals, as indicated by reference numeral A, for wafer transfer. In addition, the distance between the upper chamber and the lower chamber is preferably minimized within a range in which wafer transfer is possible in order to prevent heat loss inside the bake unit 100.

A baking plate 106 is formed in the lower chamber to load a wafer. In addition, a guide pin 108 is formed in the edge region of the baking plate 106 to prevent sliding of the loaded wafer to prevent sliding. In the center region of the bake plate 106, a wafer transferred through a transfer robot is supported to load the wafer on the bake plate 106 or to unload the wafer from which the baking process is completed from the bake plate 106. A lift pin 110 is formed, and a lift 112 for raising the lift pin 110 is formed below the lift pin 110. Although not shown in the drawings, a heat generating part for heating the bake plate to a predetermined temperature is built in the bake plate 106.

In addition, as a key component of the baking unit 100 according to the present invention, a ring-shaped shutter portion 114 surrounding the baking plate 106 is formed on the outer circumferential surface of the baking plate 106. In addition, a driving unit 116 is formed at the lower end of the shutter unit 114 to up / down the shutter unit 114. Here, the drive unit 116 may be implemented as a cylinder of the air compression method.

Therefore, when the driving unit 116 is operated to raise the shutter unit 114, the wafer transfer space between the lower chamber 104 and the upper chamber 102 is blocked from the outside. 4 illustrates a state in which the shutter unit 114 is raised.

Referring to FIG. 4, the driving unit 116 is operated to raise the shutter unit 114 from the bake plate 106 to the upper chamber 102. As a result, the space between the lower chamber 104 and the upper chamber 102, that is, the space held for transporting the wafer, is blocked from the outside to create a baking process atmosphere.

As such, when the space between the lower chamber 104 and the upper chamber 102 is blocked from the outside, the baking plate 106 is heated to a predetermined temperature by using a heat generating part formed inside the baking plate 106. Then, the photoresist film of the wafer loaded on the baking plate 106 is baked. In this case, in order to more efficiently control the temperature inside the baking unit 100, as shown in FIG. 5, a heating wire 118 may be further formed on the shutter unit 114. In this case, the number or shape of the heat lines 118 may be implemented in various ways.

Subsequently, after the baking process for the wafer is completed, the driving unit 116 is operated to lower the shutter unit 114 as shown in FIG. 3.

Conventionally, the baking unit is sealed by lowering the upper chamber to form a baking process atmosphere. However, as the wafer diameter gradually increased, the size of the bake unit increased, thereby gradually increasing the load of the upper chamber. Therefore, a driving failure occurs in a cylinder for up / down of the upper chamber, and the level of the upper chamber is distorted, so that the baking unit is not completely sealed, and thus the temperature inside the baking unit is not kept uniform. As a result, even heat treatment is not performed on the wafer loaded on the bake plate, so that undeveloped photoresist cannot be partially developed, or CD (Critical Demension) indicating the width of the developing site after development. There was a problem that the characteristics are degraded. In addition, in the process of forcibly up / down the heavy load of the upper chamber, the cylinder was worn and particles were generated. These particles not only contaminated the inside of the baking unit but also contaminated the wafer, and as a result, it was analyzed as a major cause of deterioration of the reliability and productivity of the semiconductor device.

Accordingly, in the present invention, in order to solve the above-mentioned conventional problems, a shutter unit is formed in the baking unit that performs the baking process to seal the space between the lower chamber and the upper chamber. In addition, the space between the lower chamber and the upper chamber is sealed by up / down the shutter unit instead of the method of up / down the upper chamber as in the related art, thereby raising and lowering the level chamber of the upper chamber and the upper chamber. Particle generation due to wear of the cylinder can be eliminated.

As such, by blocking the processing space inside the baking unit from the outside by using the shutter unit, the temperature inside the baking unit is maintained to be uniform throughout so that a smooth baking process can be performed. In addition, when the hot wire is embedded in the shutter unit, the temperature inside the bait unit is more accurately managed, which can help to improve the reliability and productivity of the semiconductor device.

In the above, the shutter unit for sealing the processing space has been described with reference to the baking unit used in the photolithography process. However, the bake unit is only one exemplary semiconductor device manufacturing apparatus presented to describe the shutter unit according to an embodiment of the present invention, and may be applied to other semiconductor device manufacturing apparatuses that require a processing space sealing process in addition to the baking unit. Of course, it is possible to apply and try the appropriate application and modification.

As described above, in the present invention, an open space between the upper chamber and the lower chamber is sealed by forming a shutter unit which is up / down by the driving unit inside the baking unit. As such, when the inside of the bake unit is blocked from the outside by using the shutter unit, the problem of level misalignment of the upper chamber is solved at the source to maintain the temperature inside the bake unit uniformly. In addition, it is possible to further improve the reliability and productivity of the semiconductor device by eliminating the conventional problem in which particles are generated due to wear of the cylinder for up / down the upper chamber.

Claims (8)

In the baking unit of the semiconductor device manufacturing apparatus for baking the photoresist applied on the wafer: A baking plate onto which a wafer is loaded; A lower chamber in which the baking plate is formed; An upper chamber spaced apart from the lower chamber by an interval for wafer transfer; And And a shutter unit which is lifted to the upper chamber side by an operation of a driving unit and seals a space between the lower chamber and the upper chamber. The bake unit of claim 1, wherein the shutter unit is positioned on an outer circumferential surface of the bake plate when lowered. 3. The baking unit of claim 2, wherein the shutter unit has a ring shape. 4. The baking unit of claim 3, wherein a heat wire is built in the shutter unit. 5. The baking unit of claim 4, wherein a guide pin is formed in an edge region of the baking plate to prevent wafer sliding. 6. The bake unit of claim 5, wherein a lift pin is formed at a center region of the bake plate to support the wafer during wafer loading and unloading. 7. The baking unit of claim 6, wherein a heat generating portion for heating the baking plate is formed inside the baking plate. 8. The baking unit of claim 7, wherein the upper chamber and the lower chamber are spaced apart from each other by a minimum distance for transferring the wafer.
KR1020070021843A 2007-03-06 2007-03-06 Bake unit of semiconductor device manufacturing apparatus KR20080081595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070021843A KR20080081595A (en) 2007-03-06 2007-03-06 Bake unit of semiconductor device manufacturing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070021843A KR20080081595A (en) 2007-03-06 2007-03-06 Bake unit of semiconductor device manufacturing apparatus

Publications (1)

Publication Number Publication Date
KR20080081595A true KR20080081595A (en) 2008-09-10

Family

ID=40021259

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070021843A KR20080081595A (en) 2007-03-06 2007-03-06 Bake unit of semiconductor device manufacturing apparatus

Country Status (1)

Country Link
KR (1) KR20080081595A (en)

Similar Documents

Publication Publication Date Title
JP4527670B2 (en) Heat treatment apparatus, heat treatment method, control program, and computer-readable storage medium
US8697187B2 (en) Coating treatment method and coating treatment apparatus
JP2020027915A (en) Pressing condition correction method and substrate processing system
KR100629255B1 (en) Bake unit for semiconductor photolithography process
KR102573014B1 (en) Film forming method, storage medium, and film forming system
KR102516725B1 (en) bake apparatus a having the unit and method processing substrate by using thereof
KR20080081595A (en) Bake unit of semiconductor device manufacturing apparatus
JP2003158061A (en) Substrate processing apparatus and substrate processing method
TW201842582A (en) Film forming system, film forming method, and computer storage medium
JP7291515B2 (en) SUBSTRATE PROCESSING SYSTEM, SUBSTRATE PROCESSING METHOD, STORAGE MEDIUM, AND CONTROL DEVICE FOR SUBSTRATE PROCESSING SYSTEM
KR100809966B1 (en) apparatus for manufacturing semiconductor device and level sensing method the same
US20120070564A1 (en) Bake Plate Exhaust Monitor
KR100741578B1 (en) Hot plate of track coater and temperature control method for semiconductor manufacturing
KR102099103B1 (en) Method for cooling hot plate and Apparatus for treating substrate
TWI784143B (en) Heat treatment device and heat treatment method
KR20070000686A (en) Wafer lifting apparatus of semiconductor device manufacturing equipment
KR20030024168A (en) A bake apparatus and baking method using this stage
KR20060030207A (en) Bake apparatus
KR20030013590A (en) Baking oven apparatus
KR100718276B1 (en) Method for ashing substrates
KR20220162057A (en) Outer periphery coating method, substrate processing apparatus and storage medium
KR20060012468A (en) Baking apparatus of semiconductor exposure equipment
KR20060068073A (en) Bake apparatus
JP2022172867A (en) Substrate processing apparatus, substrate processing method, and storage medium
KR20070018176A (en) photolithgraphy apparatus for semiconductor device manufacturing

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination