KR20080080782A - Electro component package and method for manufacturing thereof - Google Patents

Electro component package and method for manufacturing thereof Download PDF

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Publication number
KR20080080782A
KR20080080782A KR1020070020943A KR20070020943A KR20080080782A KR 20080080782 A KR20080080782 A KR 20080080782A KR 1020070020943 A KR1020070020943 A KR 1020070020943A KR 20070020943 A KR20070020943 A KR 20070020943A KR 20080080782 A KR20080080782 A KR 20080080782A
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South Korea
Prior art keywords
electronic device
insulating layer
heat sink
adhesive
device package
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KR1020070020943A
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Korean (ko)
Inventor
백종환
이성
도재천
노재기
강준석
김선경
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삼성전기주식회사
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Priority to KR1020070020943A priority Critical patent/KR20080080782A/en
Publication of KR20080080782A publication Critical patent/KR20080080782A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Abstract

An electronic component package and a method for manufacturing thereof are provided to simplify a process and to improve heat-radiating efficiency by molding an electronic element in a cavity of a heat-radiating plate. An electronic component is mounted on one surface of a first insulating layer(S110). An adhesive is coated on the electronic component(S120). A heat-radiating plate including a cavity is bonded with one surface of the first insulating layer to cover the electronic component(S130). A circuit pattern is formed on the other surface of the first insulating layer(S140). A plurality of air bents for penetrating the heat-radiating plate are formed in a bottom surface of the heat-radiating plate.

Description

전자소자 패키지 및 그 제조방법{electro component package and method for manufacturing thereof}Electronic component package and method for manufacturing thereof

도 1은 종래기술에 따른 전자소자 패키지 제조방법을 나타내는 흐름도.1 is a flow chart showing a method for manufacturing an electronic device package according to the prior art.

도 2는 종래기술에 따른 전자소자 패키지를 나타내는 단면도.2 is a cross-sectional view showing an electronic device package according to the prior art.

도 3은 본 발명의 일 측면에 따른 전자소자 패키지 제조방법을 나타내는 순서도.3 is a flow chart showing a method of manufacturing an electronic device package according to an aspect of the present invention.

도 4는 도 3의 전자소자 패키지 제조방법을 나타내는 흐름도.4 is a flowchart illustrating a method of manufacturing an electronic device package of FIG. 3.

도 5 및 도 6은 방열판을 나타내는 사시도.5 and 6 are perspective views showing the heat sink.

도 7은 본 발명의 다른 측면에 따른 전자소자 패키지의 제1 실시예를 나타내는 단면도.7 is a cross-sectional view showing a first embodiment of an electronic device package according to another aspect of the present invention.

도 8은 본 발명의 다른 측면에 따른 전자소자 패키지의 제2 실시예를 나타내는 단면도.8 is a sectional view showing a second embodiment of an electronic device package according to another aspect of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10: 전자소자 20: 제1 절연층10: electronic device 20: first insulating layer

22, 52: 비아홀 24, 54: 회로패턴22, 52: via hole 24, 54: circuit pattern

26, 56: 도금층 30: 접착제26, 56 plating layer 30: adhesive

40, 40': 방열판 42: 캐비티40, 40 ': heat sink 42: cavity

44: 에어벤트 50: 제2 절연층44: air vent 50: second insulating layer

62: 솔더레지스트 64: 랜드62: solder resist 64: land

66: 솔더범프66: solder bump

본 발명은 전자소자 패키지 및 그 제조방법에 관한 것이다.The present invention relates to an electronic device package and a method of manufacturing the same.

최근 전자부품 산업에서는 칩의 I/O 수가 지속적으로 증가되고 패키지는 더욱 다기능화, 복합화되는 경향이다. 이에, 플립칩 BGA(Ball Grid Array) 패키지에서의 솔더 범프를 사용하지 않고 칩 상의 패드를 칩 스케일 그대로 패키징 하는 칩 스케일 패키지 제시되었다.Recently, in the electronic component industry, the number of I / Os of chips is continuously increasing, and packages are becoming more versatile and complex. Thus, a chip scale package has been proposed in which a pad on a chip is packaged as it is without using solder bumps in a flip chip BGA (Ball Grid Array) package.

도 1은 종래기술에 따른 전자소자 패키지 제조방법을 나타내는 흐름도이고, 도 2는 종래기술에 따른 전자소자 패키지를 나타내는 단면도이다. 도 1 및 도 2에 도시된 바와 같은 종래기술에 따른 전자소자 패키지 제조방법은. 칩(1)을 몰딩하는 과정에서 공극(void)이 발생할 염려가 있고, 댐 부재(3) 및 접착제(4)를 이용하여 연성(flexible) 기판(2)에 칩(1)을 몰딩한 다음, 방열판(8) 부착 및 레이업 공정 등과 같은 이후 공정을 수행함으로써, 핸들링이 불안정해질 수 있다는 문제가 있 다.1 is a flowchart illustrating a method of manufacturing an electronic device package according to the prior art, and FIG. 2 is a cross-sectional view illustrating an electronic device package according to the prior art. Electronic device package manufacturing method according to the prior art as shown in FIG. In the process of molding the chip 1, voids may occur, and the chip 1 is molded onto the flexible substrate 2 using the dam member 3 and the adhesive 4, There is a problem that handling may become unstable by performing a subsequent process such as the heat sink 8 attachment and layup process.

또한, 도 2에 도시된 바와 같이, 접착층(7)을 이용하여 방열판(8)을 댐 부재(3)과 결합함으로써 내구성이 약해지는 문제를 야기할 수 있으며, 전자소자(1)의 한 쪽 면만이 방열판(8)과 대향하도록 배치되어 있는 구성으로 인하여, 방열효율이 저하될 수 있는 문제 또한 제시될 수 있다.In addition, as shown in FIG. 2, by using the adhesive layer 7 to couple the heat sink 8 with the dam member 3, the durability may be weakened, and only one side of the electronic device 1 may be caused. Due to the configuration disposed to face the heat sink 8, a problem that the heat radiation efficiency may be lowered may also be presented.

본 발명은 방열판의 구조를 변경함으로써 방열효과를 극대화 시킬 수 있는 전자소자 패키지 및 그 제조방법을 제공하는 것이다.The present invention is to provide an electronic device package and a method of manufacturing the same that can maximize the heat dissipation effect by changing the structure of the heat sink.

본 발명의 일 측면에 따르면, 제1 절연층의 일면에 전자소자를 실장하는 단계; 전자소자에 접착제를 도포하는 단계; 전자소자를 커버하도록, 전자소자에 상응하여 캐비티가 형성된 방열판을 제1 절연층의 일면에 본딩하는 단계; 및 제1 절연층의 타면에 회로패턴을 형성하는 단계를 포함하는 전자소자 패키지 제조방법을 제공할 수 있다.According to an aspect of the invention, mounting the electronic device on one surface of the first insulating layer; Applying an adhesive to the electronic device; Bonding a heat sink having a cavity corresponding to the electronic device to one surface of the first insulating layer so as to cover the electronic device; And forming a circuit pattern on the other surface of the first insulating layer.

방열판의 저면에는, 방열판을 관통하는 에어벤트가 형성될 수 있으며, 이러한 에어벤트는 복수 개 형성될 수도 있다.On the bottom surface of the heat sink, an air vent penetrating the heat sink may be formed, and a plurality of such air vents may be formed.

접착제는 열매개물질(TIM)을 포함하는 재질로 이루어질 수 있으며, 제1 절연층은 폴리이미드(PI)를 포함하는 재질로 이루어질 수 있다.The adhesive may be made of a material including a fruit medium (TIM), and the first insulating layer may be made of a material containing polyimide (PI).

한편, 다층의 패키지를 제조하기 위하여, 제1 절연층의 타면에 레이업 층을 형성할 수 있다.Meanwhile, in order to manufacture a multilayer package, a layup layer may be formed on the other surface of the first insulating layer.

본 발명의 다른 측면에 따르면, 제1 절연층; 제1 절연층의 일면에 실장되는 전자소자; 전자소자의 상응하여 캐비티가 형성되고, 전자소자를 커버하도록 제1 절연층의 일면에 본딩되는 방열판; 캐비티에 충전되는 접착제; 및 제1 절연층의 타면에 형성되는 회로패턴을 포함하는 전자소자 패키지를 제공할 수 있다.According to another aspect of the invention, the first insulating layer; An electronic device mounted on one surface of the first insulating layer; A heat sink corresponding to the cavity of the electronic device and bonded to one surface of the first insulating layer to cover the electronic device; Adhesive filled in the cavity; And a circuit pattern formed on the other surface of the first insulating layer.

방열판의 저면에는 방열판을 관통하는 에어벤트가 형성될 수 있으며, 이러한 에어벤트는 복수 개 형성될 수 있다.An air vent penetrating the heat sink may be formed on the bottom surface of the heat sink, and a plurality of such air vents may be formed.

접착제는 열매개물질(TIM)을 포함하는 재질로 이루어질 수 있으며, 제1 절연층은 폴리이미드(PI)를 포함하는 재질로 이루어질 수 있다.The adhesive may be made of a material including a fruit medium (TIM), and the first insulating layer may be made of a material containing polyimide (PI).

제1 절연층의 타면에는 레이업 층이 적층될 수 있다.A layup layer may be stacked on the other surface of the first insulating layer.

전술한 것 외의 다른 측면, 특징, 이점이 이하의 도면, 특허청구범위 및 발명의 상세한 설명으로부터 명확해질 것이다.Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

이하, 본 발명에 따른 전자소자 패키지 및 그 제조방법의 바람직한 실시예를 첨부도면을 참조하여 상세히 설명하기로 하며, 첨부 도면을 참조하여 설명함에 있어, 동일하거나 대응하는 구성 요소는 동일한 도면번호를 부여하고 이에 대한 중복되는 설명은 생략하기로 한다.Hereinafter, a preferred embodiment of an electronic device package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings, in the description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals. And duplicate description thereof will be omitted.

먼저, 본 발명의 일 측면에 따른 전자소자 패키지 제조방법에 대해 설명하도록 한다. 도 3은 본 발명의 일 측면에 따른 전자소자 패키지 제조방법을 나타내는 순서도이고, 도 4는 도 3의 전자소자 패키지 제조방법을 나타내는 흐름도이다. 도 3 및 도 4를 참조하면, 전자소자(10), 제1 절연층(20), 비아홀(22, 52), 회로패턴(24, 54), 도금층(26, 56), 접착제(30), 방열판(40), 캐비티(42), 제2 절연층(50), 솔더레지스트(62), 랜드(64), 솔더범프(66)가 도시되어 있다.First, an electronic device package manufacturing method according to an aspect of the present invention will be described. 3 is a flowchart illustrating a method of manufacturing an electronic device package according to an aspect of the present invention, and FIG. 4 is a flowchart illustrating a method of manufacturing an electronic device package of FIG. 3. 3 and 4, the electronic device 10, the first insulating layer 20, the via holes 22 and 52, the circuit patterns 24 and 54, the plating layers 26 and 56, the adhesive 30, A heat sink 40, a cavity 42, a second insulating layer 50, a solder resist 62, lands 64, and solder bumps 66 are shown.

먼저, 제1 절연층(20)의 일면에 전자소자(10)를 실장한다(S110). 효율적인 접착을 위하여, 제1 절연층(20)의 일면에는 접착재료(미도시)가 도포되어 있을 수 있다.First, the electronic device 10 is mounted on one surface of the first insulating layer 20 (S110). For efficient adhesion, an adhesive material (not shown) may be applied to one surface of the first insulating layer 20.

한편, 제1 절연층(20)은 수축력이 우수하고, 박형화에 유리한 폴리이미드를 주된 재질로 하여 이루어질 수 있다.On the other hand, the first insulating layer 20 may be made of polyimide, which is excellent in shrinkage and advantageous for thinning, as the main material.

다음으로, 전자소자(10)에 접착제(30)를 도포하고(S120), 캐비티(42)가 형성된 방열판(40)을 제1 절연층(20)의 일면에 본딩한다(S130). 도 4의 (b)에 도시된 바와 같이, 전자소자(10)의 상면에 접착제(30)를 도포하고, 그 위를 캐비티(42)가 형성된 방열판(40)으로 커버하는 것이다. 도 5에 도시된 바와 같이, 방열판(40)에는 캐비티(42)가 형성되어 있으므로, 전자소자(10)의 측면과 상면은 모두 방열판(40)에 의해 커버될 수 있게 된다.Next, the adhesive 30 is applied to the electronic device 10 (S120), and the heat sink 40 having the cavity 42 is bonded to one surface of the first insulating layer 20 (S130). As shown in FIG. 4B, the adhesive 30 is applied to the upper surface of the electronic device 10, and the upper surface of the electronic device 10 is covered with the heat sink 40 having the cavity 42 formed thereon. As shown in FIG. 5, since the cavity 42 is formed in the heat sink 40, both the side surface and the top surface of the electronic device 10 may be covered by the heat sink 40.

전자소자(10)에 도포되는 접착제(30)의 양은, 캐비티(42)와 전자소자(10)의 부피 등을 고려하여 이에 상응하도록 결정할 수 있다. 즉, 방열판(40)으로 전자소자(10)를 커버하였을 경우, 전자소자(10)와 방열판(40)의 내벽 사이에 형성되는 공간의 부피만큼 접착제(30)를 도포할 수 있는 것이다.The amount of the adhesive 30 applied to the electronic device 10 may be determined to correspond to the volume 42 of the cavity 42 and the electronic device 10. That is, when the electronic device 10 is covered by the heat sink 40, the adhesive 30 may be applied by the volume of the space formed between the electronic device 10 and the inner wall of the heat sink 40.

그러나, 이처럼 도포되는 접착제(30)의 양을 정확하게 맞추는 것이 용이하지 않을 수도 있으며, 도포되는 접착제(30)의 양을 잘못 맞추는 경우, 자칫 접착 제(30) 내부에 공극(void)이 생길 염려도 있다.However, it may not be easy to precisely adjust the amount of the adhesive 30 to be applied in this way, and if the amount of the adhesive 30 to be applied is incorrectly adjusted, even if there is a concern that voids may occur inside the adhesive 30. have.

이를 고려하여, 도 6에 도시된 바와 같이, 방열판(40)의 저면에 방열판(40)을 관통하는 에어벤트(44)를 형성할 수 있다. 방열판(40)에 에어벤트(44)를 형성함으로써, 전자소자(10)에 도포되는 접착제(30)의 양에 여유를 갖게 될 수 있게 되는 것이다. 즉, 전자소자(10)에 충분한 양의 접착제(30)를 도포한 다음 방열판(40)을 본딩하면, 캐비티(42)의 여분의 공간에 접착제(30)가 충분히 채워지게 되며, 과잉 공급된 접착제(30)는 에어벤트(44)를 통해 외부로 배출될 수 있게 되므로, 접착제(30) 내부에 공극이 생길 염려를 줄일 수 있다.In consideration of this, as shown in FIG. 6, an air vent 44 penetrating the heat sink 40 may be formed on the bottom surface of the heat sink 40. By forming the air vent 44 on the heat sink 40, the amount of the adhesive 30 to be applied to the electronic device 10 can be afforded. That is, when a sufficient amount of the adhesive 30 is applied to the electronic device 10 and then the heat sink 40 is bonded, the adhesive 30 is sufficiently filled in the extra space of the cavity 42, and the over-supplied adhesive 30 can be discharged to the outside through the air vent 44, it is possible to reduce the fear of the voids generated in the adhesive (30).

이러한 에어벤트(44)는 복수 개 형성되어, 접착제(30)의 유동을 고려하여 배치될 수 있다. 도 6에는 4개의 에어벤트(44)가 캐비티(42)의 각 코너에 배치된 모습이 도시되어 있다.The plurality of air vents 44 may be formed in consideration of the flow of the adhesive 30. 6 shows four air vents 44 arranged at each corner of the cavity 42.

방열판(40)은 전자소자(10)에서 발생하는 열을 흡수, 전달하는 기능을 수행하는 것으로서, 열전도성의 우수한 구리(Cu), 알루미늄(Al) 등으로 이루어질 수 있다. 상술한 기능을 고려하였을 때, 방열판(40)이 구리, 알루미늄을 제외한 다른 금속 재질로 이루어질 수 있음은 물론이다.The heat sink 40 performs a function of absorbing and transferring heat generated from the electronic device 10, and may be made of excellent copper (Cu), aluminum (Al), and the like. Considering the above function, the heat sink 40 may be made of a metal material other than copper, aluminum, of course.

한편, 접착제(30)가 전자소자(10)를 견고히 지지하는 기능을 수행할 뿐만 아니라, 전자소자(10)에서 발생한 열을 방열판(40)에 효율적으로 전달하는 기능 또한 수행하도록 할 수도 있다. 이를 위하여, 접착제(30)로서 열매개물질(thermal interface material, TIM)을 이용할 수도 있다. On the other hand, the adhesive 30 may not only perform a function of firmly supporting the electronic device 10, but may also perform a function of efficiently transferring heat generated from the electronic device 10 to the heat sink 40. To this end, a thermal interface material (TIM) may be used as the adhesive 30.

다음으로, 제1 절연층(20)의 타면에 회로패턴을 형성한다(S140). 회로패 턴(24)을 형성함과 아울러, 회로패턴(24)과 전자소자(10)가 전기적으로 연결될 수 있도록 비아를 형성할 수도 있다. 즉, 도 4의 (c)에 도시된 바와 같이 제1 절연층(20)을 관통하는 비아홀(22)을 형성하고, 도 4의 (d)에 도시된 바와 같이 도금층(26)을 형성함으로써 비아를 형성할 수 있는 것이다. 물론, 도 4를 통하여 제시하는 방법은 비아를 형성하는 방법 가운데 일 예에 불과하며, 이 외의 다양한 방법으로 회로패턴(24)과 전자소자(10)를 전기적으로 연결할 수 있다.Next, a circuit pattern is formed on the other surface of the first insulating layer 20 (S140). In addition to forming the circuit pattern 24, a via may be formed to electrically connect the circuit pattern 24 and the electronic device 10. That is, the via hole 22 penetrating the first insulating layer 20 is formed as shown in FIG. 4C, and the plating layer 26 is formed as shown in FIG. 4D. It can form. Of course, the method shown in FIG. 4 is only one example of a method of forming a via, and the circuit pattern 24 and the electronic device 10 may be electrically connected in various ways.

다음으로, 제1 절연층(20)의 타면에 레이업 층을 형성한다(S150). 레이업 층을 형성함으로써 다층의 구조를 갖는 전자소자 패키지를 형성할 수 있게 된다. 레이업 층의 형성은 제2 절연층(50)의 적층(도 4의 (e) 참조), 비아홀(52)의 천공(도 4의 (f) 참조), 도금층(56) 및 회로패턴(54)의 형성(도 4의 (g) 참조) 등의 과정을 통하여 구현될 수 있다. 이 후, 최 외곽 층에는 솔더레지스트(62)를 도포하고(도 4의 (h) 참조), 랜드(64)부를 형성한 다음(도 4의 (i) 참조), 솔더범프(66)를 형성할 수 있다(도 4의 (j) 참조).Next, a layup layer is formed on the other surface of the first insulating layer 20 (S150). By forming the layup layer, it is possible to form an electronic device package having a multilayer structure. The formation of the layup layer is performed by stacking the second insulating layer 50 (see FIG. 4E), drilling the via hole 52 (see FIG. 4F), the plating layer 56 and the circuit pattern 54. ) May be implemented through a process such as forming (see FIG. 4G). Subsequently, a solder resist 62 is applied to the outermost layer (see FIG. 4 (h)), lands 64 are formed (see FIG. 4 (i)), and solder bumps 66 are formed. (See (j) of FIG. 4).

이상 본 발명의 일 측면에 따른 전자소자 패키지 제조방법에 대해 설명하였으며, 이하에서는 본 발명의 다른 측면에 따른 전자소자 패키지에 대해 설명하도록 한다.The electronic device package manufacturing method according to an aspect of the present invention has been described above. Hereinafter, the electronic device package according to another aspect of the present invention will be described.

도 7은 본 발명의 다른 측면에 따른 전자소자 패키지의 제1 실시예를 나타내는 단면도이다. 도 7을 참조하면, 전자소자(10), 제1 절연층(20), 비아홀, 회로패턴, 도금층, 접착제(30), 방열판(40), 캐비티(42), 제2 절연층(50), 솔더레지스 트(62), 랜드(64), 솔더범프(66)가 도시되어 있다.7 is a cross-sectional view showing a first embodiment of an electronic device package according to another aspect of the present invention. Referring to FIG. 7, the electronic device 10, the first insulating layer 20, the via hole, the circuit pattern, the plating layer, the adhesive 30, the heat sink 40, the cavity 42, the second insulating layer 50, Solder register 62, lands 64, solder bumps 66 are shown.

제1 절연층(20)의 일면에는 전자소자(10)가 실장된다. 전자소자(10)가 견고하게 실장될 수 있도록 하기 위하여, 제1 절연층(20)의 일면에는 접착층이 형성되어 있을 수도 있다. 제1 절연층(20)으로는, 수축력이 우수하고, 박형화에 유리한 폴리이미드 재질을 이용할 수 있다. 도 7에는 페이스 다운(face down) 방식으로 제1 절연층(20)에 실장된 전자소자(10)가 도시되어 있다.The electronic device 10 is mounted on one surface of the first insulating layer 20. In order to securely mount the electronic device 10, an adhesive layer may be formed on one surface of the first insulating layer 20. As the 1st insulating layer 20, the polyimide material which is excellent in shrinking force and advantageous for thinning can be used. FIG. 7 illustrates an electronic device 10 mounted on the first insulating layer 20 in a face down manner.

방열판(40)은 전자소자(10)가 실장된 제1 절연층(20)의 일면에 본딩되며, 이러한 방열판(40)에는 전자소자(10)에 상응하여 캐비티(42)가 형성되어, 전자소자(10)를 커버할 수 있게 된다. 도 5 및 도 7에 도시된 바와 같이, 방열판(40)에는 캐비티(42)가 형성되어 있으므로, 전자소자(10)의 측면과 하면은 모두 방열판(40)에 의해 커버될 수 있게 된다. 이러한 구조를 통하여 방열판(40)의 면적을 증가시켜, 방열효율을 증대시킬 수 있게 된다.The heat sink 40 is bonded to one surface of the first insulating layer 20 on which the electronic device 10 is mounted, and the heat sink 40 is formed with a cavity 42 corresponding to the electronic device 10. (10) can be covered. As shown in FIGS. 5 and 7, since the cavity 42 is formed in the heat sink 40, both the side surfaces and the bottom surface of the electronic device 10 may be covered by the heat sink 40. Through such a structure, the area of the heat sink 40 may be increased to increase the heat dissipation efficiency.

방열판(40)은 전자소자(10)에서 발생하는 열을 흡수, 전달하는 기능을 수행하는 것으로서, 열전도성의 우수한 구리(Cu), 알루미늄(Al) 등으로 이루어질 수 있다. 상술한 기능을 고려하였을 때, 방열판(40)이 구리, 알루미늄을 제외한 다른 금속 재질로 이루어질 수 있음은 물론이다.The heat sink 40 performs a function of absorbing and transferring heat generated from the electronic device 10, and may be made of excellent copper (Cu), aluminum (Al), and the like. Considering the above function, the heat sink 40 may be made of a metal material other than copper, aluminum, of course.

방열판(40)의 내벽과 전자소자(10) 사이의 공간, 즉 캐비티(42)의 여분의 공간에는 접착제(30)가 충전된다. 이러한 접착제(30)는 전자소자(10)가 방열판(40)의 캐비티(42)에 수용되도록 견고히 지지하는 기능을 수행할 수 있다.The adhesive 30 is filled in the space between the inner wall of the heat sink 40 and the electronic device 10, that is, the extra space of the cavity 42. The adhesive 30 may function to firmly support the electronic device 10 to be accommodated in the cavity 42 of the heat sink 40.

뿐만 아니라, 전자소자(10)에서 발생하는 열을 방열판(40)으로 전달하는 기 능을 수행할 수도 있는데, 이러한 열 전달 기능을 보다 효율적으로 수행할 수 있도록 하기 위하여, 접착제(30)로는 열매개물질(TIM)을 이용할 수 있다.In addition, a function of transferring heat generated from the electronic device 10 to the heat sink 40 may be performed. In order to perform the heat transfer function more efficiently, the adhesive 30 may be a nut. Materials (TIM) can be used.

이러한 접착제(30)를 충전하는 방법은, 전술한 전자소자 패키지 제조방법을 통하여 제시한 바와 동일하므로, 이에 대한 구체적인 설명은 생략하도록 한다.Since the method of filling the adhesive 30 is the same as the above-described method of manufacturing the electronic device package, a detailed description thereof will be omitted.

제1 절연층(20)의 타면에는 회로패턴(24)이 형성된다. 회로패턴(24)은 본 실시예에 따른 전자소자 패키지가 소정의 기능을 수행할 수 있도록 하는 수단이며, 제1 절연층(20)에 형성되는 비아를 통하여 전자소자(10)의 전극과 전기적으로 연결될 수 있게 된다.The circuit pattern 24 is formed on the other surface of the first insulating layer 20. The circuit pattern 24 is a means for enabling the electronic device package according to the present embodiment to perform a predetermined function, and is electrically connected to the electrode of the electronic device 10 through vias formed in the first insulating layer 20. Can be connected.

한편, 다층의 전자소자 패키지를 구현하기 위하여, 제1 절연층(20)의 타면에는 레이업 층이 적층될 수 있다. 레이업 층을 적층하는 방법은 전술한 전자소자 패키지 제조방법을 통하여 제시한 바와 동일하므로, 이에 대한 구체적인 설명은 생략하도록 한다.Meanwhile, in order to implement a multilayer electronic device package, a layup layer may be stacked on the other surface of the first insulating layer 20. Since the method of stacking the layup layer is the same as the method of manufacturing the electronic device package described above, a detailed description thereof will be omitted.

도 8은 본 발명의 다른 측면에 따른 전자소자 패키지의 제2 실시예를 나타내는 단면도이다. 도 8을 참조하면, 전자소자(10), 제1 절연층(20), 비아홀, 회로패턴, 도금층, 접착제(30), 방열판(40), 캐비티(42), 에어벤트, 제2 절연층(50), 솔더레지스트(62), 랜드(64), 솔더범프(66)가 도시되어 있다.8 is a cross-sectional view illustrating a second embodiment of an electronic device package according to another aspect of the present invention. Referring to FIG. 8, the electronic device 10, the first insulating layer 20, the via hole, the circuit pattern, the plating layer, the adhesive 30, the heat sink 40, the cavity 42, the air vent, and the second insulating layer ( 50, solder resist 62, lands 64, solder bumps 66 are shown.

본 실시예는 상술한 실시예와 비교하여, 방열판(40)에 에어벤트(44)가 형성된 것에 그 차이가 있다. 이러한 에어벤트(44)는, 전술한 전자소자 패키지 제조방법을 통하여 제시한 바와 같이, 접착제(30)의 충전을 보다 효율적으로 구현하기 위한 것으로서, 이에 대한 구체적은 설명은 생략하도록 한다.This embodiment is different from the above-described embodiment, in which the air vent 44 is formed on the heat sink 40. The air vent 44, as presented through the above-described method for manufacturing an electronic device package, to more efficiently implement the filling of the adhesive 30, a detailed description thereof will be omitted.

전술한 실시예 외의 많은 실시예들이 본 발명의 특허청구범위 내에 존재한다.Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

상술한 바와 같이 본 발명의 바람직한 실시예에 따르면, 방열판에 캐비티를 형성하고, 열전도성과 접착력이 우수한 물질을 이용하여 전자소자를 캐비티에 몰딩함으로써, 공정을 단순화할 수 있고, 방열효과를 향상시킬 수 있다. According to a preferred embodiment of the present invention as described above, by forming a cavity in the heat sink, and molding the electronic device in the cavity using a material having excellent thermal conductivity and adhesion, it is possible to simplify the process and improve the heat dissipation effect have.

Claims (12)

제1 절연층의 일면에 전자소자를 실장하는 단계;Mounting an electronic device on one surface of the first insulating layer; 상기 전자소자에 접착제를 도포하는 단계;Applying an adhesive to the electronic device; 상기 전자소자를 커버하도록, 상기 전자소자에 상응하여 캐비티가 형성된 방열판을 상기 제1 절연층의 일면에 본딩하는 단계; 및Bonding a heat sink having a cavity corresponding to the electronic device to one surface of the first insulating layer so as to cover the electronic device; And 상기 제1 절연층의 타면에 회로패턴을 형성하는 단계를 포함하는 전자소자 패키지 제조방법.Forming a circuit pattern on the other surface of the first insulating layer. 제1항에 있어서,The method of claim 1, 상기 방열판의 저면에는, 상기 방열판을 관통하는 에어벤트가 형성되는 것을 특징으로 하는 전자소자 패키지 제조방법.The bottom surface of the heat sink, the electronic device package manufacturing method characterized in that the air vent penetrating the heat sink is formed. 제2항에 있어서,The method of claim 2, 상기 에어벤트는 복수 개 형성되는 것을 특징으로 하는 전자소자 패키지 제조방법.The air vent is a plurality of electronic device package manufacturing method characterized in that formed. 제1항에 있어서,The method of claim 1, 상기 접착제는 열매개물질(TIM)을 포함하는 재질로 이루어지는 것을 특징으로 하는 전자소자 패키지 제조방법.The adhesive is an electronic device package manufacturing method, characterized in that made of a material containing a fruit medium (TIM). 제1항에 있어서,The method of claim 1, 상기 제1 절연층은 폴리이미드(PI)를 포함하는 재질로 이루어지는 것을 특징으로 하는 전자소자 패키지 제조방법.The first insulating layer is a method for manufacturing an electronic device package, characterized in that made of a material containing polyimide (PI). 제1항에 있어서,The method of claim 1, 상기 제1 절연층의 타면에 레이업 층을 형성하는 단계를 더 포함하는 전자소자 패키지 제조방법.The method of claim 1, further comprising forming a layup layer on the other surface of the first insulating layer. 제1 절연층;A first insulating layer; 상기 제1 절연층의 일면에 실장되는 전자소자;An electronic device mounted on one surface of the first insulating layer; 상기 전자소자의 상응하여 캐비티가 형성되고, 상기 전자소자를 커버하도록 상기 제1 절연층의 일면에 본딩되는 방열판;A heat sink corresponding to the cavity of the electronic device and bonded to one surface of the first insulating layer to cover the electronic device; 상기 캐비티에 충전되는 접착제; 및Adhesive filled in the cavity; And 상기 제1 절연층의 타면에 형성되는 회로패턴을 포함하는 전자소자 패키지.An electronic device package comprising a circuit pattern formed on the other surface of the first insulating layer. 제7항에 있어서,The method of claim 7, wherein 상기 방열판의 저면에는 상기 방열판을 관통하는 에어벤트가 형성되는 것을 특징으로 하는 전자소자 패키지.An electronic device package, characterized in that the air vent penetrating the heat sink is formed on the bottom surface of the heat sink. 제8항에 있어서,The method of claim 8, 상기 에어벤트는 복수 개 형성되는 것을 특징으로 하는 전자소자 패키지.The air vent is an electronic device package, characterized in that formed in plurality. 제7항에 있어서,The method of claim 7, wherein 상기 접착제는 열매개물질(TIM)을 포함하는 재질로 이루어지는 것을 특징으로 하는 전자소자 패키지.The adhesive is an electronic device package, characterized in that made of a material containing a fruit medium (TIM). 제7항에 있어서,The method of claim 7, wherein 상기 제1 절연층은 폴리이미드(PI)를 포함하는 재질로 이루어지는 것을 특징으로 하는 전자소자 패키지.The first insulating layer is an electronic device package, characterized in that made of a material containing polyimide (PI). 제7항에 있어서,The method of claim 7, wherein 상기 제1 절연층의 타면에 적층되는 레이업 층을 더 포함하는 전자소자 패키지.The electronic device package further comprises a layup layer stacked on the other surface of the first insulating layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101456943B1 (en) * 2014-04-11 2014-11-04 (주)디에이치씨 Printed circuit board having cirtcuit pattern of multi-layer structure using conductive ink

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101456943B1 (en) * 2014-04-11 2014-11-04 (주)디에이치씨 Printed circuit board having cirtcuit pattern of multi-layer structure using conductive ink

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