KR20080079978A - Operating method of charge trap flash memory device - Google Patents

Abstract

An operation method of a charge trap flash memory device is provided to assure stability of a program/erase state by preventing opposite charges from being left in a charge trap layer in a program state or an erase state, by improving recombination speed of electrons and holes and stabilizing charges. According to an operation method of performing program or erase operation in a charge trap flash memory device having a charge trap layer, program or erase operation is performed by using a composite signal of a DC pulse signal and an AC perturbation signal. The composite pulse has the AC perturbation signal following the DC pulse signal for a constant time. The composite signal has an overlapped signal of a first DC pulse signal, a second DC pulse signal smaller than the first DC pulse signal and the AC perturbation signal.

Description

Operating method of charge trap flash memory device

1 schematically shows an example of a charge trap type flash memory device in which a program or erase operation may be performed by applying an operating method according to the present invention.

2 shows a memory signal according to a method of operating a charge trapping flash memory device according to an embodiment of the present invention in comparison with a memory signal according to a conventional operating method.

3 to 5 show a memory signal according to a method of operating a charge trapping flash memory device of other embodiments of the present invention.

FIG. 6 is a graph showing the frequency dependence of AC conductivity disclosed in R. D. Gould and S. A. Awan, Thin Solid Films, 443, 309 (2003).

7A and 7B show the possibility of recombination of electron-holes in the absence of AC perturbation and in the presence of AC perturbation when there are electrons trapped in the deep trap and immovable.

<Brief description of symbols for the main parts of the drawings>

10 ... Charge trap type flash memory element 21 ... Tunnel insulating film

23.Charge trap layer 25.Blocking insulating film

27 ... gate electrode

The present invention relates to a method of operating a charge trapping flash memory device, and more particularly, to promote charge stabilization and recombination of electrons and holes to secure program / erase states. The present invention relates to a method of operating a charge trapping flash memory device.

Among the semiconductor memory devices, the nonvolatile memory device is a storage device in which stored data is not destroyed even when power supply is cut off.

The configuration of the memory cell, which is a basic component of the nonvolatile semiconductor memory device, depends on the field in which the nonvolatile semiconductor memory device is used.

A high-capacity nonvolatile semiconductor memory device widely used at present, and in the case of a NAND (not and) flash semiconductor memory device, the gate of the transistor includes a floating gate in which charge is stored, that is, data is stored. It has a structure in which a control gate (control gate) for controlling this is sequentially stacked.

In such a flash semiconductor memory device, the memory cell size is rapidly being reduced in order to meet the increasing demand for increasing memory capacity every year. In addition, in order to reduce the size of the cell, it is required to effectively reduce the height in the vertical direction of the floating gate.

Means for storing charge in order to effectively reduce the vertical height of the memory cell, while maintaining retention characteristics, which are memory characteristics of the memory cell, for example, keeping the stored data intact for a long time. MOIOS (Silicon-Oxide-Nitride-Oxide-Semiconductor) or MONOS (Metal-Oxide- Nitride-Oxide-Semiconductor) memory devices configured using a silicon nitride film (Si ₃ N ₄ ) rather than a floating gate. A semiconductor memory device having a metal-oxide-insulator-oxide-semiconductor structure has been proposed, and active research is being conducted. Here, the difference is that SONOS uses silicon as the control gate material and MONOS uses metal as the control gate material.

SONOS and MONOS type memory devices use a charge trap layer such as silicon nitride (Si ₃ N ₄ ) instead of a floating gate as a means for storing charge. That is, the SONOS type or MONOS type memory device uses an oxide film to form a stack (a stack composed of a floating gate and insulating layers stacked above and below) between a substrate and a control gate in a memory cell configuration of a flash semiconductor memory device. , A charge trap using a characteristic in which a nitride film and an oxide film are replaced with an ONO stacked sequentially, and a threshold voltage is shifted as the charge is trapped in the nitride film. Charge Trap Flash (CTF) memory devices.

For more information about SONOS memory devices, see Technical Digest of International Electron Device Meeting (IEDM 2002, December), pp. 927-930. Swift et al., "An Embedded 90nm SONOS Nonvolatile Memory Utilizing Hot Electron Programming and Uniform Tunnel Erase".

The basic structure of a SONOS type memory device is as follows. A first silicon oxide film (SiO ₂ ) is formed as a tunnel insulating film on the semiconductor substrate between the source and drain regions, that is, on the channel region so that both ends contact the source and drain regions. The first silicon oxide film is a film for tunneling charges. A silicon nitride film (Si ₃ N ₄ ) is formed on the first silicon oxide film as the electrolytic trap layer. The silicon nitride film is a material film in which data is substantially stored, and charges tunneling the first silicon oxide film are trapped. A second silicon oxide film is formed on the silicon nitride film as a blocking insulating film for blocking the charge from moving upward through the silicon nitride film. A gate electrode is formed on the second silicon oxide film.

However, the SONOS type memory device having such a general structure has low dielectric constants of silicon nitride and silicon oxide films, insufficient trap site density in the silicon nitride film, high operating voltage, and high data rate (program speed). The problem is that the charge retention time in the vertical and horizontal directions is not sufficient as desired.

Recently, the use of an aluminum oxide film (Al ₂ O ₃ ) having a larger dielectric constant than the silicon oxide film as the blocking insulating film instead of the silicon oxide film has improved the program speed and retention characteristics compared with the silicon oxide film. It has been reported.

For more information on this report, please see the Extended Abstract of 2002 International Conf. on Solid State Device and Materials, Nagoya, Japan, Sept. 2002, pp. 162-163, in "Novel Structure of SiO ₂ / SiN / High-k dielectric, Al ₂ O ₃ for SONOS type flash memory," published by C. Lee et al.

As described above, in a charge trapping flash (CTF) memory device having a charge trap layer instead of a floating gate, electrons are stored in the charge trap layer during programming, and holes are stored in the charge trap layer during erasing. holes) to remove electrons stored in the charge trap layer by hole-electron recombination.

However, when initially programmed into an unused charge trapping flash memory device, the injected electrons are trapped in the charge trap layer and localized, where the electrons are thermally stabilized as a deep trap and spread spatially. Goes. Since the threshold voltage value of the device is changed while the electrons are stabilized and spread in space, it takes time until the threshold voltage Vth is fixed as localized electron thermalization proceeds.

Such time-dependent Vth fluctuations make it difficult to control the threshold voltage value distribution during programming by an incremental step pulse programming (ISPP) method.

As is well known, the ISPP method applies a program pulse voltage followed by applying a verifying voltage to verify the threshold voltage of the memory cell so that the threshold voltage of the memory cell reaches a desired value. That's the way it is. Since a plurality of memory cells constituting the memory device has an initial threshold voltage distribution, an ISPP scheme is introduced to allow all memory cells to reach a desired threshold voltage in consideration of the threshold voltage distribution for each memory cell.

However, when the threshold voltage changes with time as described above, it is difficult to control the threshold voltage value distribution by the ISPP method, and it is not easy to program the memory cell within a desired threshold voltage value range.

On the other hand, upon erasing of the programmed information, the recombination of the injected holes and the electrons de-trapped by the localized electrons or the fields is made non-localized, and the holes left after the recombination and localization not completely removed Re-distribution of the former electrons can be made.

During such electron-hole recombination and charge rearrangement, since the threshold voltage value of the memory element is changed, the effective erase time is not the hole injection time but the sum of the recombination time and the rearrangement time. Should be considered.

For the lifetime distribution of electron-holes after optical pumping measured in silicon nitride made by LPCVD, see K. S. Seol et al., Phys. Rev. B 62, 1532 (2000).

According to this document, the recombination time of electron-holes is widely distributed from ns to ms. In the LESR measurement results, it is known that the recombination time is distributed to ˜10 ³ s.

The recombination time (tau) of the localized electrons and holes can be expressed by Equation (1).

τ = τ ₀ exp (2 R / R ₀ ) (τ ₀ = 10 ^-8 s)

Where R ₀ is the localization length of the electron or hole, where R ₀ (E) = [ h ² / m ( E _c -E )] ^1/2 or [ h ² / m ( E _v -E ) ] ^1/2 can be satisfied. R is the localized electron-space space distance.

As can be seen from Equation 1, the deep trap ( R ₀ ) decreases, the recombination time increases.

In the erase mode, the injected holes stabilize over time and settle to deep levels.

In the program mode or the erase mode, the variation of the threshold voltage value is large while the stabilization occurs and the charge spreads spatially. Further stabilization results in less threshold voltage fluctuations, but at the same time, charges are localized to deep levels, making them difficult to move.

Therefore, when the recombination time is long, electrons or holes stabilized over time and localized to a deep level cannot be moved, and it becomes difficult to recombine with the opposite charge. In addition, when stabilization, the movement of electrons or holes is limited, the stabilization time is gradually longer.

In addition, the recombination time is long, and the charge is stabilized over time, so that sufficient hole-electron recombination does not occur, and if the electrons trapped by such incomplete recombination remain after erasing, the dispersion increases during programming. .

For example, in a state in which electron-holes are incompletely recombined in the erase mode and electrons are present together as well as holes, even if the electrons are injected with the same number of electrons as the holes remaining when the electron-holes are completely recombined, And holes are incompletely recombined, resulting in the presence of holes as well as electrons. Even if an additional number of electrons are injected therein, the electrons may still be incompletely recombined to bring the holes together. Since the remaining holes can be recombined with the electrons at any moment during the program of repeating the electron injection process and the verification process by the ISPP method, the threshold voltage value can be changed, thus increasing the dispersion of the threshold voltage value at the completion of the program. .

As described above, due to incomplete recombination, the possibility of coexistence with opposite charges causes a scatter during programming, and only when the electrons are removed cleanly in the erased state, it is possible to prevent such a spread during programming.

Due to such incomplete recombination, if the opposite charges coexist, even during high temperature storage (HTS), electron-hole recombination may proceed to cause a change in the threshold voltage value.

Therefore, as described above, when the stabilization time and the recombination time are prolonged, and incomplete recombination is performed, the stability of the erase state or the program state decreases, and the possibility of deterioration of the dispersion of threshold voltage values during program or erase This becomes large, and a change occurs in the threshold voltage value during high temperature storage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and improves the rate of charge stabilization and recombination of electrons and holes. It is an object of the present invention to provide a method of operating a charge trapping flash memory device which can prevent the remaining inside, thereby ensuring the stability of the program / erase state.

In order to achieve the above object, the present invention provides a method of performing a program or erase operation on a charge trapping flash memory device having a charge trap layer, wherein the program or erase operation is performed using a complex signal of a DC pulse signal and an AC perturbation signal. It is characterized by.

According to an aspect of the present invention, the composite signal may be formed in a form in which an AC perturbation signal appears after a DC pulse signal for a predetermined time.

According to another feature of the invention, the composite signal, the DC pulse signal and the AC perturbation signal may be formed in the form alternately.

According to another feature of the present invention, the composite signal may be configured such that the first DC pulse signal, the second DC pulse signal having a smaller magnitude than the first DC pulse signal, and the superimposition signal of the AC perturbation signal alternately appear.

According to another feature of the present invention, the complex signal may be formed in a form in which an AC perturbation signal is superimposed on a DC pulse signal for a predetermined time.

Here, the AC perturbation signal is preferably an AC pulse signal.

In this case, the AC perturbation signal preferably has a frequency greater than the inverse of the section in which the DC pulse signal appears.

Hereinafter, a method of operating a charge trapping flash memory device according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 schematically shows an example of a charge trap type flash memory device in which a program or erase operation may be performed by applying an operating method according to the present invention.

Referring to FIG. 1, a charge trapping memory device 10 according to an embodiment of the present invention includes a substrate 11 and a gate structure 20 formed on the substrate 11.

First and second impurity regions 13 and 15 doped with a predetermined conductive impurity may be formed in the substrate 11. One of the first and second impurity regions 13 and 15 may be used as a drain D and the other as a source S.

The gate structure 20 includes a tunnel insulating film 21 formed on the substrate 11, a charge trap layer 23 formed on the tunnel insulating film 21, and a blocking insulating film 25 formed on the charge trap layer 23. ). The gate electrode 27 may be formed on the blocking insulating layer 25. In FIG. 1, reference numeral 19 denotes a spacer.

The tunnel insulating layer 21 is a film for tunneling charge, and is formed on the substrate 11 to contact the first and second impurity regions 13 and 15. The tunneling insulating film 21 may be formed of, for example, SiO ₂ or an oxide made of various high-k oxides or a combination thereof as a tunneling oxide film.

Alternatively, the tunnel insulating film 21 may be formed of a silicon nitride film, for example, Si ₃ N ₄ . At this time, the silicon nitride film is preferably formed so that the impurity concentration is not high (that is, the impurity concentration is comparable to that of the silicon oxide film) and the interface property with silicon is excellent. In order to form such a high quality silicon nitride film, the silicon nitride film constituting the tunnel insulating film 21 may be formed using a special manufacturing method such as Jet Vapor Depositon.

When the silicon nitride film is formed by the above-mentioned special manufacturing method, it is possible to form a defect-less silicon nitride film (defect-less Si ₃ N ₄ ) which does not have a high impurity concentration as compared with the silicon oxide film and has excellent interface characteristics with silicon.

Alternatively, the tunnel insulating layer 21 may be formed of a double layer structure of a silicon nitride film and an oxide film.

As described above, the tunnel insulating layer 21 may be formed of a single layer structure of an oxide or nitride, or may be formed of a plurality of layers of materials having different energy band gaps.

The charge trap layer 23 is a region in which information is stored by the charge trap. The charge trap layer 23 may be formed to include any one of polysilicon, nitride, high-k dielectric having high dielectric constant, and nanodots.

For example, the charge trap layer 23 may be formed of a nitride such as Si ₃ N ₄ or a high-k oxide such as SiO ₂ , HfO ₂ , ZrO ₂ , Al ₂ O ₃ , HfSiON, HfON, or HfAlO.

In addition, the charge trap layer 23 may include a plurality of nanodots discontinuously disposed as a charge trap site. In this case, the nano-dots may be made in the form of a microcrystal (nanocrystal).

The blocking insulating layer 25 is for blocking charge from moving upward through the position where the charge trap layer 23 is formed, and may be formed of an oxide layer.

The blocking insulating layer 25 is formed of SiO ₂ , or a high-k material, such as Si ₃ N ₄ , Al ₂ O ₃ , HfO ₂ , Ta ₂ O _5, or ZrO, which is a material having a higher dielectric constant than the tunneling insulating film 21. ₂ can be formed. The blocking insulating film 25 may be formed in a multilayer structure. For example, the blocking insulating film 25 may be formed of two or more layers including an insulating layer made of a commonly used insulating material such as SiO ₂ and a high dielectric layer formed of a material having a higher dielectric constant than the tunneling insulating film 21. Can be configured.

The gate electrode 27 may be formed of a metal film. For example, the gate electrode 27 may be formed of aluminum (Al). In addition, the gate electrode 27 may be formed of a silicide material such as Ru, TaN metal, or NiSi, which is typically used as a gate electrode of a semiconductor memory device. .

By injecting electrons into the charge trapping flash memory device as described above, a program is performed such that the injected electrons are trapped at the trap site of the charge trap layer to have a threshold voltage of a program state, for example, 3V, or to the memory device. Holes may be injected to erase electrons by electron-hole recombination to perform an erase such that a threshold voltage of an erase state becomes a threshold voltage of, for example, 0V.

At this time, as described above, the program or erase operation of the present invention is performed to stabilize charges (electrons and / or holes) during programming or erasing in a short time and to prevent incomplete recombination of electron-holes during erasing. According to the charge trapping flash memory device operating method, a program or erase operation is performed with a complex signal of a DC pulse signal and an AC perturbation signal. Hereinafter, a signal for performing a program or erase operation on the charge trapping flash memory element is represented by a memory signal.

2 shows a memory signal according to a method of operating a charge trapping flash memory device according to an embodiment of the present invention in comparison with a memory signal according to a conventional operating method.

As can be seen in Fig. 2, the memory signal according to the conventional method is composed of DC pulse signal components only. The DC pulse time period during which the DC pulse signal is applied may be approximately 10 μs in the program mode and 10 ms in the erase mode.

On the other hand, the memory signal according to the present invention becomes a composite signal consisting of a DC pulse signal component and an AC perturbation signal component. In this case, the AC perturbation signal is preferably an AC pulse signal, and in this case, it is preferable that the AC perturbation signal has a frequency greater than the inverse of the time period in which the DC pulse signal appears.

2 shows an embodiment in which a memory signal according to the present invention is a complex signal in which an AC perturbation signal appears after a DC pulse signal for a predetermined time.

The predetermined time may correspond to a DC pulse section of a memory signal composed of only a DC pulse signal according to a conventional method.

In the composite signal of FIG. 2, the DC pulse duration may be, for example, approximately 10 μs in the program mode and approximately 10 ms, for example, in the erase mode. In this case, in the program mode, the AC perturbation signal component may be an AC pulse signal that has a frequency greater than 1/10 μs = 0.1 MHz, and in the erase mode the AC perturbation signal component has a frequency greater than 1/10 ms = 100 Hz. Can be an AC pulse signal. The AC perturbation signal of the memory signal of the embodiments of FIGS. 3 to 5 below may likewise be an AC pulse signal satisfying this frequency range.

3 to 5 show a memory signal according to a method of operating a charge trapping flash memory device of other embodiments of the present invention.

Referring to FIG. 3, the memory signal may be a complex signal formed of alternating DC pulse signals and AC perturbation signals. 3 shows an example in which the memory signal is a complex signal in which a DC pulse signal and an AC perturbation signal pair appear three times.

Referring to FIG. 4, the memory signal may be a complex signal in which a first DC pulse signal, a second DC pulse signal having a smaller magnitude, and an overlapping signal of an AC perturbation signal alternately appear. 4 shows an example in which the memory signal is a complex signal in which the first DC pulse signal and the second DC pulse signal + AC perturbation signal (overlapping signal) pairs appear three times.

Referring to FIG. 5, the memory signal may be a complex signal having an AC perturbation signal superimposed on a DC pulse signal for a predetermined time. In this case, the predetermined time may correspond to the DC pulse section of the memory signal consisting of only the DC pulse signal according to the conventional method.

According to the method for operating a charge trapping flash memory device which performs the program or erase operation of the present invention as described above, after the injection of charges (electrons in the program mode, holes in the erase mode), it is subjected to external perturbation by the AC perturbation signal component. As a result, the movement of the charges can be temporarily smoothed, and the stabilization of the charges and the recombination rate of the electron-holes can be greatly improved, and the stabilization and recombination time can be greatly shortened.

The evidence that AC perturbation can enhance the rate of stabilization and recombination can be found in the literature on the frequency dependence of AC conductivity as disclosed in R. D. Gould and S. A. Awan, Thin Solid Films, 443, 309 (2003).

6 is a graph showing the frequency dependence of the AC conductivity disclosed in this document.

As can be seen in Figure 6, the AC conductivity increases with increasing ac frequency, in the present invention in the frequency range of several hundred Hz to several MHz, the AC conductivity is used in the program mode or erase mode, AC conductivity is It can be seen that the value is quite large. The higher the frequency, the greater the AC conductivity, so the larger the frequency, the longer the charge travels.

Therefore, it can be seen that the conduction of the charge is possible by the AC perturbation signal component, and the movement of the charge can be more actively by the AC perturbation.

At this time, the AC conduction in the insulator is a directional conduction of the charge, that is, conduction due to an increase in the mean free path of the charge, not DC conduction.

Therefore, when the AC perturbation signal is applied to the charge trapping flash memory device, the movement of the trapped charges in the nitride constituting the charge trap layer, for example, the charge trap layer becomes active. Thereby, the rate of stabilization of the charge can be greatly enhanced. In addition, the recombination rate of electron-holes can be greatly enhanced, thereby significantly lowering the possibility of incomplete recombination, thereby greatly reducing the possibility of coexistence with opposite charges.

In addition, even when the charge is trapped in the deep trap, since the charge trapped in the deep trap is easy to move due to AC perturbation, the recombination probability can be greatly increased.

7A and 7B show the possibility of recombination of electron-holes in the absence of AC perturbation and in the presence of AC perturbation when there are electrons trapped in the deep trap and immovable.

As shown in FIG. 7A, in the absence of AC perturbation, the probability of electrons trapped in deep traps and immovable is recombined with the holes. However, as shown in FIG. 7B, when there is AC perturbation, the electrons trapped in the deep trap are also easily moved by AC perturbation, so that the probability of electrons recombining with holes increases. At this time, since the charge by AC perturbation moves randomly without the directivity, there is no substantial transfer of charge even if AC perturbation occurs.

According to the operation method of performing a program or erase operation on a charge trapping flash memory device having a charge trap layer according to the present invention as described above, the AC perturbation signal component is applied in addition to the DC pulse signal during program or erase. In addition, the charge movement in the charge trap layer is active, thereby greatly increasing the stabilization rate and recombination rate of the charge, and significantly reducing the possibility of incomplete recombination, thereby greatly reducing the possibility of coexistence with the opposite charge.

Therefore, it is possible to ensure the stability of the erase state or the program state, greatly reduce the possibility of deterioration of the dispersion of the threshold voltage value during program or erase, and change the threshold voltage value during high temperature storage. Can be prevented.

Claims (7)

An operation method of performing a program or erase operation on a charge trapping flash memory device having a charge trap layer, A method for operating a charge trapping flash memory device, characterized in that a program or erase is performed with a complex signal of a DC pulse signal and an AC perturbation signal. The method of claim 1, wherein the complex signal is configured such that an AC perturbation signal appears after a DC pulse signal for a predetermined time. The method of claim 1, wherein the complex signal has a form in which a DC pulse signal and an AC perturbation signal are alternately displayed. 2. The charge trapping flash of claim 1, wherein the complex signal comprises a first DC pulse signal, a second DC pulse signal having a smaller magnitude than the first DC pulse signal, and an overlapping signal of an AC perturbation signal. How memory devices work. The method of claim 1, wherein the complex signal is formed by superposing an AC perturbation signal on a DC pulse signal for a predetermined time. 6. A method as claimed in any one of claims 1 to 5, wherein said AC perturbation signal is an AC pulse signal. 7. The method of claim 6, wherein the AC perturbation signal has a frequency greater than the inverse of the interval in which the DC pulse signal appears.

Images