KR20080078318A - Flash memory of hybrid combination and method for manufacturing thereof - Google Patents

Abstract

A flash memory of hybrid combination and a manufacturing method thereof are provided to prevent current from flowing to a damaged tunneling layer by using metal nano particles as a charge storage layer. A flash memory of hybrid combination comprises source and drain electrodes(31,33), a semiconductor nano wire(40), a tunneling layer(51), a charge storage layer(53), an oxide layer(55), and a gate electrode. The source and drain electrodes are formed in a silicon substrate(10). The semiconductor nano wire, floating on the substrate, connects the source electrode with the drain electrode. The tunneling layer wraps the semiconductor nano wire and is formed through atomic layer deposition. The charge storage layer covers the tunneling layer and is composed of metal nano particles obtained by heat-treating a metal nano film on the surface of the tunneling layer. The oxide layer surrounds the charge storage layer and is formed through atomic layer deposition. The gate electrode, covering the oxide layer, is formed on the substrate between the source and drain electrodes.

Description

Nonvolatile memory electronic device of nano-wire nanoparticle heterojunction and manufacturing method thereof

1 is a cross-sectional view of a nonvolatile memory electronic device of nanowire / nanoparticle heterojunction according to the present invention.

FIG. 2 is an enlarged cross-sectional view of part “A” of FIG. 1.

3A to 3G are diagrams illustrating a process of manufacturing a nonvolatile memory electronic device having nanowire-nanoparticle heterobonds according to the present invention.

4A is a scanning electron micrograph of a nanowire having metal nanoparticles formed thereon, according to the present invention.

Figure 4b is a plan view of a non-volatile memory electronic device of the nano-wire nanoparticle heterojunction fabricated in accordance with the present invention.

Figure 5 is a graph of the electrical characteristics of the non-volatile memory electronic device of the nano-wire nanoparticle heterojunction fabricated according to the present invention.

Explanation of symbols on the main parts of the drawings

10 substrate 20 insulating film

31 source electrode 33 drain electrode

35 gate electrode 40 semiconductor nanowire

43: first photoresist 45: second photoresist

50: memory element layer 51: tunneling layer

53 charge storage layer 55 oxide layer

The present invention relates to a nonvolatile memory electronic device and a method of manufacturing the same, by forming a charge storage layer by forming a metal nanoparticle of the nanowire and a heterogeneous on the surface of the tunneling layer formed to surround the semiconductor nanowire, excellent charge transfer capability The present invention relates to a non-volatile memory electronic device of a nanowire-nanoparticle heterojunction capable of operating at low voltage and increasing operating speed by complementary action of nanowires and metal nanoparticles having excellent information storage capability, and a method of manufacturing the same.

Currently, the DRAM-oriented memory market, which is leading the economic and industrial development of Korea, requires various memory products due to the development of mobile business and IT technology such as digital camera and mobile phone.

Among them, the flash memory market, which has recently been exploding in demand, is growing rapidly every year and is expected to occupy most of the memory market in the future. In order to support the performance of recently developed IT devices, research on low cost next generation nonvolatile memory technology with excellent information storage capability and operation speed that complements the disadvantages of current flash memory is urgently needed.

This is expected to be a growth engine of economic and industrial development in the future. If this technology development is delayed, it will be difficult for Korea's memory device technology to maintain its current global position. Therefore, the nanowire floating gate memory device, which supplements the problems of the current flash memory structure, can be commercialized as soon as the existing process can be applied as it is. Therefore, related studies should be made as soon as possible.

The current flash memory requires a high operating voltage and shows various problems when the cell size becomes small, showing a limitation in reducing the size. In current flash memory, the program / erase voltage is more than 10V, which is very large compared to the CMOS driving voltage.

This is because, when programming, electrons move to the floating gate by the injection of Channel-Hot-Electron (CHE), and when erased, they are discharged again by high-field-assisted tunneling (Fowler-Nordheim tunneling) and directly tunneled. It requires a higher voltage than the case (3-4V).

Therefore, in order to enable direct tunneling and to increase program / erase time, an ultra thin oxide film should be formed. In this case, the characteristics of the SiO ₂ thin film currently used as a tunneling layer are very important.

However, many defects in the SiO ₂ thin film form a leakage path, which makes it difficult to prevent electrons from the floating gate from leaking into the channel. In order to solve this problem, eliminating defects of the tunneling layer is also an important problem.

On the other hand, the current flash memory is attracting attention as a mass storage medium because it has a higher density than DRAM, but to support the performance of the rapidly developing IT equipment, the next generation of low-cost, high-speed operation at low voltage and excellent information storage capability Development of nonvolatile memory is urgent.

In addition, in order to increase the capacity of the flash memory, it is necessary to reduce the size of the memory cell. In order to reduce the size of the cell, the thickness of the tunneling layer must be minimized, and as the thickness becomes smaller, the program / erase voltage can be lowered.

However, current flash memory has a program / erase voltage of 9-12V, which is very large compared to CMOS and DRAM driving voltages. After multiple program / erase cycles with such a large voltage, the thin tunneling layer is destroyed, causing the charge of the floating gate to leak into the channel and lose its function.

In addition, the charge storage layer of the conventional flash memory device is composed of a continuous thin film in the form of a film. However, when a part of the tunneling layer was destroyed, the charges in the charge storage layer flowed through the damaged tunneling layer into the channel to generate a large leakage current.

As the number of program / erase increases, the tunneling layer is naturally damaged, and thus the device cannot be used for a long time.

In order to prevent this problem, a thicker tunneling layer and an oxide layer are used, which degrades the device density and requires a high program / erase voltage.

The present invention was devised to solve the above problems of the prior art, by forming a charge storage layer by forming a metal nanoparticle heterogeneous with the nanowire on the surface of the tunneling layer formed to surround the semiconductor nanowire, the charge transfer capability Provided is a non-volatile memory electronic device of a nanowire-nanoparticle heterojunction that can operate at a low voltage and increase the operation speed by the complementary action of the excellent nanowire and the metal nanoparticle having excellent information storage capability, and a method of manufacturing the same. For that purpose.

In order to solve the above technical problem, the constituent means of the nonvolatile memory electronic device of the nanowire-nanoparticle heterojunction, which is the present invention, includes a source and a drain electrode formed on a silicon substrate in a nonvolatile memory electronic device. And a semiconductor nanowire for connecting the source and drain electrodes in a suspended state from the silicon substrate, the semiconductor nanowire to surround the semiconductor nanowire, and a tunneling layer formed by atomic layer deposition, and to surround the tunneling layer. A charge storage layer comprising metal nanoparticles obtained by thermal evaporation of the metal nanofilm formed on the surface of the tunneling layer, an oxide layer formed to surround the charge storage layer, and formed by atomic layer deposition; It is formed to surround the oxide layer, and on the silicon substrate between the source and drain electrodes And a gate electrode formed on the characterized in that is made.

In addition, carbon nanotubes or organic tubes instead of the semiconductor nanowires may connect the source and drain electrodes in a suspended state from the silicon substrate.

In addition, the semiconductor nanowire is characterized by consisting of any one of Si, Ge, GaN, InP, GaAs, GaP, Si ₃ N ₄ , SiO ₂ , SiC, ZnO and Ga ₂ O ₃ .

In addition, the metal nanoparticles are characterized by consisting of any one component of Au, Ag, Pt, Ti and Al. That is, the metal nanoparticle is formed of a component that is heterogeneous with the semiconductor nanowire.

In addition, the tunneling layer and the oxide layer is characterized in that made of any one of Al ₂ O ₃ , HfO ₂ and SiO ₂ material.

On the other hand, in the non-volatile memory electronic device manufacturing method of the present invention nanowire-nanoparticle heterojunction constituent means, in the method of manufacturing a nonvolatile memory electronic device, a HMDS (Hexamethyldisilazane) layer is coated on the semiconductor substrate Forming a route on the HMDS, applying a first photoresist on the HMDS layer on which the semiconductor nanowires are formed, and forming a plurality of first space portions by photolithography; 1 by depositing a metal layer on the photoresist and removing the first photoresist and the HMDS layer to form a source electrode and a drain electrode at both ends of the semiconductor nanowire, the tunneling layer by atomic layer deposition to surround the semiconductor nanowire; Step of forming, is formed to surround the tunneling layer, the semiconductor nanowires and heterogeneous metal nanoparticles phase Forming a charge storage layer by forming a surface of the tunneling layer, forming an oxide layer by an atomic layer deposition method to surround the charge storage layer, and forming an oxide layer on the substrate on which the oxide layer, the source, and the drain electrode are formed. 2 a photoresist is applied, a second space portion is formed between the source and drain electrodes using a photolithography method, a metal layer is laminated on the second space portion and the second photoresist, and the second photoresist It characterized in that it comprises a step of removing to form a gate electrode.

In addition, carbon nanotubes (CNT) or organic tubes are formed on the HMDS (Hexamethyldisilazane) instead of the semiconductor nanowires.

In addition, the semiconductor nanowire is characterized by consisting of any one of Si, Ge, GaN, InP, GaAs, GaP, Si ₃ N ₄ , SiO ₂ , SiC, ZnO and Ga ₂ O ₃ .

The semiconductor nanowires may be obtained by growing on a substrate by thermal evaporation.

The forming of the charge storage layer may include coating a metal nanofilm on the surface of the tunneling layer by thermal evaporation, and heating the metal nanofilm with a rapid thermal processor (RTA) to form metal nanoparticles. Characterized by including a process.

In addition, the metal nanofilm is characterized in that the thickness between 2nm ~ 10nm, the metal nanofilm is characterized in that it is heated for 5 seconds to 30 seconds at a temperature between 250 ℃ ~ 450 ℃.

In addition, the tunneling layer and the oxide layer is characterized in that any one of Al ₂ O ₃ , HfO ₂ and SiO ₂ material is formed by the atomic layer deposition method, when the tunneling layer and the oxide layer is formed of Al ₂ O ₃ As a precursor, TMA (Trimethylaluminum) and H ₂ O are used.

In addition, the tunneling layer is characterized in that the thickness between 5nm ~ 30nm, the oxide layer is characterized in that the thickness between 10nm ~ 60nm.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of a non-volatile memory electronic device of the present invention nanowire-nanoparticle heterobond consisting of the above configuration means and a method of manufacturing the same.

1 is a cross-sectional view of a nonvolatile memory electronic device of a nanowire-nanoparticle heterojunction according to an embodiment of the present invention, and FIG. 2 is an enlarged view of portion “A” of FIG. 1.

1 and 2, the non-volatile memory electronic device of the nanowire-nanoparticle dissociation sum according to the present invention includes source and drain electrodes 31 and 33 formed on a silicon substrate 10, and the source. And a tunneling layer 51, a charge storage layer 53, and an oxide layer formed to continuously surround the semiconductor nanowire 40 connecting the drain electrodes 31 and 33, and the semiconductor nanowire 40. And a gate electrode 35 formed between the source and drain electrodes 31 and 33 having a cylindrical shape.

The source and drain electrodes 31 and 33 formed on the silicon substrate 10 are formed by a photolithography process, and the semiconductor nanowire 40 is in a suspended state therebetween. That is, the source and drain electrodes 31 and 33 are connected to the semiconductor nanowires 40, but the source and drain electrodes 31 are supported by the semiconductor nanowire 40 from the silicon substrate 10. , 33).

SiO ₂ may be further included between the silicon substrate 10 and the source and drain electrodes 31 and 33. On the other hand, the semiconductor nanowire 40 that is present in a suspended state between the source and drain electrodes 31 and 33 may be replaced with carbon nanotubes or organic tubes. That is, the material for connecting the source and drain electrodes 31 and 33 in a supported state may be any one of semiconductor nanowires, carbon nanotubes, and organic tubes. Such semiconductor nanowires are used as charge transfer channels in nonvolatile memory electronic devices of the present invention nanowire-nanoparticle heterobonds.

The semiconductor nanowire is used as a channel in a nonvolatile memory electronic device, which is any one of Si, Ge, GaN, InP, GaAs, GaP, Si ₃ N ₄ , SiO ₂ , SiC, ZnO, and Ga ₂ O ₃ . It is preferred to consist of components.

The memory device layer 50 is formed around the semiconductor nanowire 40. The memory device layer 50 includes a tunneling layer 51 through which charges can pass, a charge storage layer 53 capable of storing charges, and an oxide layer 55 that prevents external charges from entering and exiting. .

The tunneling layer 51 is formed to surround the semiconductor nanowire 40, and is formed by atomic layer deposition. The oxide layer 55 is formed to surround the charge storage layer 53, and is formed by atomic layer deposition. The tunneling layer 51 and the oxide layer 55 are formed by depositing any one of Al ₂ O ₃ , HfO _2, and SiO ₂ materials.

Meanwhile, the charge storage layer 53 formed between the tunneling layer 51 and the oxide layer 55 is formed to surround the tunneling layer 51, and metal nanoparticles are formed on the surface of the tunneling layer 51. It is formed to exist.

The metal nanoparticles constituting the charge storage layer 53 are obtained by thermally depositing a metal nanofilm on a surface of the tunneling layer 51 and performing heat treatment on the deposited metal nanofilm.

The metal nanofilm obtained by performing heat treatment on the metal nanofilm and the metal nanofilm is composed of any one of Au, Ag, Pt, Ti, and Al. That is, the metal nanoparticles are composed of the semiconductor nanowire and the dissimilar metal, and the metal nanoparticles play a role of storing charge.

As described above, the tunneling layer 51, the charge storage layer 53, and the oxide layer 55 are sequentially formed on the surface of the semiconductor nanowire 40, and the tunneling layer 51 and the charge storage layer are sequentially formed. The semiconductor nanowire 40 having the 53 and the oxide layer 55 formed on the surface has a cylindrical shape.

Meanwhile, a gate electrode 35 is formed on the upper surface of the silicon substrate between the source and drain electrodes 31 and 33 while surrounding the oxide layer 55. The gate electrode 35 is formed between the source and drain electrodes 31 and 33 in the form of a cylinder or surrounding the memory device layer 50.

Next, a manufacturing process of the non-volatile memory electronic device of the nanowire-nanoparticle heterojunction according to the present invention will be described with reference to FIGS. 3A to 3G.

First, referring to FIG. 3A, in order to increase the adhesion of the first photoresist 43 on the silicon substrate 10, a HMDS (Hexamethyldisilazane; 21) film is formed and a semiconductor nanowire 40 is disposed on the HMDS film. After spraying, the first photoresist 43 is applied, and a resist pattern for the electrode part is formed around the nanowires to have a width of several um to several tens of nm through exposure and development. That is, a first space portion (not shown) in which source and drain electrodes, which will be described later, will be formed is formed by using photolithography. On the other hand, SiO ₂ between the silicon substrate 10 and the HMDS film 21 The insulating film 20 can be further formed.

Here, the semiconductor nanowire 40 is formed on the HMDS (Hexamethyldisilazane; 21) film. In some cases, carbon nanotubes or organic tubes are formed on the HMDS (Hexamethyldisilazane; 21) film instead of the semiconductor nanowire. Can be. The semiconductor nanowire 40 is preferably made of any one of Si, Ge, GaN, InP, GaAs, GaP, Si ₃ N ₄ , SiO ₂ , SiC, ZnO and Ga ₂ O ₃ .

The semiconductor nanowire 40 is obtained by growing on a silicon substrate by thermal evaporation, and the grown semiconductor nanowire 40 is dispersed in an aqueous solution and then sprayed onto the HMDS (Hexamethyldisilazane; 21) film.

Then, after the metal layer is laminated on the first space portion and the first photoresist 43, the first photoresist 43 and the HMDS (Hexamethyldisilazane; 21) film are removed. Then, as illustrated in FIG. 3B, the source electrode 31 and the drain electrode 33 are formed at both ends of the semiconductor nanowire 40. The metal layer forming the source and drain electrodes 31 and 33 is formed by sequentially stacking titanium (Ti) gold (Au).

3C to 3E, the memory device layer 50 is formed to surround the semiconductor nanowire 40. This will be described as follows.

As shown in FIG. 3C, the tunneling layer 51 is formed to surround the semiconductor nanowire 40. The tunneling layer 51 is formed by atomic layer deposition using any one of alumina (Al ₂ O ₃ ), HfO _2, and SiO ₂ materials. In this state, the semiconductor nanowire 40 having the tunneling layer 51 deposited on the outer surface has a cylindrical shape.

When the tunneling layer 51 is formed using alumina (Al ₂ O ₃ ) to form the tunneling layer 51 by the atomic layer deposition method as described above, aluminum (Al) constituting alumina and TMA (Trimethylaluminum) and H ₂ O are used as precursors of oxygen (O).

The process of depositing the alumina to form the tunneling layer 51 allows the coating process to be performed for 100 to 200 cycles at 250 ° C. to 300 ° C., and the semiconductor nanowires by the self-control mechanism of atomic layer deposition (ALD). 40) Alumina is uniformly deposited to a thickness of about 5nm ~ 30nm on top.

After the tunneling layer 51 is formed to surround the semiconductor nanowire 40, the charge storage layer 53 is formed to surround the tunneling layer 51, as shown in FIG. 3D. The process of forming the charge storage layer 53 is a process of forming metal nanoparticles different from the semiconductor nanowire 40 on the surface of the tunneling layer 51.

In the process of forming the metal nanoparticles on the surface of the tunneling layer 51 to form the charge storage layer 53, first, the metal nanofilm is coated on the surface of the tunneling layer 51 by thermal evaporation. Then, metal nanoparticles are formed by heating the metal nanofilm using a rapid heat processor (RTA). The formed metal nanoparticles constitute a charge storage layer 53 for storing charge.

The thickness of the metal nanofilm which is thermally deposited and coated on the surface of the tunneling layer 51 is preferably about 2 nm to about 10 nm, and the metal nanofilm having the thickness is 5 seconds to 30 at a temperature between 250 ° C. and 450 ° C. By heating for a second, metal nanoparticles are formed. In this state, the semiconductor nanowire 40 having the tunneling layer 51 and the charge storage layer 53 deposited on the outer surface has a cylindrical shape. As described above, the photograph taken by the scanning electron microscope of the nanowire formed with the metal nanoparticles constituting the charge storage layer 53 is as shown in Figure 4a.

After forming the charge storage layer 53 made of the metal nanoparticles to surround the tunneling layer 51, as illustrated in FIG. 3E, the oxide layer 55 is wrapped to surround the charge storage layer 53. To form.

The oxide layer 55 is formed by atomic layer deposition using any one of alumina (Al ₂ O ₃ ), HfO _2, and SiO ₂ materials. In this state, the semiconductor nanowire 40 having the tunneling layer 51, the charge storage layer 53, and the oxide layer 55 deposited on the outer surface has a cylindrical shape.

When the oxide layer 55 is formed by the atomic layer deposition method as described above, when the oxide layer 55 is formed by using alumina (Al ₂ O ₃ ), aluminum (Al) constituting alumina and TMA (Trimethylaluminum) and H ₂ O are used as precursors of oxygen (O).

In the process of depositing the alumina to form the oxide layer 55, the coating process is performed for 200 to 400 cycles at 250 ° C to 300 ° C, and the charge storage layer (ALD) is controlled by the self-controlling mechanism of the ALD. 53) Alumina is uniformly deposited to a thickness of about 10nm ~ 60nm on top.

Then, as illustrated in FIG. 3F, a second photoresist 45 is coated on the silicon substrate 10 on which the memory device layer 50 and the source and drain electrodes 31 and 33 are formed. The second space portion (not shown) in which the gate electrode 35 to be described later will be formed is formed between the source and drain electrodes 31 and 33 by using photolithography.

Thereafter, when the metal layer is stacked on the second space portion and the second photoresist 45 and the second photoresist 45 is removed, the source drain electrodes 31 and 33 are illustrated in FIG. 3G. Between the gate electrodes 35. The metal layer forming the gate electrode 35 is formed by sequentially depositing titanium (Ti) gold (Au).

Figure 4b is a planar photograph of a non-volatile memory electronic device of the nano-wire nanoparticles heterobonds of the present invention produced according to the above process. As shown in FIG. 4B, a nanowire 40 is formed between the source and drain electrodes 31 and 33, and a gate electrode 35 is formed between the source and drain electrodes 31 and 33. On the surface of the nanowire 40, a tunneling layer 51, a charge storage layer 53 composed of metal nanoparticles different from the nanowire 40, and an oxide layer 55 are sequentially deposited.

Next, the electrical characteristics of the non-volatile memory electronic device of the nanowire-nanoparticle heterojunction produced by the process of FIGS. 3A to 3G will be described with reference to FIG. 5.

As shown in FIG. 5, when a positive voltage is applied to the gate electrode, charges flowing through the nanowires are tunneled and stored in the charge storage layer. In contrast, when a negative voltage is applied, the charges stored in the charge storage layer are again stored. You can see it flowing into the nanowires.

In addition, as the gate voltage is applied to a larger value, the number of charges moving through the nanowire channel and the charge storage layer increases, and the change of the current becomes larger.

According to the nonvolatile memory electronic device of the nanowire-nanoparticle heterojunction of the present invention having the configuration and the preferred embodiment as described above, and a method for manufacturing the same, the nanowire and the heterogeneous metal nanowire on the surface of the tunneling layer formed to surround the semiconductor nanowire Since the particles form a charge storage layer, the complementary action of the nanowires having excellent charge transfer ability and the metal nanoparticles having excellent information storage capability can operate at low voltage and increase the operating speed.

In addition, according to the present invention, the nanowires are used as the charge transfer channels to maximize the electron transfer ability, and the metal nanoparticles are used as the charge storage layer to reduce the operating current while reducing the leakage current flowing to the damaged tunneling layer. It has the effect of having a fast operating speed.

Claims (16)

In a nonvolatile memory electronic device, Source and drain electrodes formed on the silicon substrate; A semiconductor nanowire connecting the source and drain electrodes in a suspended state from the silicon substrate; A tunneling layer formed to surround the semiconductor nanowire, and formed by an atomic layer deposition method; A charge storage layer formed to surround the tunneling layer, the charge storage layer comprising metal nanoparticles obtained by applying heat treatment to the metal nanofilm formed on the tunneling layer surface; An oxide layer formed to surround the charge storage layer and formed by atomic layer deposition; And a gate electrode formed to surround the oxide layer, the gate electrode formed on the silicon substrate between the source and drain electrodes. The method according to claim 1, A carbon nanotube or an organic tube instead of the semiconductor nanowires connects the source and drain electrodes in a suspended state from the silicon substrate. The method according to claim 1, The semiconductor nanowires are heterogeneous nanowires-nanoparticles characterized in that the composition consists of any one of Si, Ge, GaN, InP, GaAs, GaP, Si ₃ N ₄ , SiO ₂ , SiC, ZnO and Ga ₂ O ₃ Combined nonvolatile memory electronics. The method according to claim 1, The metal nanoparticle is a non-volatile memory electronic device of the nanowire-nanoparticle hetero bond, characterized in that consisting of any one of Au, Ag, Pt, Ti and Al. The method according to claim 1, The tunneling layer and the oxide layer is a non-volatile memory electronic device of the nanowire-nanoparticle hetero bond, characterized in that consisting of any one of Al ₂ O ₃ , HfO ₂ and SiO ₂ material. In the non-volatile memory electronic device manufacturing method, Applying a Hexamethyldisilazane (HMDS) layer on top of the semiconductor substrate and forming a semiconductor nanowire on the HMDS; Applying a first photoresist on the HMDS layer on which the semiconductor nanowires are formed and forming a plurality of first spaces by photolithography, and then laminating a metal layer on the first spaces and the first photoresist. Removing a first photoresist and the HMDS layer to form a source electrode and a drain electrode across the semiconductor nanowire; Forming a tunneling layer by atomic layer deposition to surround the semiconductor nanowires; Forming a charge storage layer formed around the tunneling layer and forming metal nanoparticles different from the semiconductor nanowire on the surface of the tunneling layer; Forming an oxide layer by atomic layer deposition to surround the charge storage layer; After applying a second photoresist on the substrate on which the oxide layer, the source and the drain electrode are formed, and forming a second space portion between the source and the drain electrode by a photolithography method, the second space Stacking a metal layer on the secondary and the second photoresist, and removing the second photoresist to form a gate electrode manufacturing a non-volatile memory electronic device of the nanowire-nanoparticle heterojunction comprising the Way. The method according to claim 6, Forming carbon nanotubes (CNTs) or organic tubes on the HMDS (Hexamethyldisilazane) instead of the semiconductor nanowires (nanowire) characterized in that the manufacturing method of the non-volatile memory electronic device of the nanowire-nanoparticle hetero bond. The method according to claim 6, The semiconductor nanowires are heterogeneous nanowires-nanoparticles, characterized in that any one of Si, Ge, GaN, InP, GaAs, GaP, Si ₃ N ₄ , SiO ₂ , SiC, ZnO and Ga ₂ O ₃ A method of manufacturing a nonvolatile memory electronic device in combination. The method according to claim 8, Wherein the semiconductor nanowires are grown on a substrate by thermal evaporation. The method of claim 6, wherein forming the charge storage layer, Nanowires comprising the step of coating the metal nanofilm on the surface of the tunneling layer using a thermal evaporation method, the step of heating the metal nanofilm with a rapid heat treatment (RTA) to form metal nanoparticles- A method for manufacturing a nonvolatile memory electronic device of nanoparticle heterojunction. The method according to claim 10, The metal nanofilm is a nanowire-nanoparticle heterobond nonvolatile memory electronic device manufacturing method, characterized in that the thickness between 2nm ~ 10nm. The method according to claim 10, The metal nanofilm is a method for manufacturing a non-volatile memory electronic device of the nanowire-nanoparticle hetero bond, characterized in that heated for 5 seconds to 30 seconds at a temperature between 250 ℃ to 450 ℃. The method according to claim 6, The tunneling layer and the oxide layer of any one of Al ₂ O ₃ , HfO ₂ and SiO ₂ material is a non-volatile memory electronic device of the nanowire-nanoparticle hetero bond characterized in that the atomic layer deposition method. The method according to claim 13, When the tunneling layer and the oxide layer is formed of Al ₂ O ₃ , TMA (Trimethylaluminum) and H ₂ O as a precursor, characterized in that the manufacturing method of the non-volatile memory electronic device of the nanowire-nanoparticle hetero bond. The method according to claim 13, The tunneling layer has a thickness of between 5nm ~ 30nm nanowire-nanoparticle heterobond nonvolatile memory electronic device manufacturing method. The method according to claim 13, The oxide layer has a thickness of between 10nm ~ 60nm nanowire-nanoparticle heterobond nonvolatile memory electronic device manufacturing method.

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