KR20080078190A - Method of manufacturing a semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to increase a contact area between a contact plug and a lower electrode by etching the contact plug selectively which is connected with the lower electrode through a dry etch and a wet etch. A method for manufacturing a semiconductor device includes the steps of: providing a semiconductor substrate(100) with a storage node contact plug(114); forming an etch stopper layer(116) and a sacrificial insulation layer on the semiconductor substrate; exposing the upper part of the contact plug by etching the sacrificial insulation layer and the etch stopper layer through a dry etch; forming an opening by etching a part of the exposed contact plug through a wet etch; forming a capacitor lower electrode(122a) on the sacrificial insulation layer, and the inner wall and a bottom of the opening; and removing the sacrificial insulation layer.

Description

Method of manufacturing a semiconductor device

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 junction

104: first interlayer insulating film 106: bit line

108: hard mask film 110: spacer

112: second interlayer insulating film 114: contact plug

116: etch stop film 118: insulating film for lower electrode

120: open area 122: conductive film

122a: lower electrode 124: silicide film

114: silicide film

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for securing a stable lower electrode and reducing contact resistance.

In general, a capacitor stores charges and supplies charges necessary for the operation of the semiconductor device. As the semiconductor device becomes more integrated, the capacitance of the device becomes smaller while the unit cell becomes smaller in size. ) Tends to increase slightly.

As the semiconductor device is highly integrated, the capacitor is also required to be miniaturized. However, the capacitor has a limit in storing electric charges, and thus the capacitor is difficult to be integrated with the cell size. Various companies have variously changed the structure for storing the charge of the capacitor.In order to increase the charge of the capacitor, a method of using a material having a large dielectric constant, a method of reducing the thickness of the dielectric material, and the surface area of the capacitor There is a method of increasing, and in recent years, a method of increasing the surface area of a capacitor is mainly used.

That is, in the structure of the charge storage electrode of the capacitor, the electrode which stores the charge largely has a stacked structure to obtain a large capacitor area by stacking several layers on a narrow plane and a groove having a constant depth in the semiconductor substrate. After forming, it is largely classified into a trench structure for forming a capacitor at the site and storing charge.

In particular, the laminated structure has a fin type formed in the shape of a fin, a cylinder shaped and a cavity type formed in a cylindrical shape such as a cylinder, and a shape of hemispherical shaped grains (HSG) and bellows. Efforts have been made to increase the charging capacity of capacitors, which are composed of modified capacitor structures, such as a).

Currently, in order to solve the storage capacity problem, a capacitor having a high aspect ratio cylinder structure is mainly used.

However, a problem occurs that the lower electrode collapses during the insulating film removal process formed between the lower electrodes. To solve this problem, it is necessary to reduce the height of the lower electrode, which increases the aspect ratio of the capacitor, or increase the critical dimension (CD) of the lower electrode.

However, reducing the height of the lower electrode causes the capacitance of the capacitor to decrease, and increasing the critical dimension (CD) of the lower electrode causes a micro bridge between neighboring capacitors. These microbridges generate a leakage current or short in each capacitor through the lower electrode separation.

According to the present invention, a dry etching process and a wet etching process may be performed to selectively etch a contact plug connected to the lower electrode to increase a contact area between the contact plug and the lower electrode, thereby securing a stable lower electrode and reducing contact resistance.

In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a semiconductor substrate having a storage node contact plug is provided. An etch stop layer and a sacrificial insulating layer are formed on the semiconductor substrate including the contact plug. In the first etching process, the sacrificial insulating layer and the etch stop layer are etched to expose the upper portion of the contact plug. A portion of the contact plug exposed by the second etching process is selectively etched to form an opening. A capacitor lower electrode is formed on the inner wall and the bottom of the sacrificial insulating film and the opening. Remove the sacrificial insulating film.

In the above, the first etching process applies a dry etching process, and the second etching process applies a wet etching process capable of isotropic etching. The opening is in the form of a bulb. The lower electrode is formed of a stacked structure of titanium (Ti) and titanium nitride film (TiN). The lower electrode has 80% to 100% coatability. Due to the heat used in the lower electrode forming process, a silicide layer is formed on the interface between the semiconductor substrate and the lower electrode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a first interlayer insulating layer 104 is formed on the semiconductor substrate 100. In this case, before the first interlayer insulating layer 104 is formed, a process of forming a transistor (not shown), a junction 102, and a contact plug (not shown) are performed. The first interlayer insulating film 104 is formed of an oxide.

Then, the bit line conductive material 106 and the hard mask film 108 are formed in a stacked structure on the first interlayer insulating film 104, and then the bit line conductive material 106 and the hard mask film 108 are formed. Etching is performed sequentially to form the bit line 106. Subsequently, spacers 110 are formed on sidewalls of the bit line 106 and the hard mask film 108.

Referring to FIG. 1B, a second interlayer insulating layer 112 is formed on the semiconductor substrate 100 including the bit line 106. In this case, the second interlayer insulating layer 112 is formed of an oxide.

Then, portions of the first and second interlayer insulating films 104 and 112 are etched to form contact holes that expose the junction 102 of the semiconductor substrate 100. The contact plug 114 is formed by filling a conductive film in the contact hole.

Referring to FIG. 1C, an etch stop layer 116 and an insulating layer 118 for lower electrodes are formed on the semiconductor substrate 100 including the contact plug 114. Specifically, the etch stop film 116 is formed of a nitride film, and the lower electrode insulating film 118 is formed of an oxide.

Then, the lower electrode insulating layer 118 and the etch stop layer 116 are sequentially etched so that the upper portion of the contact plug 114 is exposed by a dry etching process to open the three-dimensional structure in which the lower electrode of the capacitor is formed. Area 120 is formed. At this time, it is difficult to secure the mask margin during the etching process for forming the open region 120 may cause misalignment. However, the second interlayer insulating layer 112 may be prevented from being etched by the etch stop layer 116 during the etching process of the lower electrode insulating layer 118.

Referring to FIG. 1D, the exposed contact plug 114 is selectively etched by applying a wet etching process capable of isotropic etching. At this time, since the surface of the contact plug 104 is etched isotropically and concavely etched in a hemispherical shape, the contact area between the contact plug 114 and the lower electrode increases.

Referring to FIG. 1E, a conductive layer 122 for lower electrodes is formed on the entire surface of the semiconductor substrate 100 including the open region 120. At this time, the conductive film 122 forms a titanium (Ti) and titanium nitride film (TiN) in a laminated structure. The conductive film 122 is well formed in the selectively etched contact plug 114 because the coating property is 80% to 100%. The silicide layer 124 is formed at the interface between the contact plug 114 and the conductive layer 122 due to the heat used in the conductive layer 122 forming process.

Referring to FIG. 1F, a conductive layer formed on the lower electrode insulating layer 118 so that the conductive layer 122 remains only in the open region 120 may be subjected to an etch back process or a chemical mechanical polishing (CMP) process. Membrane 122 is removed.

Referring to FIG. 1G, a dip-out process may be performed to remove the lower electrode insulating layer 118 between the conductive layers 122. As a result, the outer wall of the conductive film 122 is exposed to form the lower electrode 122a of the cylinder structure.

As described above, a dry etching process and a wet etching process are performed to selectively etch the contact plug 114 connected to the lower electrode 122a to increase the contact area between the contact plug 114 and the lower electrode 122a. . This can reduce the contact resistance. In addition, since the lower portion of the lower electrode 122a is fixed to the concave portion of the contact plug 114, the problem that the lower electrode 122a falls down can be prevented.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the effects of the present invention are as follows.

First, the contact area between the contact plug and the lower electrode may be increased by selectively etching the contact plug connected to the lower electrode by performing a dry etching process and a wet etching process.

Second, the contact resistance can be reduced by increasing the area between the lower electrode and the contact plug.

Third, since the lower part of the lower electrode is fixed to the concave portion of the contact plug, it is possible to prevent the lower electrode from falling down.

Claims (7)

Providing a semiconductor substrate having a storage node contact plug formed thereon; Forming an etch stop layer and a sacrificial insulating layer on the semiconductor substrate including the contact plugs; Etching the sacrificial insulating layer and the etch stop layer by a first etching process to expose an upper portion of the contact plug; Selectively etching a portion of the contact plug exposed by a second etching process to form an opening; Forming a capacitor lower electrode on an inner sidewall and a bottom of the sacrificial insulating layer and the opening; And Removing the sacrificial insulating film. The method of claim 1, The first etching process is a manufacturing method of a semiconductor device applying a dry etching process. The method of claim 1, The second etching process is a method for manufacturing a semiconductor device applying a wet etching process capable of isotropic etching. The method of claim 1, The opening is a method of manufacturing a semiconductor device in the form of a bulb (bulb). The method of claim 1, The lower electrode is a semiconductor device manufacturing method of forming a titanium (Ti) and titanium nitride film (TiN) in a laminated structure. The method of claim 1, The lower electrode has a coating property of 80% to 100% manufacturing method of a semiconductor device. The method of claim 1, And a silicide layer is formed on an interface between the semiconductor substrate and the lower electrode due to heat used in the lower electrode forming process.

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