KR20080076194A - Method for testing self calibration and circuits for testing - Google Patents

Abstract

A method for testing self calibration and a test circuit thereof are provided to verify whether calibration scheme in a semiconductor memory device operates normally. According to a method for testing self calibration, pullup resistances of an output driver(118) in a semiconductor memory device are different in entering a test mode and not entering the test mode. The pullup resistance of the output driver in entering the test mode is larger than the pullup resistance of the output driver in not entering the test mode. A test circuit(100) for testing self calibration comprises a first transistor and a second transistor. The first transistor is turned on in entering the test mode. The second transistor is turned off in entering the test mode, and is turned off in the other mode except the test mode and has smaller resistance than the first transistor.

Description

Method for testing self calibration and circuits for testing

1 is a conventional self-calibration operation test circuit diagram,

2 is a self-calibration operation test circuit diagram according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

RZQ: Resistance (impedance) test: Signal to enter test mode

112: comparator

The present invention relates to a test method and a test circuit for a self-calibration operation. More particularly, the present invention relates to a test method and a test circuit for checking whether a self-calibration operation is performed in a semiconductor memory device.

In most cases, semiconductor integrated circuit devices such as microcontrollers and semiconductor memory devices exchange data with other semiconductor integrated circuit devices through a transmission line.

In addition, semiconductor memory devices have been continually improved to increase the degree of integration and to improve their operation speed. In order to improve the operation speed, a so-called synchronous memory device that can operate in synchronization with a clock given from the outside of the memory device has emerged.

The first proposal is a so-called single data rate (SDR) synchronous memory device that inputs and outputs one data over one period of the clock at one data pin in synchronization with a rising edge of the clock from the outside of the memory device.

However, an SDR synchronous memory device is also insufficient to satisfy the speed of a system requiring high-speed operation. Accordingly, a double data rate (DDR) synchronous memory device, which processes two data in one clock cycle, has been proposed.

Each data entry / exit pin of the digital synchronous memory device continuously inputs and outputs two data in synchronization with a rising edge and a falling edge of an externally input clock. At least twice as much bandwidth as the SDR synchronous memory device can realize a high speed operation.

Several new concepts have been added to make the data transfer rate of a digital memory device faster. The DIII synchronous type proposed by the Joint Electron Device Engineering Council (JEDEC), an organization called the World Semiconductor Standards Association or the International Semiconductor Standards Consultative Organization. The specification of the memory device has a concept of an Off Chip Driver (hereinafter referred to as OCD) calibration control that can adjust the impedance of an output part outputting data from a digital memory device.

The OCD adjustment control measures the voltage or current flowing through the output drive of a memory device that interfaces data from an external device such as a chipset, and adjusts the output drive's impedance to be optimal in the current system.

Therefore, in order to satisfy the specification of JEDEC's DIII synchronous memory device, the output drive of the memory device needs to have an additional function of adjusting impedance.

There is also called On Die Termination (ODT), which is called on die termination, which adjusts the output stage resistance value when the memory device is integrated into a board, etc., so that it can be transmitted to the next chip without impedance mismatch of the data signal.

 Accordingly, most semiconductor integrated circuit devices include an off chip driver for outputting a signal from the semiconductor integrated circuit device to the outside and an on die termination circuit for preventing reflection of a signal transmitted from the outside to the semiconductor integrated circuit device. In this case, in order to secure signal integrity, the impedance characteristics of the off-chip driver or the on-die termination circuit must be calibrated. The higher the system is operated, the greater the need for calibration.

Some semiconductor memory devices have a separate ZQ terminal for calibrating the impedance characteristics of an internal off-chip driver or an on-die termination circuit, and a reference resistor is directly connected thereto in proportion to the impedance of the reference resistor. Perform impedance calibration.

Figure 1 shows part of a conventional calibration scheme.

As shown in FIG. 1, a conventional calibration scheme is provided for matching the strength of the output driver 18 of the semiconductor memory device inner circumference 10 with an external RZQ resistor. To this end, a comparator 12 for connecting the RZQ resistor to the RZQ pad and comparing the voltage input through the RZQ pad with a reference voltage is provided.

 The comparator 12 outputs a comparison signal comparing the voltage level of the RZQ pad node with a reference voltage level and stores the comparison signal in the register 14. The comparison through the comparator 12 determines whether the strength of the output driver 18 matches the RZQ resistance. For reference, the output driver 18 has a series connection structure of a resistor R1 and a PMOS transistor P1 having a constant resistance value. As described above, a conventional calibration scheme is a semiconductor memory device (RZQ self-calibration scheme). For example, there is a need for a method for verifying that a DRAM performs normal operation.

Accordingly, it is an object of the present invention to provide a self-calibration operation test method and test circuit capable of overcoming the above-mentioned conventional problems.

Another object of the present invention is to provide a self-calibration operation test method and test circuit capable of verifying that a calibration scheme operates normally in a semiconductor memory device.

According to an embodiment of the present invention for achieving some of the above technical problems, the self-calibration operation test method according to the present invention, the pull-up resistance of the output driver in the semiconductor memory device, enters the test mode and enters the test mode It is characterized by different cases when not.

The pull-up resistance of the output driver may be greater in the case of entering the test mode than in the case of entering the test mode when entering the test mode.

According to an embodiment of the present invention for achieving some of the above technical problems, the test circuit according to the present invention, the first transistor is turned on when entering the test mode and the other mode other than the test mode is turned off when entering the test mode In this case, the self-calibration operation test may be performed with a second transistor having a resistance smaller than that of the first transistor.

According to the above configuration, it is possible to verify whether the semiconductor memory device is self-calibrating.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, without any other intention than to provide a thorough understanding of the present invention to those skilled in the art.

2 is a test circuit for testing ZQ self calibration operation verification in accordance with one embodiment of the present invention.

As shown in FIG. 2, the test circuit 100 includes first and second PMOS transistors PA and PB connected in parallel to each other between the RZQ pad and the first node.

The first PMOS transistor PA is turned off in response to a test mode enable signal test = '1' and turned on in response to a test mode disable signal test = '0'.

The second PMOS transistor PB is turned on in response to the inversion signal / test = '0' of the test mode enable signal and responds to the inversion signal / test = '1' of the test mode disable signal. Is turned off.

A third PMOS transistor PC is provided between the first node and the input terminal of the output driver 118. The third PMOS transistor PC is always turned on because a gate is connected to the ground terminal.

The first PMOS transistor PA and the third transistor PC have the same turn-on resistance, and the second PMOS transistor PB is larger than the first PMOS transistor PA and the third transistor PC. It may have a turn on resistance.

The output driver 118 is formed in series connection with a resistor R101 and one PMOS transistor P101.

The comparator 112 is connected to the first node. The comparator 112 outputs a comparison value by comparing the voltage level of the first node with a reference level VREF. The comparison value is stored in register 114. The reference level VREF may have a level 1/2 times the power supply voltage.

An RZQ resistor, which is an external resistor, is connected to the RZQ pad.

When the test operation mode is not entered, that is, when the test mode disable signal test = '0' and its inversion signal / test = '1' are applied, the first PMOS transistor PA and the third PMOS transistor are applied. (PC) turns on and self-calibration proceeds normally.

When the test mode is entered, that is, when the test mode enable signal test = '1' and its inversion signal / test = '0' are applied, the second PMOS transistor PB and the third PMOS transistor PC ) Is turned on. In this case, the resistance value viewed by the output driver 118 becomes larger than when the test mode does not enter the test mode. If such changes are confirmed by a method such as BIST (Built In Self Test), it is possible to verify whether the semiconductor memory device is self-calibrating.

As described above, when the test operation mode is entered and the test operation mode is not entered, the self-calibration operation can be verified by differently configuring the resistance values.

The description of the above embodiments is merely given by way of example with reference to the drawings for a more thorough understanding of the present invention, and should not be construed as limiting the present invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention.

As described above, according to the present invention, as the calibration operation is tested by differently applying the resistance value when entering the test mode and the resistance value when not entering the test mode, the calibration scheme in the semiconductor memory device operates normally. It has the effect of knowing whether or not to perform.

Claims (3)

In the self calibration operation test method: A self-calibration operation test method, characterized in that the pull-up resistance of an output driver in a semiconductor memory device is different from the case of entering the test mode and the case of not entering the test mode. The method of claim 1, Self-calibration operation test method characterized in that the pull-up resistance of the output driver is larger in the case of entering the test mode than when entering the test mode when entering the test mode. Self-calibration with a first transistor turned on when entering the test mode and a second transistor turned off when entering the test mode and turned on in a mode other than the test mode and having a smaller resistance value than the first transistor A test circuit, characterized by performing an operation test.

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