KR20080066142A - Refresh pulse generating circuit and semiconductor memory apparatus using the same - Google Patents

Abstract

A refresh pulse generation circuit and a semiconductor memory device using the same are provided to generate a refresh pulse corresponding frequency per bank with a different refresh cycle. A refresh pulse generation unit(100) generates a plurality of refresh pulses with different frequency. A refresh pulse selection unit(200) outputs one of the several refresh pulses selectively in response to a refresh pulse selection signal. The refresh pulse selection unit includes a refresh pulse selection signal generation part generating the refresh pulse selection signal, a decoding part generating a decoding signal by decoding the refresh pulse selection signal, and a refresh selection part selecting one of the plurality of refresh pulses by inputting the decoding signal and the plurality of refresh pulses.

Description

Refresh pulse generating circuit and semiconductor memory device using same {Refresh Pulse Generating Circuit and Semiconductor Memory Apparatus Using The Same}

1 is a block diagram of a semiconductor memory device to which a conventional refresh pulse generation circuit is applied;

2 is a block diagram of a semiconductor memory device to which a refresh pulse generation circuit according to the present invention is applied;

3 is a block diagram of the refresh pulse selecting means of FIG. 2;

4 is a block diagram of a refresh pulse select signal generation unit of FIG. 3;

5 is a circuit diagram of a first fuse unit of FIG. 4;

6 is a block diagram of a decoding unit of FIG. 3;

7 is a block diagram of the refresh pulse selector of FIG. 3;

FIG. 8 is a circuit diagram of the first selector of FIG. 7.

<Description of the symbols for the main parts of the drawings>

100: refresh pulse generating means 200: refresh pulse selecting means

The present invention relates to a semiconductor memory device, and more particularly, to a refresh pulse generation circuit and a semiconductor memory device using the same.

The semiconductor cell is composed of one capacitor and one transistor. When the capacitor constituting the semiconductor cell stores the high data, the capacitor cannot maintain the high level as the data is stored due to the leakage current. The maximum time a capacitor can hold high data is called the retention time. This retention time is different for each memory cell, which is determined by process errors and other factors. Banks, which are collections of memory cells, also have retention times.

1 is a block diagram of a semiconductor memory device to which a conventional refresh pulse generation circuit is applied. The number of banks is assumed to be four (first to fourth banks 20, 30, 40, and 50), but the description is not limited thereto.

The refresh pulse generation means 10 generates a refresh pulse ref_p having a constant period.

All of the first to fourth banks 20, 30, 40, and 50 receive the refresh pulse ref_p in common.

In the related art, a refresh period is determined based on a bank having the shortest retention time of a bank in one semiconductor memory device. This determines the refresh cycle with a minimum amount of time to ensure that all data stored in the semiconductor cell is not destroyed.

Because of the good retention time, there is a limit that the short retention time can be applied even to a bank where refreshing is long. In addition, a short refresh cycle of a bank having a good refresh retention time frequently performs a refresh operation. Therefore, it is a cause of increasing power consumption during the refresh operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and provides a refresh pulse generation circuit capable of generating a refresh pulse having a frequency corresponding to each bank having a different refresh period and outputting the refresh pulse for each bank, and a semiconductor memory device using the same. The purpose is.

A refresh pulse generation circuit of a semiconductor memory device according to the present invention includes refresh pulse generation means for generating a plurality of refresh pulses having different frequencies, and refresh for selectively outputting one of the refresh pulses in response to a refresh pulse selection signal. Pulse selection means.

In addition, the semiconductor memory device according to the present invention includes a refresh pulse generating means for generating a plurality of banks, a plurality of refresh pulses having different frequencies, and a refresh pulse of the plurality of refresh pulses for each bank in response to a refresh pulse selection signal. Refresh pulse selection means for selectively outputting.

Hereinafter, a preferred embodiment of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings. In this case, it is assumed that the number of banks is four and the number of refresh pulses having different frequencies is four, but the present invention is not limited thereto.

2 is a block diagram of a semiconductor memory device to which a refresh pulse generation circuit according to the present invention is applied.

The refresh pulse generating means 100 generates the first to fourth refresh pulses ref_p <0: 3> having different frequencies. In this case, the refresh pulse generating means 100 includes four oscillators for generating the first to fourth refresh pulses ref_p <0: 3>, respectively.

The refresh pulse selecting means 200 receives a power-up signal pwrup as an input to refresh one of the first to fourth refresh pulses ref_p <0: 3> for each bank 20, 30, 40, and 50. Pulses ref_p <i>, ref_p <j>, ref_p <k>, ref_p <m>, i, j, k, m = 0 to 3 are output.

3 is a block diagram of the refresh pulse selecting means of FIG.

The refresh pulse selecting means 200 receives the power-up signal pwrup as an input and according to the connection state of the fuse, the first to fourth refresh pulse selecting signals sel-1 <0: 1> and sel-2 <0: 1. >, sel-3 <0: 1>, sel-4 <0: 1>, and a refresh pulse selection signal generator 210 for generating the first to fourth refresh pulse selection signals sel-1 <0: 1>, sel-2 <0: 1>, sel-3 <0: 1>, sel-4 <0: 1> to decode the first to fourth decoding signals dec-1 <0: 3>, a decoding unit 220 for generating dec-2 <0: 3>, dec-3 <0: 3>, and dec-4 <0: 3>, and the first to fourth decoding signals dec-1 <0. : 3>, dec-2 <0: 3>, dec-3 <0: 3>, and dec-4 <0: 3>, respectively, to the first to fourth refresh pulses ref_p <0: 3>. ) Includes a refresh pulse selector 230 for outputting one refresh pulse ref_p <i>, ref_p <j>, ref_p <k>, ref_p <m> for each bank. In this case, the first to fourth refresh pulse selection signals sel-1 <0: 1>, sel-2 <0: 1>, sel-3 <0: 1>, sel-4 <0: 1> The first to fourth decoding signals dec-1 <0: 3>, dec-2 <0: 3>, dec-3 <0: 3>, and dec-4 <0: 3> are each first To signals corresponding to the fourth banks 20, 30, 40, and 50. For example, the first refresh pulse selection signal sel-1 <0: 1> and the first decoding signal dec-1 <0: 3> are signals related to the first bank 20.

4 is a block diagram of the refresh pulse select signal generator of FIG. 3.

The refresh pulse select signal generator 210 may include a first fuse 211 and a second refresh pulse select signal sel-2 <0: generating a first refresh pulse select signal sel-1 <0: 1>. 1>), the second fuse unit 212 generating the third refresh pulse selection signal (sel-3 <0: 1>), and the fourth fuse unit 213 generating the fourth refresh pulse selecting signal (sel). A fourth fuse portion 214 generating -4 <0: 1>. At this time, each fuse unit 211, 212, 213, and 214 commonly receives a power-up signal pwrup.

FIG. 5 is a circuit diagram of the first fuse unit of FIG. 4.

The first to fourth fuse parts 211, 212, 213, and 214 have the same configuration, and only the first fuse part 211 is shown and described.

The first fuse unit 211 initializes the first refresh pulse selection signal sel-1 <0: 1> in response to a power-up signal pwrup, and the first and second fuses fuse1 and fuse2. The activation state of the first refresh pulse selection signal sel-1 <0: 1> is determined according to the connected state of the signal.

The first fuse unit 211 initializes the first refresh pulse select signal sel-1 <0: 1> in response to the power-up signal pwrup, and the first and second fuses fuse1 and fuse2. Inverts the output signal of the signal generator 211-1 and the signal generator 211-1 for generating the first refresh pulse selection signal sel-1 <0: 1> according to a connection state of And a latch unit 211-2 for outputting the first refresh pulse selection signal sel-1 <0: 1> and maintaining the level thereof.

The signal generator 211-1 receives the power-up signal pwrup at a gate terminal and an external voltage VDD is applied to a source terminal, and at one end of the first transistor P1. The first fuse (fuse1) connected to the drain terminal of the input, the power-up signal (pwrup) is input to the gate terminal, the ground terminal (VSS) is connected to the source terminal, the other end of the first fuse (fuse1) is connected to the drain terminal The second transistor N1 connected to the third transistor P2 receiving the power-up signal pwrup at a gate terminal and applying an external voltage VDD to a source terminal, and a drain of the third transistor P2 at one end thereof. The second fuse (fuse2) connected to the stage and the power-up signal (pwrup) is input to the gate terminal, the ground terminal (VSS) is connected to the source terminal and the other end of the second fuse (fuse2) is connected to the drain terminal A fourth transistor N2 is included.

The latch unit 211-2 is a first inverter IV1 connected to a node to which the first fuse fuse1 and the second transistor N1 are connected to an input terminal, and an output terminal of the first inverter IV1 to an input terminal. Is connected and an output terminal of the first inverter IV1 is connected to the second inverter IV2, and an input terminal of the third inverter IV3 is connected to the node connected to the second fuse fuse2 and the fourth transistor N2. ), And a fourth inverter IV4 connected to an output terminal of the third inverter IV3 at an input terminal and connected to an input terminal of the third inverter IV3 at an output terminal. In this case, the first refresh selection signal sel-1 <0: 1> is output from the output terminals of the first inverter IV1 and the third inverter IV3.

6 is a block diagram of a decoding unit of FIG. 3.

The decoder 220 decodes the first refresh pulse select signal sel-1 <0: 1> to generate a first decoded signal dec-1 <0: 3>. A second decoder 222 which decodes the 2 refresh pulse select signal sel-2 <0: 1> to generate a second decode signal dec-2 <0: 3>, and a third refresh pulse select signal sel A third decoder 223 which decodes -3 <0: 1> to generate a third decoded signal dec-3 <0: 3>, and a fourth refresh pulse select signal sel-4 <0: 1 A fourth decoder 224 that decodes &quot;) to produce a fourth decoded signal dec-4 <

FIG. 7 is a block diagram of the refresh pulse selector of FIG. 3.

The refresh pulse selector 230 includes first to fourth selectors 231, 232, 233, and 234 having first to fourth refresh pulses ref_p <0: 3 as common inputs.

The first selector 231 responds to one of the first to fourth refresh pulses ref_p <0: 3> in response to the first decoding signal dec-1 <0: 3>. Select i>) to print.

The second selector 232 may generate one refresh pulse ref_p <of the first to fourth refresh pulses ref_p <0: 3> in response to the second decoding signal dec-2 <0: 3>. j>) to print it.

The third selector 233 may respond to one of the first to fourth refresh pulses ref_p <0: 3> in response to the third decoding signal dec-3 <0: 3>. k>) to print it.

The fourth selector 234 may apply one of the first to fourth refresh pulses ref_p <0: 3> in response to the fourth decoding signal dec-4 <0: 3>. m>) to print.

FIG. 8 is a circuit diagram of the first selector of FIG. 7.

The first to fourth selectors 231, 232, 233, and 234 have the same configuration, and thus only the first selector 231 is illustrated and described.

The first selector 231 outputs a first refresh pulse ref_p <0> in response to the first decoded signal 0 (dec-1 <0>), and a first switch 231-1. A second switching unit 231-2 which outputs a second refresh pulse ref_p <1> in response to the decoding signal 1 dec-1 <1>, and the first decoding signal 2 dec-1 <2> In response to the third switching unit 231-3 outputting the third refresh pulse ref_p <2>, and in response to the first decoding signal 3 dec-1 <3>, the fourth refresh pulse ref_p < 3>), and includes a fourth switching unit 213-4.

The first switching unit 231-1 may include a fifth inverter IV11 for inverting the first decoding signal 0 <dec-1 <0> and a first decoding signal 0 (dec−) at a first control terminal. And a first pass gate PG1 that receives 1 <0> and receives the output signal of the fifth inverter IV11 to the second control terminal. In addition, the first switching unit 231-1 receives the first refresh pulse ref_p <0> from an input terminal.

The second switching unit 231-2 may switch the sixth inverter IV12 to invert the first decoding signal 1 <dec-1 <1>, and the first decoding signal 1 (dec −) to a first control terminal. And a second pass gate PG2 receiving the output signal of the sixth inverter IV12 to the second control terminal. In addition, the second switching unit 231-2 receives the second refresh pulse ref_p <1> from an input terminal.

The third switching unit 231-3 is a seventh inverter IV13 for inverting the first decoding signal 2 <dec-1 <2>, and the first decoding signal 2 (dec-) at a first control terminal. And a third pass gate PG3 that receives 1 <2> and receives the output signal of the seventh inverter IV13 to the second control terminal. In addition, the third switching unit 231-3 receives the third refresh pulse ref_p <2> from an input terminal.

The fourth switching unit 231-4 is an eighth inverter IV14 for inverting the first decoding signal 3 <dec-1 <3>, and the first decoding signal 3 (dec-) at a first control terminal. And a fourth pass gate PG4 configured to receive 1 <3> and receive the output signal of the eighth inverter IV14 to the second control terminal. In addition, the fourth switching unit 231-4 receives the fourth refresh pulse ref_p <4> at an input terminal.

In this case, output terminals of the first to fourth switching units 231-1, 231-2, 231-3, and 231-4 are commonly connected and are connected to the first bank 20.

The semiconductor device according to the present invention configured as described above operates as follows.

Through the test, the refresh periods of the first to fourth banks 20, 30, 40, and 50 are measured. In this case, it is assumed that the refresh period required by the first bank 20 is 32ms, the second bank 30 is 64ms, the third bank 40 is 128ms, and the fourth bank 50 is 256ms. .

According to the test result, the refresh pulse generating means 100 includes four oscillators having frequencies required for each of the first to fourth banks 20, 30, 40, and 50. In addition, the first to fourth refresh pulse selection signals sel-1 <0: 1> and sel-2 <0: may be cut by not cutting or cutting the fuses of the first to fourth fuses 211, 212, 213, and 214. 1>, sel-3 <0: 1>, sel-4 <0: 1>). In this case, the first to fourth fuses 211, 212, 213, and 214 have the first to fourth refresh pulse selection signals sel-1 <0: 1> and sel-2 <according to the connection state of the fuses. 0: 1>, sel-3 <0: 1>, sel-4 <0: 1>), and the operation of determining the logic level is the same, only the operation of the first fuse 211 will be described.

For example, when the logic level of the first refresh select signal 0 (sel-1 <0>) is low and the logic level of the first refresh select signal 1 (sel-1 <1>) is high, the first fuse is fuse1. ) Is cut and the second fuse is not cut. When the potential level of the power-up signal pwrup increases, the first fuse unit 211 initializes the first refresh selection signal sel-1 <0: 1> to low. When the power-up signal pwrup goes low, the first fuse fuse1 is cut, so the first refresh selection signal 0 (sel-1 <0>) has a low value and the second fuse fuse2. Since the first refresh selection signal 1 (sel-1 <1>) transitions to high as the external voltage VDD flows in due to no cutting.

The logic level of the first refresh pulse select signal sel-1 <0: 1> generated by cutting or not cutting the fuses of the first to fourth fuse units 211, 212, 213, and 214 is ( 0,0), the logic level of the second refresh pulse select signal sel-2 <0: 1> is (0,1), and the logic level of the third refresh pulse select signal sel-3 <0: 1> Assume that the logic level is (1,0) and the logic level of the third refresh pulse select signal sel-4 <0: 1> is (1,1).

The first decoder 221 which decodes the first refresh pulse selection signal sel-1 <0: 1> may have a first decoding signal 0 (dec−) among the first decoding signals dec-1 <0: 3>. Only 1 <0>) is enabled.

The second decoder 222, which decodes the second refresh pulse selection signal sel-2 <0: 1>, may decode the second decoding signal 1 (dec−) from the second decoding signal dec-2 <0: 3>. Only 2 <1>) is enabled.

The third decoder 223 which decodes the third refresh pulse select signal sel-3 <0: 1> is a third decoded signal 2 (dec−) of the third decoded signal dec-3 <0: 3>. Only 3 <2>) is enabled.

The fourth decoder 224, which decodes the fourth refresh pulse select signal sel-4 <0: 1>, may use a fourth decoded signal 3 (dec −) of the fourth decoded signal dec-4 <0: 3>. Only 4 <3>) is enabled.

Outputting only one refresh pulse ref_p <i> of the first to fourth refresh pulses ref_p <0: 3> in response to the first decoding signal sel-1 <0: 3>. The first selector 231 enables only the first decoding signal 0 (sel-1 <0>) to output the first refresh pulse ref_p <1> to the first bank 20.

A second selection outputting only one refresh pulse ref_p <j of the first to fourth refresh pulses ref_p <0: 3> in response to the second decoding signal sel-1 <0: 3> The unit 232 enables only the second decoding signal 1 (sel-2 <1>) to output the second refresh pulse ref_p <2> to the second bank 30.

A third outputting only one refresh pulse ref_p <k> of the first to fourth refresh pulses ref_p <0: 3> in response to the third decoding signal sel-3 <0: 3> The selector 233 enables only the third decoding signal 2 (sel-3 <2>) to output the third refresh pulse ref_p <3> to the third bank 40.

A fourth outputting only one refresh pulse ref_p <m> of the first to fourth refresh pulses ref_p <0: 3> in response to the fourth decoding signal sel-4 <0: 3> The selector 234 enables only the fourth decoding signal 3 (sel-4 <3>) to output the fourth refresh pulse ref_p <4> to the fourth bank 50.

Therefore, each bank 20, 30, 40, 50 may have a different refresh period and perform the refresh operation.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The refresh pulse generation circuit and the semiconductor memory device using the same according to the present invention have the effect of reducing the power consumption due to the refresh operation by performing the refresh operation according to the refresh cycle characteristics of each bank.

Claims (15)

Refresh pulse generation means for generating a plurality of refresh pulses having different frequencies; And And refresh pulse selecting means for selectively outputting one of the plurality of refresh pulses in response to a refresh pulse selection signal. The method of claim 1, The refresh pulse selecting means A refresh pulse selection signal generator configured to generate the refresh pulse selection signal; A decoding unit to decode the refresh pulse selection signal to generate a decoded signal; And a refresh selector for selecting one of the plurality of refresh pulses and outputting the decoded signal and the plurality of refresh pulses as inputs. The method of claim 1, The refresh pulse select signal generator The refresh pulse generation circuit of the semiconductor memory device, characterized in that the activation of the refresh pulse selection signal is determined according to the connection state of the fuse. The method of claim 3, wherein The refresh pulse select signal generator A refresh pulse generation circuit of a semiconductor memory device, characterized in that the refresh pulse selection signal is initialized with a power-up signal as an input. The method of claim 4, wherein The refresh pulse select signal generator A signal generator for generating the refresh pulse selection signal in response to a connection state of the power up signal and the fuse; And a latch unit for inverting an output signal of the signal generator and outputting the signal as the refresh pulse select signal. The method of claim 5, wherein The signal generator A first transistor receiving the power-up signal at a gate terminal and receiving an external voltage at a source terminal, A fuse connected to one end of the drain terminal of the first transistor, and And a second transistor configured to receive the power-up signal at a gate end thereof, to a drain end thereof to the other end of the fuse, and to a source end thereof to a ground end thereof. The method of claim 2, The refresh pulse selector And a plurality of switching elements for outputting respective refresh pulses in response to the decoded signal. A plurality of banks; Refresh pulse generation means for generating a plurality of refresh pulses having different frequencies; And And refresh pulse selecting means for outputting one refresh pulse of each of the plurality of refresh pulses for each bank in response to a refresh pulse selection signal of a corresponding bank. The method according to claim 1 or 8, The refresh pulse generation means A plurality of oscillators for generating one refresh pulse, characterized in that the semiconductor memory device. The method of claim 8, The refresh pulse selecting means A refresh pulse selection signal generation unit generating a plurality of said refresh pulse selection signals, and A decoder configured to decode the plurality of refresh pulse selection signals to generate a plurality of decoded signals; And a refresh pulse selector configured to selectively output one refresh pulse of the plurality of refresh pulses for each bank by inputting the plurality of decoded signals and the plurality of refresh pulses. The method of claim 10, The refresh pulse select signal generator And a plurality of fuses configured to generate respective refresh pulse selection signals for outputting one refresh pulse among the plurality of refresh pulses to a corresponding bank among the plurality of banks. The method of claim 11, The fuse unit And a power up signal as an input to initialize the refresh pulse selection signal and determine whether to activate the refresh pulse selection signal according to a connection state of a fuse. The method of claim 10, The decoding unit And a plurality of decoders for decoding each refresh pulse select signal to generate a decoded signal of a corresponding bank. The method of claim 10, The refresh pulse selector And a plurality of selectors configured to output one refresh pulse of each of the plurality of refresh pulses for each bank in response to a decoded signal of the corresponding bank. The method of claim 14, The selection unit And a plurality of switching elements for outputting a corresponding refresh pulse in response to each decoding signal.

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