KR20080065805A - Method for fabricating semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to avoid generation of a bridge between a recess gate structure and its adjacent active region by designing a recess gate region of an island type. An STI(shallow trench isolation) process is performed on a semiconductor substrate to form an isolation structure for defining an active region(301). The active region is selectively etched to form a three-dimensional recess channel structure by using a recess gate mask of an island type in which the line width of the lengthwise direction of a gate region(305) is greater than the line width of the minor axis of the active region by 2E. A gate insulation layer is formed on the active region including the three-dimensional recess channel structure. A gate electrode is formed on the gate insulation layer to bury the three-dimensional recess channel structure. The process for forming the three-dimensional recess channel structure can include the following steps. A hard mask layer is formed on the semiconductor substrate. The hard mask layer and a predetermined thickness of the substrate are selectively etched to form a first recess by using the recess gate mask of the island type. The substrate exposed to the lower part of the first recess is selectively etched to form a second recess. The hard mask layer is removed to form the three-dimensional recess channel structure defined by the first and second recesses.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

1 is a layout of a semiconductor device according to the prior art.

2 is a cross-sectional view of a semiconductor device according to the prior art.

3 is a layout of a semiconductor device in accordance with an embodiment of the present invention.

4A through 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101: active region 103: recess gate region

105: gate region 120: device isolation region

210: semiconductor substrate 220: device isolation structure

301 active region 303 recess gate region

305: gate region 320: device isolation region

410: semiconductor substrate 412: pad oxide film

414: pad nitride film 422: first oxide film

424 first nitride film 426 hard mask layer

429: photoresist pattern 430: first recess

432: spacer 434: second recess

440: recess gate structure 460: gate insulating film

465: gate conductive layer 470: lower gate conductive layer

475: lower gate electrode 480: upper gate conductive layer

485: upper gate electrode 490: gate hard mask layer

493: gate electrode 495: gate hard mask layer pattern

497: gate structure

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an island type recess gate mask.

In order to improve the performance of the semiconductor device and to reduce the manufacturing cost, the degree of integration of the semiconductor device is continuously increasing, and a technology for stably reducing the size of the semiconductor device is required. In the meantime, in the manufacturing technology of semiconductor devices, the channel length of the metal oxide semiconductor field effect transistor (MOSFET) has been reduced by reducing the design rules of the devices in order to improve the speed and the degree of integration of the semiconductor devices.

In accordance with the trend of miniaturization and high integration of semiconductor devices, the design rules of semiconductor devices have been reduced, and channel lengths of MOS transistors have become shorter and shorter. Reducing the channel length narrows the gap between the source and drain regions, making it easy to efficiently control the voltage of the drain region affecting the source and channel regions due to the short channel effect (SCE). As a result, the characteristics of the active switch device deteriorated. In addition, it is difficult to exclude the influence of the source / drain punch-through phenomenon because the interval between the source / drain regions is narrow.

In order to solve this problem, a recess field effect transistor (FET) structure has been proposed, which increases the effective channel length by recessing a semiconductor substrate and forming a gate electrode filling the gap. This structure can improve the source / drain punchthrough phenomenon and substantially increase the distance between the source / drain regions. Therefore, the channel length reduction due to the reduction of the design rule can be increased three-dimensionally, which ultimately helps the high integration of the device.

1 is a plan view showing the layout of a semiconductor device according to the prior art. A gate structure 105, which is a word line intersecting the device isolation structure 120, the active region 101, and the active region 101, is formed on the semiconductor substrate. The recess gate region 103 is provided under the gate structure 105 in a line shape, and is smaller than the width of the gate structure 105 by D, respectively. In other words, the misalignment margin of the recess gate region 103 is D. FIG.

2 shows a cross-sectional view of a semiconductor device according to the prior art. The recess gate region 103 of FIG. 1 is provided in a line shape to recess the active region and a part of the device isolation structure. As shown in FIG. 1, when the recess gate region 103 is misaligned by more than an alignment margin, the gate structure on the device isolation structure 220 may be bridged with an adjacent active region. As a result, it has become a cause of greatly reducing the reliability of the semiconductor device. In addition, it is difficult to secure sufficient refresh characteristics of the device through the recess FET process, so that an additional process is introduced to increase the curvature radius of the lower part of the recess to improve the refresh characteristic, thereby causing a misalignment problem between the recess FET and the active region. It had a big impact on margins. As a result, the yield and reliability of the device have been reduced.

The present invention is to solve the above problems, in particular, to form a device isolation structure that defines the active region by performing an STI process on the semiconductor substrate, and selectively etching the active region with an island-type recess gate mask three-dimensional By forming a recess channel structure, forming a gate insulating film over the active region including the three-dimensional recess channel structure, and forming a gate electrode over the gate insulating film to design the semiconductor device to fill the three-dimensional recess channel structure, The present invention provides a method of manufacturing a semiconductor device capable of securing a sufficient alignment margin between the dimensional recess gate and the active region to improve the refresh characteristics of the device and improve the yield of the device.

The present invention is to achieve the above object, the manufacturing method of a semiconductor device according to the present invention,

Forming a device isolation structure defining an active region by performing an STI process on the semiconductor substrate, and acting as an island-type recess gate mask having a line width in the longitudinal direction of the gate region that is 2E larger than the shortened line width of the active region; Selectively etching the region to form a three-dimensional recess channel structure, forming a gate insulating layer on the active region including the three-dimensional recess channel structure, and forming a gate electrode on the gate insulating layer to form the three-dimensional recess channel structure And embedding the channel structure (where 0 ≦ E ≦ (1/2) F, where F is the width between adjacent gates).

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

3 is a plan view showing the layout of a semiconductor device according to the present invention. A gate structure 305 is formed on the semiconductor substrate upper device isolation structure 320, the active region 301, and a word line intersecting the active region 301. The gap between the gate structures 305 is F, and the recess gate region 303 is provided in the lower portion of the gate structure 305 as a rectangular island type rather than a line type. 305 smaller than the width of the left and right by D, respectively, and larger than the line width of the active region 301 by E, respectively. Here, O ≦ D ≦ (1/3) F, 0 ≦ E ≦ (1/2) F, and F are preferably the minimum line widths between adjacent gates according to design rules.

4A to 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. FIGS. 4A to 4G are cross-sectional views taken along line II ′ of FIG. 3. ii) to 4g (ii) are cross-sectional views along II-II 'of FIG. 3. After forming the pad oxide film 412 and the pad nitride film 414 on the semiconductor substrate 410, a photosensitive film (not shown) is formed on the pad nitride film 414. Next, a photoresist film is exposed and developed with an element isolation mask (not shown) to form a photoresist pattern (not shown) defining an element isolation region. Subsequently, the pad nitride layer 414, the pad oxide layer 412, and the semiconductor substrate 410 are etched by a predetermined thickness using the photoresist pattern as an etch mask to form a trench (not shown) defining the active region 301 of FIG. 3. After that, the photosensitive film pattern is removed. Subsequently, after forming the device isolation oxide film filling the trench, the device isolation structure 420 is formed by planarizing etching of the device isolation oxide film until the pad nitride film 414 is exposed. Here, it is preferable to form a stacked structure of a thermal oxide film (not shown), a liner nitride film (not shown), and a liner oxide film (not shown) at the interface between the oxide film for isolation and the trench.

Referring to FIG. 4B, after the device isolation structure 420 is etched by a predetermined thickness by a wet etching method to decrease its height, the remaining pad nitride film 414 and the pad oxide film 412 are removed to expose the semiconductor substrate 410. . Next, after forming the first oxide film 422 on the exposed semiconductor substrate 410, a photosensitive film (not shown) is applied to the entire surface. Subsequently, the photoresist layer is exposed and developed with a mask that exposes the cell region, thereby forming a photoresist pattern (not shown), and then implanting ions with the mask to inject the well and channel ion implantation regions into the semiconductor substrate 410 under the first oxide layer. (Not shown) is formed. Then, the photoresist pattern is removed. Thereafter, the planarized first nitride film 424 and the first hard mask layer 426 are formed on the entire surface. Here, the first hard mask layer 426 is preferably formed of any one selected from a polysilicon layer, an amorphous carbon film, a CVD oxide film, a SiON film, and a combination thereof.

Referring to FIG. 4C, after the photoresist layer (not shown) is formed on the first hard mask layer 426, the photoresist layer is exposed and developed with an exposure mask defining the recess gate region 303 of FIG. 3. 429, the line width of the recess gate mask is longer than the width of the active region 301 of FIG. 3 in the longitudinal direction of the gate region 305 of FIG. 3, and the length of the active region 301 of FIG. 3. In the direction, the line width of the recess gate mask is smaller than that of the gate region 305 of FIG. 3. Next, the first hard mask layer 426, the first nitride film 424, and the first oxide film 422 are exposed by etching the photoresist pattern 429 as an etch mask, thereby forming the recess gate region 303 of FIG. 3. The semiconductor substrate 310 is exposed. Meanwhile, in another embodiment of the present invention, the recess gate mask may be formed of a closed polygon such as an ellipse.

4D and 4E, the exposed semiconductor substrate 410 is etched by a predetermined thickness and the exposed device isolation structure 420 is etched to form a first recess 430 defining a recessed channel region. Next, after removing the remaining photoresist pattern 429 and the first hard mask layer 426, the semiconductor substrate 410, the first oxide film 422, and the first nitride film 424 exposed in the first recess 430 are removed. After the insulating film (not shown) is formed on the sidewalls of the substrate), the insulating film is dry-etched to form the spacers 432 on the sidewalls of the first recesses 430. Thereafter, the semiconductor substrate 410 exposed to the lower portion of the first recess 430 by etching the spacer 432 is etched to a predetermined thickness to form a second recess 434. Here, the etching process for forming the second recess 434 is preferably an isotropic etching method. Further, the lower portion of the second recess 434 is preferably elliptical or circular in the longitudinal direction of the active region 401 of FIG. 3.

Referring to FIG. 4F, the spacer 432 is removed to form a three-dimensional recess gate structure 440 defined by the first recess 430 and the second recess 434. Next, after the gate insulating layer 460 is formed on the exposed semiconductor substrate 410, a gate conductive layer 465 filling the recess gate structure 440 is formed. Next, a gate hard mask layer 490 is formed on the gate conductive layer 465. According to an embodiment of the present invention, the gate conductive layer 465 preferably has a stacked structure of the lower gate conductive layer 470 and the upper gate conductive layer 480.

Referring to FIG. 4G, after the photoresist film (not shown) is applied on the gate hard mask layer 490, the photoresist film is exposed and developed with a gate mask (not shown) to define the gate region 305 of FIG. 3. A pattern (not shown) is formed. Next, the gate hard mask layer 490, the upper gate conductive layer 480, and the lower gate conductive layer 470 are patterned using the photoresist pattern as an etch mask to form the gate hard mask layer pattern 495 and the gate electrode 493. A gate structure 497 formed of a laminated structure is formed. According to an embodiment of the present invention, the gate electrode 493 has a stacked structure of the lower gate electrode 475 and the upper gate electrode 485. In addition, the lower gate conductive layer 470 may be formed of a polysilicon layer, a SiGe layer, or a stacked structure thereof, and the upper gate conductive layer 480 may be a titanium nitride film, a tungsten nitride film, a tungsten polyside layer, or a titanium polyside. It is preferable to form one selected from a layer, a titanium layer, a tungsten layer or a combination thereof.

As described above, in the method of manufacturing the semiconductor device according to the present invention, the recess gate region is designed to have an island type when the recess gate structure is formed, such that the recess gate structure is misaligned and adjacent to the recess gate structure. There is an advantage that can improve the reliability and characteristics of the device because the bridge of the active area does not occur. In addition, since the bridge of the recess gate structure and the adjacent active region is prevented from affecting the adjacent gate, the influence on the threshold voltage may be minimized.

In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

Performing an STI process on the semiconductor substrate to form an isolation structure defining an active region; Forming a three-dimensional recess channel structure by selectively etching the active region with an island-type recess gate mask having a line width in a length direction of the gate region that is 2E larger than a shortened line width of the active region; Forming a gate insulating layer on the active region including the three-dimensional recess channel structure; And Forming a gate electrode on the gate insulating layer to fill the three-dimensional recess channel structure (where 0 ≦ E ≦ (1/2) F and F are adjacent to each other). Width between gates). The method of claim 1, Forming the three-dimensional recess channel structure Forming a hard mask layer on the semiconductor substrate; Forming a first recess by first etching the hard mask layer and the semiconductor substrate having a predetermined thickness with the island type recess gate mask; Forming a second recess by second selectively etching the semiconductor substrate exposed under the first recess; And Removing the hard mask layer to form the three-dimensional recess channel structure defined by the first and second recesses. The method of claim 2, And the hard mask layer is formed of any one selected from an oxide film, a nitride film, a polysilicon layer, an amorphous carbon film, a CVD oxide film, a SiON film, and a combination thereof. The method of claim 2, The first selective etching process is a method of manufacturing a semiconductor device, characterized in that performed by an anisotropic etching method. The method of claim 2, The second selective etching process is a method of manufacturing a semiconductor device, characterized in that performed by an isotropic etching method.

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