KR20080062806A - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

An LCD device and a manufacturing method thereof are provided to dispose a common electrode, which was formed in a pixel area, in the lower part of a data line, thereby improving an aperture ratio by using an organic insulating layer such as photo-acryl. A method for manufacturing an LCD(Liquid Crystal Display) device comprises the followings: forming a first conductive layer on a substrate and continuously forming a second conductive layer; forming a gate electrode(1), a gate line(11), a gate pad(12), a data pad(22), and a common electrode(17) using photolithography including a diffraction mask or a half-tone mask on the substrate; forming a gate insulating layer(2), an amorphous silicon film, and a doped amorphous silicon film successively on the substrate and forming an active layer(5) in the upper part of the gate electrode using the photolithography; forming an organic insulating layer(20) on the substrate and proceeding photolithography to form an organic insulating pattern; and proceeding plasma processing on the substrate to form a channel protection film in the channel area of the active layer.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

1A to 1E are cross-sectional views illustrating a manufacturing process of a liquid crystal display device according to a first embodiment of the present invention.

2A to 2F are cross-sectional views illustrating a manufacturing process of a liquid crystal display device according to a second embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

 10: insulating substrate 1: gate electrode

1a: first gate pattern 1b: second gate pattern

12: gate pad 11a: first gate wiring pattern

11b: second gate wiring pattern 11: gate wiring

22: data pad 17: common electrode

20: organic insulating film

The present invention relates to a liquid crystal display device and a method of manufacturing the same that can realize a high aperture ratio.

In general, as the modern society changes to the information socialization, the importance of the liquid crystal display module, which is one of the information display devices, is gradually increasing. Cathode ray tube (CRT), which is widely used so far, has many advantages in terms of performance and cost, but has many disadvantages in terms of miniaturization or portability.

In order to compensate for the shortcomings of the CRT, a liquid crystal display device capable of realizing light and small, high brightness, large screen, low power consumption, and low cost has been developed.

The liquid crystal display (LCD) not only has superior display resolution than other flat panel displays, but also has a response characteristic that is faster than a CRT when implementing a moving image.

Such a liquid crystal display device forms a electric field between a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate, and twists the liquid crystal interposed between the substrates, thereby displaying an image of twisted nematic (TN) nematic) was used.

However, the liquid crystal display device using the twisted nematic method has a disadvantage that the viewing angle is very narrow.

Recently, in order to solve the narrow viewing angle problem, development of a liquid crystal display device employing various new methods has been actively conducted. In this method, an in-plane switching mode (IPS) or an OCB method (optically compensated) is used. birefrigence mode).

Among these, the transverse electric field type liquid crystal display device forms two electrodes on the same substrate (lower substrate) in order to drive the liquid crystal molecules in a horizontal state with respect to the substrate, and applies a voltage between the two electrodes. The electric field is generated in the horizontal direction with respect to the substrate.

Therefore, in such a transverse electric field system, the long axis of the liquid crystal molecules does not stand in the direction perpendicular to the substrate (twist nematic method). For this reason, the birefringence change of the liquid crystal with respect to the viewing direction is small, and thus the viewing angle characteristic is superior to that of the conventional TN type liquid crystal display device.

However, the conventional transverse electric field type liquid crystal display device has a low aperture ratio because the common electrode made of an opaque metal and the pixel electrode made of a transparent metal are arranged at regular intervals in the pixel area.

In order to overcome such a low aperture ratio, a process of forming a photoacryl has been developed, which additionally forms a photoacryl on a substrate and is patterned according to a mask exposure process.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, in which a common electrode formed in a pixel region is disposed under a data line to improve an aperture ratio.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, by reducing the number of steps by simultaneously patterning the gate electrode and the pixel electrode while improving the aperture ratio by using an organic insulating film such as photoacrylic.

In addition, another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which eliminates defects in wavy noise by reducing the number of steps without a diffraction mask or a halftone mask process.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can remove an organic insulating film in a seal line region without a mask process, thereby preventing defects.

In order to achieve the above object, the liquid crystal display device manufacturing method according to the present invention,

Forming a first conductive film on the substrate, and subsequently forming a second conductive film;

Forming a gate electrode, a gate wiring, a gate pad, a data pad, and a common electrode by using a photolithography method including a diffraction mask or a halftone mask on the substrate on which the first and second conductive films are formed;

Sequentially forming a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film on the substrate on which the gate electrode is formed, and then forming an active layer on the gate electrode using a photolithography method;

Forming an organic insulating layer on the substrate on which the active layer is formed, and then performing a photo process to form an organic insulating layer pattern; And

And forming a channel protective film in a channel region of the active layer by performing a plasma treatment process on the substrate on which the organic insulating film pattern is formed.

According to another embodiment of the present invention, a method of manufacturing a liquid crystal display device is provided.

Forming a first conductive film on the substrate, and subsequently forming a second conductive film;

Forming a gate electrode, a gate wiring, a gate pad, a data pad, and a common electrode by using a photolithography method including a diffraction mask or a halftone mask on the substrate on which the first and second conductive films are formed;

Sequentially forming a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film on the substrate on which the gate electrode is formed, and then forming an active layer on the gate electrode using a photolithography method;

Forming an organic insulating layer on the substrate on which the active layer is formed, and then performing a photo process to form an organic insulating layer pattern; And

Forming a passivation layer on the substrate on which the organic insulating layer pattern is formed, and then performing a contact hole process exposing the gate pad region and the data pad region.

According to another embodiment of the present invention,

Board;

Gate lines and data lines cross-arranged to define pixel regions on the substrate;

A thin film transistor formed at an intersection of the gate line and the data line; And

A common electrode and a pixel electrode alternately formed in the pixel region;

An organic insulating layer is formed between the common electrode formed to overlap the data line.

According to the present invention, the aperture ratio is improved by arranging the common electrode formed in the pixel region under the data wiring.

In addition, the present invention reduces the number of steps by simultaneously patterning the gate electrode and the pixel electrode while improving the aperture ratio by using an organic insulating film such as photoacrylic.

In addition, the present invention eliminates the waste noise (wavy noise) by reducing the number of steps without a diffraction mask or halftone mask process.

In addition, the present invention can remove the organic insulating film in the seal line region without the mask process, it is possible to prevent the seal failure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a manufacturing process of a liquid crystal display device according to a first embodiment of the present invention.

As shown in FIG. 1A, the liquid crystal display array area of the present invention is a thin film transistor TFT, a pixel, a gate pad, a data pad, and a data line area. Each pattern formation process is demonstrated separately.

First, indium-oxide (hereinafter referred to as "ITO"), indium-zinc-oxide (hereinafter referred to as "IZO") and indium- on the transparent insulating substrate 10; A first conductive film of any one of a transparent conductive material such as tin-zinc-oxide (hereinafter referred to as "ITZO") is formed.

Then, a second conductive film made of copper, aluminum (Al) or aluminum alloy (AlNd) is subsequently formed. As described above, when the first conductive film and the second conductive film are sequentially formed on the insulating substrate 10, exposure and etching processes may be performed by a photolithography method including a diffraction mask or a halftone mask, thereby forming a TFT on the TFT region. The gate electrode 1 stacked with the first gate pattern 1a and the second gate pattern 1b is formed.

In this case, in the pixel region, the second conductive layer is removed, and the first conductive layer, which is a transparent conductive material, is patterned to form the pixel electrode 19. In the gate pad region, the gate wiring 11 is formed in a double growth structure of the first gate wiring pattern 11a and the second gate wiring pattern 11b up to the gate wiring. At the edge of the gate line 11, a gate pad 12 having a second conductive layer removed and a first conductive layer patterned is formed.

In the data pad region, the second conductive film is removed and the first conductive film is patterned to form the data pad 22. Thus, the gate pad 12 and the data pad 22 are patterned with a transparent conductive material.

In addition, the second conductive film is removed in the data wiring region adjacent to the pixel region, and the first conductive film is patterned to form the common electrode 17. That is, the common electrode 17 adjacent to the data line among the common electrodes formed in the pixel area is formed in the data line formation area.

As described above, in the present invention, since the common electrode 17 is made of a transparent metal and moved to the data wiring region, the aperture ratio of the pixel region is improved.

That is, in the present invention, the common electrode, the pixel electrode 19, the gate electrode 1, the gate wiring 11, the gate pad 12, and the data pad 22 are simultaneously formed in the pixel region in the first mask process. .

Then, as shown in FIG. 1B, the gate insulating film 2, the amorphous silicon film, and the doped amorphous silicon film are sequentially formed on the insulating substrate 10. Then, the exposure and etching process is performed by a photolithography method to pattern the gate insulating layer 2 and the active layer 5 serving as the ohmic contact layer on the gate electrode 1 in the thin film transistor region. At this time, the gate insulating film 2 formed on the pixel region, the gate pad region, the data pad region, and the data wiring region, the amorphous silicon film, and the doped amorphous silicon film are all removed.

Therefore, the pixel electrode 19 of the pixel region, the gate pad 12 of the gate pad region, the data pad 22 of the data pad region, and the common electrode 17 of the data wiring region are exposed to the outside.

When the active layer 5 is formed on the insulating substrate 10 as described above, as shown in FIG. 1C, the organic insulating film 20 is coated on the insulating substrate 10 and then patterned. The type of organic insulating film 20 used at this time is as follows. Photoacryl organic compounds, Teflon, BCB (benzocyclobutene), cytotopes (cytop) or perfluorocyclobutane (PFCB) are used. In this case, it is preferable to use a material having a dielectric constant smaller than that of the liquid crystal layer.

In addition, in the organic insulating film 20 in the gate pad region, the organic insulating film 20 is formed up to the gate wiring 11 region, and the gate pad 12 has the first pad contact hole 30a from which the organic insulating film 20 is removed. ) Is formed. Therefore, the gate pad 12 is exposed to the outside by the first pad contact hole 30a.

In the data pad region, a second pad contact hole 30b from which a portion of the organic insulating layer 20 is removed is formed, and a portion of the data pad 22 is exposed to the outside.

In the data wiring region, an organic insulating film 20 pattern is formed on the common electrode 17. The organic insulating layer 20 pattern formed on the common electrode 17 is a pattern formed to separate the common electrode 17 from the data line as far as possible in order to minimize parasitic capacitance with the data line to be formed later. In addition, since the dielectric constant of the organic insulating film 20 is small, parasitic capacitance can be reduced as much as possible. That is, the common electrode 17 is formed in the area where the data line is to be formed in the pixel area to increase the aperture ratio, and the organic insulating layer 20 is disposed between the common electrode 17 and the data line to be formed later, thereby forming the data line and the common electrode. Parasitic capacitances that occur between (17) were minimized.

When the organic insulating film 20 is patterned as shown in FIG. 1C, a metal film is formed on the insulating substrate 10 as shown in FIG. 1D, and then exposed and etched by photolithography to obtain a source in the thin film transistor region. Drain electrodes 27a and 27b are formed. At this time, the edge of the drain electrode 27b is patterned in an electrically contacted state with the pixel electrode 19 in the pixel region.

As the data line 13 is formed in the data pad area, a data line pattern 40 for electrical contact with the lower data pad 22 is formed. The data line 13 intersects with the gate line 11, and a thin film transistor is formed in the cross region.

After the source / drain electrodes 27a and 27b and the data wiring 13 are formed as described above, as shown in FIG. 1E, the doped amorphous silicon film of the active layer 5 exposed by the dry etching process is applied. A portion thereof is removed to form an ohmic contact layer under the source / drain electrodes 27a and 27b, and a channel region is formed between the source / drain electrodes 27a and 27b.

Although not shown in the drawings, after the source / drain electrodes 27a and 27b are formed, oxygen (O ₂ ) or nitrogen (N ₂ ) gas may be used to protect the channel region between the source / drain electrodes 27a and 27b. A silicon oxide film or a silicon nitride film can be formed.

As described above, in the present invention, the aperture ratio is improved by overlapping the common electrode 17 in the pixel region with the data line 13. In addition, the organic insulating film 20 is formed on the insulating substrate and patterned to realize a high opening ratio.

In addition, when the active layer 5 and the source / drain electrodes 27a and 27b are formed by separate mask processes, and the active layer and the source / drain electrodes are simultaneously formed using a diffraction mask or a halftone mask, they frequently occur. Eliminating the way noise noise (wavy noise).

In addition, the organic insulating layer in the region where the seal line is to be formed is removed without an additional mask process to prevent the seal burst defect in advance.

The present invention can be applied to all of the TN mode, VA mode, IPS mode and FFS mode which are generally applied in the liquid crystal display.

2A to 2F are cross-sectional views illustrating a manufacturing process of a liquid crystal display device according to a second embodiment of the present invention.

As shown in FIG. 2A, the liquid crystal display array area of the present invention is a thin film transistor TFT, a pixel, a gate pad, a data pad, and a data line area. Each pattern formation process is demonstrated separately.

First, indium-oxide (hereinafter referred to as "ITO"), indium-zinc-oxide (hereinafter referred to as "IZO") and indium- on the transparent insulating substrate 110. A first conductive film of any one of a transparent conductive material such as tin-zinc-oxide (hereinafter referred to as "ITZO") is formed.

Then, a second conductive film made of copper, aluminum (Al) or aluminum alloy (AlNd) is subsequently formed. As described above, when the first conductive layer and the second conductive layer are sequentially formed on the insulating substrate 110, exposure and etching processes are performed by a photolithography method including a diffraction mask or a halftone mask, thereby forming a TFT on the TFT region. The gate electrode 101 stacked with the first gate pattern 101a and the second gate pattern 101b is formed.

In this case, in the pixel region, the second conductive layer is removed, and the first conductive layer, which is a transparent conductive material, is patterned to form the pixel electrode 119. In the gate pad region, the gate wiring 111 is formed in a double increase structure of the first gate wiring pattern 111a and the second gate wiring 111b up to the gate wiring. A gate pad 112 is formed on the edge of the gate wiring 111 to remove the second conductive layer and pattern the first conductive layer.

In the data pad region, the second conductive film is removed, and the first conductive film is patterned to form the data pad 122. Thus, gate pad 112 and data pad 122 are patterned with a transparent conductive material.

In addition, the second conductive film is removed in the data wiring area adjacent to the pixel area, and the first conductive film is patterned to form the common electrode 117. That is, the common electrode 117 adjacent to the data line among the common electrodes formed in the pixel area is formed in the data line formation area.

As described above, in the present invention, since the common electrode 117 is made of a transparent metal and moved to the data wiring region, the aperture ratio of the pixel region is improved.

That is, in the first mask process, the common electrode, the pixel electrode 119, the gate electrode 101, the gate wiring 111, the gate pad 112, and the data pad 122 are simultaneously formed in the pixel region.

Next, as shown in FIG. 2B, a gate insulating film 102, an amorphous silicon film, and a doped amorphous silicon film are sequentially formed on the insulating substrate 110. Then, an exposure and etching process is performed by a photolithography method. In the thin film transistor region, the gate insulating layer 102 and the active layer 105 serving as an ohmic contact layer are patterned on the gate electrode 101. In this case, all of the gate insulating film 102, the amorphous silicon film, and the doped amorphous silicon film formed on the pixel area, the gate pad area, the data pad area, and the data wiring area are removed.

Accordingly, the pixel electrode 119 of the pixel area, the gate pad 112 of the gate pad area, the data pad 122 of the data pad area, and the common electrode 117 of the data wiring area are exposed to the outside.

When the active layer 105 is formed on the insulating substrate 110 as described above, as shown in FIG. 2C, the organic insulating layer 120 is coated on the insulating substrate 110 and then patterned. The type of organic insulating film 120 used at this time is as follows. A photo acryl organic compound, Teflon, BCB (benzocyclobutene), cytotope (cytop) or perfluorocyclobutane (PFCB) is used. In this case, it is preferable to use a material having a dielectric constant smaller than that of the liquid crystal layer.

In addition, the organic insulating layer 120 in the gate pad region is formed with the organic insulating layer 120 up to the gate wiring 111 region, and the gate pad 112 has the first pad contact hole 130a from which the organic insulating layer 120 is removed. ) Is formed. Therefore, the gate pad 112 is exposed to the outside by the first pad contact hole 130a.

In addition, a second pad contact hole 130b from which a portion of the organic insulating layer 120 is removed is formed in the data pad region, and a portion of the data pad 122 is exposed to the outside.

In addition, the organic insulating layer 120 pattern is formed on the common electrode 117 in the data wiring region. The organic insulating layer 120 pattern formed on the common electrode 117 is a pattern formed to be spaced apart from the common electrode 117 as far as possible in order to minimize parasitic capacitance between the data line to be formed later. In addition, since the dielectric constant of the organic insulating layer 120 is small, parasitic capacitance can be reduced as much as possible.

That is, the common electrode 17 is formed in the area where the data line is to be formed in the pixel area to increase the aperture ratio, and the organic insulating layer 20 is disposed between the common electrode 17 and the data line to be formed later, thereby forming the data line and the common electrode. Parasitic capacitances that occur between (17) were minimized.

When the organic insulating film 120 is patterned as shown in FIG. 2C, a metal film is formed on the insulating substrate 110 as shown in FIG. 2D, and then exposed and etched by a photolithography method. Drain electrodes 127a and 127b are formed. At this time, the edge of the drain electrode 127b is patterned in a state of being in electrical contact with the pixel electrode 119 in the pixel region.

As the data line 113 is formed in the data pad region, the data line pattern 140 for electrical contact with the lower data pad 122 is formed.

After forming the source / drain electrodes 127a and 127b and the data wiring 113 as described above, as shown in FIG. 2E, a portion of the exposed active layer 105 is removed by applying a dry etching process to the source. An ohmic contact layer is formed under the / drain electrodes 127a and 127b, and a channel region is formed between the source / drain electrodes 127a and 127b.

Although not shown in the drawings, after the source / drain electrodes 127a and 127b are formed, oxygen (O ₂ ) or nitrogen (N ₂ ) gas may be used to protect the channel region between the source / drain electrodes 27a and 27b. A silicon oxide film or a silicon nitride film can be formed.

If the silicon oxide film or the silicon nitride film is not formed in the channel region, as shown in FIG. 2F, the passivation layer 129 is formed on the entire region of the insulating substrate 110, and then the gate pad 112 region is formed. And a contact hole process for removing the passivation layer 129 on the data line pattern 140 (data pad region).

As described above, in the present invention, the aperture ratio is improved by overlapping the common electrode of the pixel region with the data wiring. In addition, the organic insulating film was formed on the insulating substrate and patterned to realize a high opening ratio.

In addition, the active layer and the source / drain electrodes are formed by separate mask processes to remove the frequently generated noise defects using a diffraction mask or a halftone mask.

In addition, the organic insulating film in the region where the seal line is to be formed is removed without an additional mask process, thereby preventing the seal failure.

The present invention can be applied to all of the TN mode, VA mode, IPS mode and FFS mode which are generally applied in the liquid crystal display.

As described in detail above, according to the present invention, the common electrode formed in the pixel region is disposed under the data line to improve the aperture ratio.

In addition, the present invention has the effect of reducing the number of steps by simultaneously patterning the gate electrode and the pixel electrode while improving the aperture ratio by using an organic insulating film such as photoacrylic.

In addition, the present invention has the effect of eliminating the way noise (wavy noise) by reducing the number of steps without a diffraction mask or halftone mask process.

In addition, the present invention can remove the organic insulating film of the seal line region without the mask process has the effect of preventing the seal failure.

The present invention is not limited to the above-described embodiments, and various changes can be made by those skilled in the art without departing from the gist of the present invention as claimed in the following claims.

Claims (20)

Forming a first conductive film on the substrate, and subsequently forming a second conductive film; Forming a gate electrode, a gate wiring, a gate pad, a data pad, and a common electrode by using a photolithography method including a diffraction mask or a halftone mask on the substrate on which the first and second conductive films are formed; Sequentially forming a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film on the substrate on which the gate electrode is formed, and then forming an active layer on the gate electrode using a photolithography method; Forming an organic insulating layer on the substrate on which the active layer is formed, and then performing a photo process to form an organic insulating layer pattern; And And forming a channel passivation layer in a channel region of the active layer by performing a plasma treatment process on the substrate on which the organic insulating layer pattern is formed. The method of claim 1, wherein the first conductive film is a transparent conductive material. The method of claim 1, wherein the second conductive film is any one of copper, aluminum, or an aluminum alloy. The method of claim 1, wherein the gate electrode has a double layer structure in which a first conductive layer and a second conductive layer are patterned. The method of claim 1, wherein the pixel electrode is formed by patterning a first conductive layer. The method of claim 1, wherein the gate line has a double layer structure in which a first conductive layer and a second conductive layer are patterned. The method of claim 1, wherein the gate pad is formed by patterning a first conductive layer. The method of claim 1, wherein the organic insulating layer pattern has a structure in which contact holes are formed in the gate pad region and the data pad region. The method of claim 1, wherein an organic insulating layer pattern is formed between the common electrode and the data line. The method of claim 1, wherein the channel protective film formed by the plasma treatment is a silicon oxide film or a silicon nitride film. Forming a first conductive film on the substrate, and subsequently forming a second conductive film; Forming a gate electrode, a gate wiring, a gate pad, a data pad, and a common electrode by using a photolithography method including a diffraction mask or a halftone mask on the substrate on which the first and second conductive films are formed; Sequentially forming a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film on the substrate on which the gate electrode is formed, and then forming an active layer on the gate electrode using a photolithography method; Forming an organic insulating layer on the substrate on which the active layer is formed, and then performing a photo process to form an organic insulating layer pattern; And And forming a protective film on the substrate on which the organic insulating layer pattern is formed, and then performing a contact hole process exposing the gate pad region and the data pad region. The method of claim 11, wherein the first conductive film is a transparent conductive material. 12. The method of claim 11, wherein the second conductive film is any one of copper, aluminum, or an aluminum alloy. The method of claim 11, wherein the gate electrode has a double layer structure in which a first conductive layer and a second conductive layer are patterned. The method of claim 11, wherein the pixel electrode is formed by patterning a first conductive layer. The method of claim 11, wherein the gate line has a double layer structure in which a first conductive layer and a second conductive layer are patterned. The method of claim 11, wherein the gate pad is formed by patterning a first conductive layer. The method of claim 11, wherein the organic insulating layer pattern has a structure in which contact holes are formed in the gate pad region and the data pad region. 12. The method of claim 11, wherein an organic insulating layer pattern is formed between the common electrode and the data line. Board; Gate lines and data lines cross-arranged to define pixel regions on the substrate; A thin film transistor formed at an intersection of the gate line and the data line; And A common electrode and a pixel electrode alternately formed in the pixel region; And an organic insulating layer formed between the common electrodes formed to overlap the data line.

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