KR20080062569A - Line on glass type liquid crystal display - Google Patents

Abstract

An LOG(Line On Glass)-type LCD device is provided to divide a signal line corresponding to selected one of a gate control signal and a power signal into a signal line passing through gate TCPs and a signal line directly connected to a corresponding gate driver and form the area of the signal lined directly connected to the gate driver to match the resistance values of the signal lines directly connected to the each gate driver, thereby preventing the deterioration of image quality generated by line delay in proportion to the length of an LOG line. An LCD(Liquid Crystal Display) panel(100) is configured by attaching a color filter substrate(120) and an array substrate(130). A timing controller(162) receives a control signal and a power signal from the outside. A driving PCB(Printed Circuit Board)(160) has the mounted timing controller and is bonded to the upper side end of the array substrate. Plural TCPs(Tape Carrier Packages)(146~148,156~159) are bonded to the side end of the array substrate to drive the LCD panel under the control of the timing controller. Plural signal lines(L1,L2,L3) are connected to the plural TCPs, are formed on the array substrate, and supply the control signal and power signal of plural drivers(141~143,151~154). At least selected one of the signal lines is configured by a first partial line and a second partial line. The first partial line passes through the plural TCPs having the same resistance value. The second partial line is directly connected to the plural drivers.

Description

Line on glass type liquid crystal display

1 is a block diagram illustrating a conventional line-on-glass type liquid crystal display device.

2 is a block diagram illustrating a LOG type liquid crystal display device according to an exemplary embodiment of the present invention.

3 is a view showing in more detail the arrangement of the LOG signal line of the LOG type liquid crystal display according to an embodiment of the present invention.

4 is a schematic diagram illustrating a form in which a gate low signal VGL is input to a gate driver among LOG signal lines according to an exemplary embodiment of the present invention.

<Brief description of the main parts of the drawing>

100: liquid crystal panel 120: color filter substrate

130: array substrate 141 to 143: gate driver

146 to 148: gate TCP 151 to 154: data driver

156 to 159: data TCP 160: driving PCB

162: timing controller L1 to L3: LOG signal line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a line on glass type liquid crystal display device which improves image quality by matching a resistance difference between LOG lines.

A liquid crystal display device is a light receiving display device that forms an electric field in a liquid crystal material having dielectric anisotropy to adjust light transmittance and thereby display an image. Such a liquid crystal display generally includes an array substrate in which a gate line and a data line cross each other and are arranged in a matrix, and a liquid crystal panel in which color filter substrates having three primary colors of R, G, and B are formed at a predetermined distance from each other, and A driving driver for supplying a driving signal to the liquid crystal panel is provided.

In addition, a pixel is defined as a point where the gate line and the data line cross each other in the liquid crystal panel, and the pixel is provided with a thin film transistor that serves as a switching element.

The driver includes a plurality of integrated circuits, and the driver includes a tape carrier package (TCP) method in which the driver is mounted on a thin flexible film made of a polymer material. The mounted TCP is connected to the edge region of the array substrate by a tape automated bonding method.

In addition, a method of connecting the driving driver to the liquid crystal panel is a chip on glass (COG) method, and the chip on glass method is a method of directly mounting the driving driver on the liquid crystal panel.

The driver of the liquid crystal panel of the TCP method and the COG method is a control signal, a drive signal, and a data signal input from an external system through signal lines mounted on a printed circuit board directly connected to TCP. For this purpose, the data TCP is directly bonded to the driving PCB, and the gate TCP is electrically connected to the data PCB in a line on glass (LOG) method by bonding a signal line to an edge of the liquid crystal panel. Connected.

FIG. 1 is a block diagram illustrating a conventional line-on-glass type liquid crystal display device, wherein a color filter substrate 20 having R, G, and B primary colors is formed, and an array substrate 30 having a plurality of pixels is provided at a predetermined distance. A liquid crystal panel 10 spaced apart and bonded to the left end portion of the array substrate 30, and gate TCPs 46 to 48 having gate drivers 41 to 43 mounted thereon, and the array substrate 30. A plurality of gate control signals and power signals received from an external system (not shown) and data TCPs 56 to 59 bonded to an upper end portion of each other and mounted with data drivers 51 to 54. A timing controller 62 for supplying a plurality of data control signals and data signals to the data drivers 51 to 54, and a driving PCB 60 in which the timing controller 62 is mounted. do.

 In addition, the gate TCPs 46 to 48 are electrically connected to the driving PCB 60 to receive the gate control signal and the power signal. To this end, the PCB wiring formed on the driving PCB 60 is connected to the signal wiring on the liquid crystal panel 10.

Here, the signal wiring is defined as a line on grass (LOG) signal line L1 via an edge edge of the second substrate 30.

Such liquid crystal display devices tend to be increasingly large in accordance with user requirements. However, when the liquid crystal panel is implemented in a large screen, as the size increases, problems of uniformity and image quality of the screen due to signal delay of the gate driving signal may occur.

In more detail, the LOG signal line L1 is formed in a fine pattern by using the same metal layer as the gate lines (not shown) in the limited region at the edge end of the second substrate 30. In addition, as the LOG signal line L1 is electrically connected to the gate TCPs 46 to 48 through bonding, the contact portion with the gate TCPs 46 to 48 increases to increase the contact resistance. Accordingly, the LOG signal line L1 has a larger line resistance than the wiring on the conventional gate PCB.

Each of the LOG signal lines L1 has a line resistance proportional to its line length and is connected in series via the gate TCPs 46 to 48.

As a result, the gate control signal and the power signal supplied to the gate drivers 41 to 43 are distorted, which is a major cause of deterioration of the image quality.

The present invention has been made to solve the above problems, in the LOG type liquid crystal display device by reducing the line resistance of the LOG signal line of the liquid crystal panel, deterioration in image quality due to distortion of the gate control signal and power signal supplied to the gate driver Its purpose is to minimize it.

In order to achieve the above object, a LOG type liquid crystal display device according to the present invention includes a liquid crystal panel in which a color filter substrate and an array substrate are bonded; A timing controller configured to receive a control signal and a power signal from the outside; A driving PCB mounted with the timing controller and bonded to an upper end of the array substrate; A plurality of TCPs bonded to the side ends of the array substrate and mounted with a plurality of drivers for driving the liquid crystal panel under the control of the timing controller; At least one signal line selected from among the plurality of signal lines, the plurality of signal lines being connected to the plurality of TCPs and formed on the array substrate and supplying control signals and power signals of the plurality of drivers. The first sub-line via the plurality of TCPs having the same resistance value and the second sub-line directly connected to the plurality of drivers, characterized in that the configuration.

At least one signal line selected from among the plurality of signal lines may be a signal line formed at a position closest to an inner direction of the liquid crystal panel.

The second partial line has a different area of the line.

 The control signal of the plurality of drivers may be one selected from a gate output enable signal GOE, a gate shift clock signal GSC, and a gate start pulse signal GSP.

 The power signals of the plurality of drivers may be one selected from a ground voltage GND, a power voltage VCC, a common voltage Vcom, a gate high voltage VGH, and a gate low voltage VGL.

At least one signal line selected from among the plurality of signal lines is a signal line for supplying a gate low voltage VGL.

 The second partial line is characterized in that the area of the line is wider toward the lower end.

In the plurality of drivers, at least one input terminal is a gate driver IC positioned in the same direction as the output terminal.

Hereinafter, a liquid crystal display panel according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating a LOG type liquid crystal display device according to an exemplary embodiment of the present invention, in which a color filter substrate 120 having three primary colors of R, G, and B, and an array substrate 130 having a plurality of pixels are provided. First to third gate TCPs 146 to 148 bonded to the bonded liquid crystal panel 100 and the left end of the array substrate 130 and mounted with the first to third gate drivers 141 to 143. And first to fourth data TCPs 156 to 159 bonded to an upper end of the array substrate 130 and mounted with first to fourth data drivers 151 to 154.

In addition, the PCB wiring for supplying the gate control signal, the data control signal, the data signal and the power signal to the first to third gate drivers 141 to 143 and the first to fourth data drivers 151 to 154 may be provided. It is composed of a drive PCB (160) formed.

The driving PCB 160 receives a plurality of gate control signals and power signals from an external system (not shown) and supplies them to the first to third gate drivers 141 to 143, and a plurality of data control signals and data signals. The timing controller 162 is mounted to receive the input and supply the first to fourth data drivers 151 to 154.

Here, the first to third gate drivers 141 to 143 are electrically connected to the LOG signal lines L1, L2, and L3, each of which comprises a plurality of signal lines for receiving the gate control signal and the power signal. . The LOG signal lines L1, L2, and L3 are connected to the first to third gate TCPs 146 to 148, respectively, and are formed at the left edges of the second substrate 130.

More specifically, the first to third gate drivers 141 to 143 may include the gate output enable signal GOE, the gate shift clock signal GSC, and the gate start pulse signal GSP, which are signals necessary for driving. The gate control signal and power signals such as the ground voltage GND, the power supply voltage VCC, the common voltage Vcom, the gate high voltage VGH, and the gate low voltage VGL are inputted, and correspondingly, the array substrate ( The turn-on / off signal of the thin film transistor (not shown) formed at 130 sequentially supplies the gate high voltage VGH and the gate low voltage VGL one by one horizontal line.

To this end, first, the gate control signals and the power signals from the timing controller 162 are formed at the corner edge of the array substrate 130 through the first data TCP 156 through the PCB wiring of the driving PCB 160. It is connected to the first gate TCP 146 via the LOG signal line L1.

The first to fourth gate drivers 141 to 143 may include a plurality of input terminals and output terminals, and at least one of the plurality of input terminals may be a gate driver IC disposed in the same direction as the output terminal.

More specifically, as shown in the figure, one of the gate control signals and the power signals input to the first gate driver 141 through the first LOG signal line L1 is formed in the innermost direction of the liquid crystal panel. The signal line is divided into two lines before being connected to the first gate TCP 146, which is a wire directly connected to the first gate driver 141, and a second LOG via the first gate TCP 146. It is connected to the signal line L2.

In addition, one signal line formed in the innermost direction of the liquid crystal panel of the second LOG signal line L2 is divided into two lines before being connected to the second gate TCP 147, which is the second gate. The wiring directly connected to the driver 142 is connected to the third LOG signal line L3 via the second gate TCP 147.

In this case, the wires directly connected to the first gate driver 141 and the wires directly connected to the second gate driver 142 may be formed to have the same resistance value in consideration of a line delay.

In addition, one signal line formed in the innermost direction of the liquid crystal panel of the third LOG signal line L3 is directly connected to a third gate driver 143, which is the first gate driver 141. And a wire directly connected to the wire and a wire directly connected to the second gate driver 142.

Therefore, the signal delay of the gate control signal and the power signal due to the line resistance proportional to the line length is improved.

FIG. 3 is a view showing in detail the arrangement of the LOG signal lines of the LOG type liquid crystal display according to an exemplary embodiment of the present invention. As illustrated, the timing controller 162 includes gate drivers 141 and 142. Gate control signals such as gate output enable signal (GOE), gate shift clock signal (GSC), gate start pulse signal (GSP), ground voltage (GND), power supply voltage (VCC) Power signals such as the voltage Vcom, the gate high voltage VGH, and the gate low voltage VGL are supplied to the first and second gate drivers 141 and 142 through the LOG signal lines L1 and L2.

In the drawing, only some signal lines 170, 180, and 190 of the LOG signal lines are shown for convenience, and the gate control signal and the power signal may be selected from three signal lines 170, 180, and 190 according to a setting. It can also be supplied via a signal line, which is not limited to a particular signal line.

Here, the first partial line 191 and the first gate of the first LOG signal line L1 shown through the gate TCP 146 are connected to the signal line 190 closest to the inside of the array substrate 130. It is divided into the second partial line 192 directly input to the driver 141. In this case, in order to reduce the line resistance of the second partial line 192, the line area of the connected portion 195 of the first gate TCP 146 is larger than other signal lines.

In addition, among the second LOG signal lines L2 connected to the second gate driver 142, the signal line in the innermost direction of the liquid crystal panel may also be connected to the first partial line 191 via the first gate TCP 146. The first gate driver 141 is divided into a second partial line 192 directly input to the first gate driver 141, and the area of the line of the portion 197 connected to the second gate TCP 147 is the first gate TCP 146. Is formed larger than the portion 194 to be connected.

Here, the signal supplied through one LOG signal line formed in the inner direction of the liquid crystal panel 100 among the above-described LOG signal lines L1 and L2 is preferably a gate low signal VGL.

The distortion of the gate low signal VGL has the greatest influence in determining the image quality quality among the gate control signal and the power signal. More specifically, the gate low signal VGL maintains a constant level of the pixel voltage charged in the pixel in the gate high signal VGH period until the next pixel voltage is charged. This is because the level of the charged pixel voltage changes when distorted.

FIG. 4 is a schematic diagram illustrating a form in which a gate low signal VGL is input to a gate driver among LOG signal lines according to an exemplary embodiment of the present invention. FIG. 14 shows the routes of the gate low signals LVGL1, LVGL2, LVGL3 supplied to the signals 141 to 143, respectively.

As shown, in the embodiment of the present invention, the gate resistances LVGL1, LVGL2, and LVGL3 supplied to the gate drivers 141 to 143 are equally matched with line resistances, thereby causing variations in signal levels due to line delays. Will improve.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the present invention described in the claims below I can understand that you can.

Accordingly, the LOG type liquid crystal display device according to an embodiment of the present invention includes a signal line of one signal selected from a gate control signal and a power signal supplied to the gate driver and a signal line via a gate TCP and a corresponding gate driver. The signal lines are directly connected to each other, and the area of the signal lines directly connected to the corresponding gate drivers is increased to match the resistance values of the signal lines directly connected to the respective gate drivers.

Therefore, there is an effect of improving the problem of deterioration in image quality caused by line delay in proportion to the LOG line length.

Claims (8)

A liquid crystal panel to which a color filter substrate and an array substrate are bonded; A timing controller configured to receive a control signal and a power signal from the outside; A driving PCB mounted with the timing controller and bonded to an upper end of the array substrate; A plurality of TCPs bonded to the side ends of the array substrate and mounted with a plurality of drivers for driving the liquid crystal panel under the control of the timing controller; A plurality of signal lines connected to the plurality of TCPs, formed on the array substrate, and supplying control signals and power signals of the plurality of drivers; Wherein at least one signal line selected from among the plurality of signal lines includes a first partial line via the plurality of TCPs having the same resistance value, and a second partial line directly connected to the plurality of drivers. LOG type liquid crystal display device, characterized in that consisting of. The method of claim 1, And at least one signal line selected from among the plurality of signal lines is a signal line formed at a position closest to an inner direction of the liquid crystal panel. The method of claim 1, The second partial line is a LOG type liquid crystal display device, characterized in that the area of the line is different from each other. The method of claim 1,  And a control signal of the plurality of drivers is one selected from a gate output enable signal (GOE), a gate shift clock signal (GSC), and a gate start pulse signal (GSP). The method of claim 1,  The power signal of the plurality of drivers may be one selected from ground voltage GND, power voltage VCC, common voltage Vcom, gate high voltage VGH, and gate low voltage VGL. Type liquid crystal display device. The method of claim 1, The at least one signal line selected from among the plurality of signal lines is a signal line for supplying a gate low voltage (VGL). The method of claim 3, wherein The second partial line is a LOG type liquid crystal display device characterized in that the area of the line is wider toward the lower end. The method of claim 1, And wherein the plurality of drivers are gate driver ICs in which at least one input terminal is located in the same direction as the output terminal.

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