KR20080061979A - Pulse generator - Google Patents

Abstract

A pulse generating circuit is provided to generate a pulse having a constant pulse width regardless of the variation of process conditions by utilizing dull signals on the variation of the process conditions. A pulse generating circuit includes a pulse inputting unit(100) and a pulse regulating unit(140). The pulse inputting unit is used for inputting pulses. The pulse regulating unit synchronizes the inputted pulses with a regulation signal and outputs the synchronized input pulses as an output pulse. The pulse inputting unit inputs a column selection signal for controlling the delivery of data between bit lines and input/output lines, which are connected to a memory cell that is selected in a reading or writing operation of a semiconductor memory device, as the input pulses.

Description

Pulse generator circuit {PULSE GENERATOR}

1 is a block diagram showing a pulse generating circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating an example of the pulse shaping unit 140 of FIG. 1.

3 is a waveform diagram illustrating a pulse width change of the pulse OUTP output from the pulse shaping unit 140 of FIG. 2 according to a voltage change.

4 is a circuit diagram illustrating another example of the pulse shaping unit 140 of FIG. 1.

FIG. 5 is a circuit diagram illustrating still another embodiment of the pulse shaping unit 140 of FIG. 1.

The present invention relates to a pulse generating circuit, and more particularly to a pulse generating circuit for generating a pulse having a pulse width insensitive to process conditions.

In general, a pulse generation circuit using RC delay is fast compared to a slow state (Slow Condition: Slow Model, Low Voltage, High Temperature) due to process conditions, that is, PVT (Process, Voltage, Temperature) changes. Model, High Voltage, Low Temperature) generates pulse with width of about 1/3.

The pulses generated by these pulse generating circuits are not suitable for circuits that must operate stably with changes in process conditions.

For example, a pulse generation circuit for generating a column selection signal of a conventional semiconductor memory device generates a pulse using an RC delay, so that the column selection signal having a pulse width of about 1/3 in a fast state compared to a slow state Create

The column select signal generated by the pulse generator circuit is provided to the gate of the column select transistor connecting the bit line and the segment input / output line to each other to control the switching operation of the column select transistor.

At this time, when the gate of the column select transistor is sensitive, the current of the segment input / output line may affect the bit line sense amplifier at the moment when the column select transistor is turned on by the column select signal, thereby causing a noise defect. Therefore, the gate of the column select transistor is designed to be as insensitive as possible.

However, if the gate of the column select transistor is insensitive, the pulse width of the column select signal may become small in a fast state, and thus the column select transistor may not be sufficiently turned on. As a result, data may not be properly transferred to the bit line or the segment input / output line. You may not be able to.

Therefore, the pulse width of the column select signal should not be affected by the change in the process condition, and in order to generate a pulse insensitive to the change in the process condition like this column select signal, the conventional pulse generating circuit uses many resistors and MOS capacitors. It was. However, the use of many resistors and MOS capacitors does not significantly improve the skew of the process condition change and occupies only a large area of the circuit.

In particular, the voltage change during the process condition change greatly affects the pulse width, and the influence of the voltage change can be solved by using a large resistance. However, since the size of the resistor used to minimize the pulse width due to the voltage change is proportional to the area, there is a problem that the circuit size may be restricted.

As a result, a pulse generating circuit having a pulse width insensitive to changes in process conditions using a conventional RC delay has many implementation limitations.

An object of the present invention is to generate a pulse having a pulse width insensitive to changes in process conditions.

Another object of the present invention is to design a pulse generator circuit that does not occupy a large area and generates a pulse which is invariant to process condition changes.

According to an aspect of the present invention, there is provided a pulse generation circuit including: a pulse input unit configured to input a pulse; And a pulse shaping unit for outputting the input pulse as an output pulse in synchronization with the shaping signal.

Here, the shaping signal is a clock having a constant duty cycle, an external clock, an internal clock generated by an external clock, or a toggled external signal input to a semiconductor memory device, and the internal clock is an inverted and delayed external clock. The clock may be a clock or an internal clock used for an address latch in a semiconductor memory device, and the toggled external signal may be a chip select signal.

The pulse input unit may input a column selection signal that controls data transfer between a bit line connected to a selected memory cell and an input / output line during a read or write operation of a semiconductor memory device as the input pulse.

The pulse shaping unit may include: a driving unit for controlling a pull-up operation by the input pulse and controlling a pull-down operation by the output pulse fed back; A latch unit for latching an output signal of the driving unit; And an output unit configured to output an output signal as the output pulse in synchronization with the shaping signal, wherein the output pulse corresponds to a signal latched in the pull-up operation in synchronization with a first edge of the shaping signal. Preferably, a level shift occurs, and a level shift occurs in the output pulse corresponding to the signal latched in the pull-down operation in synchronization with the second edge of the shaped signal.

In this case, the input pulse is preferably enabled before the first edge of the shaping signal.

In the configuration of the pulse shaping section, the driving section includes: MOS transistor type pull-up means for pulling up an output stage by the input pulse; And MOS transistor type pull-down means for pulling down the output stage by the output pulse.

In the configuration of the pulse shaping section, the output section generates the output pulse shifted from a low level to a high level at a rising edge of the shaping signal, and the output pulse shifted from a high level to a low level at a falling edge of the shaping signal. Or generate the output pulse shifted from the low level to the high level at the falling edge of the shaped signal, and generate the output pulse shifted from the high level to the low level at the rising edge of the shaped signal. Do.

The output unit performing such an operation may include: a pulse generation unit configured to output the output signal as the output pulse in synchronization with the shaping signal; And a feedback unit feeding back the output pulse to the driving unit according to the state of the shaping signal.

In the configuration of the output unit, the pulse generator comprises: first switching means for transmitting a signal latched in the pull-up operation to a first node when the shaping signal is in a first state; Second switching means for transferring a latched signal to a second node in the pull-down operation when the shaped signal is in a second state; And transmission means for outputting the signals transmitted to the first and second nodes as the output pulses.

In the configuration of the pulse generator, it is preferable that the first and second switching means each include a three-phase inverter, and each three-phase inverter of the first and second switching means switches oppositely by the shaped signal. .

In addition, the transmission means preferably comprises a NAND gate NAND combination of the signal of the first node and the signal of the second node.

In the configuration of the output unit, the feedback unit preferably includes third switching means for transmitting the output pulse to the drive unit in accordance with the state of the shaping signal.

Here, the third switching means includes a three-phase inverter for switching according to the state of the shaping signal, wherein each of the three-phase inverter of the second and third switching means has the same switching timing by the shaping signal. Do.

On the other hand, it is preferable that the reset means for initialization is further connected to a node connecting between the driving unit and the latch unit, a node inside the output unit, and a node connecting between the driving unit and the output unit, respectively.

At this time, the reset means connected to the node inside the output unit is preferably connected to the node between the first switch means and the transfer means.

Each reset means having such a connection preferably includes MOS transistor type pull down means which is turned on by a reset signal enabled during initial operation to pull down each node.

According to another aspect of the present invention, a pulse generator circuit may include: a first pulse generator configured to operate by an input pulse to generate a first output pulse synchronized with a first state of a shaping signal; A second pulse generator configured to operate by the input pulse to generate a second output pulse synchronized with a second state of the shaping signal; And a selector configured to select one of the first output pulse and the second output pulse and output the third output pulse as a third output pulse.

The input pulse may be a column select signal that controls data transfer between a bit line connected to a selected memory cell and an input / output line during a read or write operation of a semiconductor memory device.

The shaping signal may be a clock having a constant duty cycle, an external clock, an internal clock generated by an external clock, or a toggled external signal input to a semiconductor memory device, wherein the internal clock is an inverted and delayed external clock. The clock may be a clock or an internal clock used for an address latch in a semiconductor memory device, and the toggled external signal may be a chip select signal.

The first pulse generator may include: a first driver configured to control a pull up operation by the input pulse and to control a pull down operation by the first output pulse fed back; A first latch unit for latching an output signal of the first driver; A first output pulse that is shifted from a low level to a high level in response to a signal latched in the pull-up operation at the rising edge of the shaping signal and latched in the pull-down operation at the falling edge of the shaping signal A first output unit configured to generate the first output pulse shifted from a high level to a low level corresponding to the first output pulse; A first feedback unit feeding back the first output pulse to the first driver at the falling edge of the shaped signal; And initializing a node between the first driver and the first latch unit, a node inside the first output unit, and a node between the first feedback unit and the first driver by a reset signal enabled during initial operation. It is preferable to include; a first reset unit.

In the configuration of the first pulse generator, the first driver comprises: first MOS transistor type pull-up means for pulling up an output terminal by the input pulse; And first MOS transistor type pull-down means for pulling down the output stage by the output pulse.

The first output unit may further include: first switching means for transmitting a signal latched in the pull-up operation at a rising edge of the shaping signal; Second switching means for transferring a latched signal in the pull down operation at a falling edge of the shaped signal; And first transmission means for outputting the signals transmitted from the first and second switching means as the first output pulse.

In the configuration of the first output unit, the first and second switching means switch a three-phase inverter for switching by the shaping signal and inverting and transmitting the signal latched by the pull-up operation and the signal latched by the pull-down operation. It is preferable to include each.

Further, the first transfer means preferably includes a NAND gate for NAND combining the signals transmitted from the first and second switching means.

In the configuration of the first pulse generator, it is preferable that the first feedback unit includes third switching means for transmitting the first output pulse to the first driver at the falling edge of the shaping signal.

Here, the third switching means preferably comprises a three-phase inverter for inverting the second output pulse to the second driver according to the state of the shaping signal.

In the configuration of the first pulse generator, the first reset unit is a node between the first driver and the first latch unit, a node inside the first output unit, the first feedback unit and the first feedback unit by the reset signal. It is preferred to include a plurality of pull down means for respectively pulling down the nodes between the one drive.

At this time, the pull-down means for pulling down the node inside the first output unit is preferably connected to the node between the first switching means and the transfer means.

On the other hand, the second pulse generation unit, the pull-up operation is controlled by the input pulse, the pull-down operation is controlled by the second output pulse is fed back; A second latch unit for latching an output signal of the second driver; A second output pulse shifted from a low level to a high level corresponding to the signal latched in the pull-up operation at the falling edge of the shaped signal, and latched in the pull-down operation at the rising edge of the shaped signal A second output unit configured to generate the second output pulse shifted from a high level to a low level corresponding to the second output pulse; A second feedback unit feeding back the second output pulse to the second driver at the rising edge of the shaped signal; And initializing a node between the second driver and the second latch unit, a node inside the second output unit, and a node between the second feedback unit and the second driver by a reset signal enabled during an initial operation. It is preferable to include a; second reset unit.

In the configuration of the second pulse generator, the second driver, second MOS transistor type pull-up means for pulling up the output terminal by the input pulse; And second MOS transistor type pull-down means for pulling down the output stage by the output pulse.

The second output unit may further include: fourth switching means for transferring a signal latched in the pull-up operation at the falling edge of the shaping signal; Fifth switching means for transferring a latched signal in the pull-down operation at the rising edge of the shaped signal; And second transmission means for outputting signals transmitted from the fourth and fifth switching means as the second output pulse.

In the configuration of the second output unit, the fourth and fifth switching means inverts and transfers the latched signal in the pull-up operation and the latched signal in the pull-down operation according to the state of the shaping signal. It is preferable to include each.

In addition, the second transfer means preferably includes a NAND gate for NAND combining the signals transmitted from the fourth and fifth switching means.

In the configuration of the second pulse generator, the second feedback unit preferably includes sixth switching means for transferring the second output pulse to the second driver at the rising edge of the shaping signal.

Here, the sixth switching means preferably includes a three-phase inverter for inverting and transmitting the second output pulse to the second driver according to the state of the shaping signal.

In the configuration of the second pulse generator, the second reset part is a node between the second driving part and the second latch part, a node inside the second output part, the second feedback part and the second part by the reset signal. It is preferable to include a plurality of pull down means for respectively pulling down the node between the two drives.

At this time, the pull-down means for pulling down the node inside the second pulse generator is preferably connected to the node between the fourth switching means and the transfer means.

Preferably, the selector outputs the third output pulse enabled when either one of the first output pulse and the second output pulse is enabled.

The selector for performing such an operation may include: a noah gate for quinoa combining the first output pulse and the second output pulse; And an inverter for inverting the output signal of the NOR gate and outputting the third output pulse.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a pulse is generated using a signal corresponding to a constant duty cycle, an external clock, or an external clock, and a signal corresponding to an external clock refers to a clock generated by inverting and delaying an external clock.

In one embodiment, the pulse generation circuit of the present invention is configured to generate the pulse OUTP synchronized with the high level section of the shaping signal FIX_SIG using the shaping signal FIX_SIG as shown in FIG. 1.

Here, as described above, the shaping signal FIX_SIG is a clock, an external clock, or a signal corresponding to an external clock having a constant duty cycle, and the signal corresponding to the external clock is an internal clock or a semiconductor memory device generated by an external clock. It means a toggling external signal input to. The internal clock refers to a clock in which an external clock is inverted and delayed or a clock used for address latching in a semiconductor memory device, and the external signal toggled refers to a chip select signal related to a command.

Specifically, the pulse generating circuit of the present invention includes a pulse input unit 100 for inputting the pulse INP, and a pulse shaping unit 140 for outputting the input pulse INP as an output pulse in synchronization with the shaping signal FIX_SIG.

The pulse input unit 100 inputs a target pulse INP, that is, a pulse INP that is greatly influenced by a change in process conditions, to the pulse shaping unit 140. For example, the pulse input unit 100 may input a column selection signal that controls data transfer between a bit line connected to a selected memory cell and an input / output line during a read or write operation of a semiconductor memory device as an input pulse INP.

As shown in FIG. 2, the pulse shaping unit 140 may include a reset unit 200 for initializing a circuit before operation, a pull-up operation controlled by an input pulse INP, and an output pulse OUTP fed back. By the pull-down operation controlled by the drive unit 210, the latch unit 220 for latching the output signal of the drive unit 210, and the output signal of the latch unit 220 is output in synchronization with the high level period of the shaping signal FIX_SIG The output unit 230 outputs the pulse OUTP.

The reset unit 200 initializes the nodes A, C, and F with the reset signal RST enabled during initial operation.

The reset unit 200 that performs the initialization may be configured with pull-down elements that pull down each of the nodes A, C, and F. Preferably, the reset unit 200 is connected to the node A and is connected to the node A. The NMOS transistor N1 for initializing (A), the NMOS transistor N2 connected to the node C to initialize the node C by the reset signal RST, and the reset signal RST connected to the node F It may be composed of an NMOS transistor N3 for initializing the node F.

Here, the node A corresponds to the output terminal of the driver 12, the node C corresponds to the node included in the pulse generator 231 of the output unit 230, which will be described later, and the node F will be described later. It corresponds to the output terminal of the feedback unit 232 of the output unit 230.

That is, each of the NMOS transistors N1 to N3 is turned on by the reset signal RST to lower each node A, C, and F to the ground voltage VSS level, and each node A, C, and F is connected to the ground voltage VSS. As it descends to the level, the pulse generator circuit is reset to its initial state.

The driver 210 provides the power supply voltage VDD to the node A by the input pulse INP, and provides the ground voltage VSS to the node A by the output pulse OUTP transmitted from the feedback unit 232.

The driving unit 210 that performs the driving includes an inverter IV1 that inverts the input pulse INP, a pull-up element that pulls up the node A by the output signal of the inverter IV1, and a node by the output pulse OUTP. It may be configured as a pull-down element for pulling down A).

In this case, the pull-up device may be configured as a PMOS transistor P1 that is turned on by the output signal of the inverter IV1 to raise the node A to the power supply voltage VDD level, and the pull-down device is configured by the output pulse OUTP. It may be configured as an NMOS transistor N4 that is turned on to lower the node A to the ground voltage VSS level.

The latch unit 220 latches the signal transmitted to the node A, the inverter IV2 which inverts the signal of the node A and transmits the signal to the node B, and the node B by inverting the signal of the node B. It may be composed of an inverter IV3 for transferring to (A). Here, the node B corresponds to the output terminal of the latch unit 220.

The output unit 230 outputs the pulse latched by the latch unit 220 to the output pulse OUTP in synchronization with the high level period of the shaping signal FIX_SIG, and the output pulse OUTP at the falling edge of the shaping signal FIX_SIG. It includes a feedback unit 232 for feeding back to the drive unit (210).

The above-described pulse generator 231 is an inverter IV4 that inverts the shaping signal FIX_SIG, and a three-phase that inverts the signal of the node B and transmits it to the node C when the output signal of the inverter IV4 is at a low level. When the output signal of the inverters TIV1 and IV4 is at a high level, the signal of the three-phase inverter TIV2 and the node C and the node D that inverts and transmits the signal of the node B to the node D. NAND gate NA1 for NAND-combining the signal of the (), and an inverter IV5 for inverting the output signal of the NAND gate NA1 and outputting it to the output pulse OUTP.

In addition, the feedback unit 232 described above inverts the output signal of the inverter IV5 and inverts the output signal of the inverter IV6 when the output signal of the inverter IV4 is at a high level. It may be configured as a three-phase inverter (TIV3) to transfer to F).

Each of the three-phase inverters TIV1 to TIV3 of the pulse generator 231 and the feedback unit 232 is a transfer element that determines whether to transfer or not according to the output signal of the inverter IV4 and an inverting element that inverts the output of the transfer element. It can be replaced, for example, it may be composed of a pass gate (Pass Gate) and an inverter.

Looking at the operation of the pulse shaping unit 140 of Figure 2 having such a configuration in detail as follows.

First, when the reset signal RST is enabled, each node A, C, and F is initialized to a low level.

When the input pulse INP is input at the high level, the PMOS transistor P1 is turned on to raise the node A to the high level. And the latch part 13 latches the signal of the high level supplied to the node A. As shown in FIG. At this time, the input pulse INP is preferably transitioned to a high level before the shaping signal FIX_SIG.

Then, when the shaping signal FIX_SIG transitions to a high level, the signal latched by the latch unit 30 is inverted through the three-phase inverter TIV1 and transmitted to the node C.

The signal of the node C is inverted by the NAND gate NA1, and the output signal of the NAND gate NA1 is inverted through the inverter IV5 and outputted to the output pulse OUTP.

After the output pulse OUTP is inverted through the inverter IV6, when the shaping signal FIX_SIG is at a low level, the output pulse OUTP is inverted again through the three-phase inverter TIV3 and transferred to the node F. That is, since the output pulse OUTP is at the high level, the node F rises to the high level when the shaping signal FIX_SIG changes to the low level.

When the node F rises to the high level, the NMOS transistor N4 is turned on to lower the node A to the low level. Accordingly, the node B rises to a high level, and the signal of the node B is inverted through the three-phase inverter TIV2 and transmitted to the node D.

Therefore, since the node D is at the low level, the output pulse OUTP is disabled at the low level by the NAND gate NA1 and the inverter IV5.

That is, the pulse shaping unit 140 of FIG. 2 latches the input pulse IN when the input pulse IN is input and enables the output pulse OUTP when the shaping signal FIX_SI is at a high level, and output pulses when the shaping signal FIX_SIG is at a low level. Disable OUTP.

Therefore, the high level section of the output pulse OUTP has the same pulse width as the high level section of the shaping signal FIX_SIG.

As described above, the pulse generation circuit of the present invention including the pulse shaping unit 140 of FIG. 2 generates an output pulse OUTP synchronized with the high level period of the shaping signal FIX_SIG by using the shaping signal FIX_SIG invariant to PVT change. Output pulse OUTP is hardly affected by PVT variation.

As a result of testing the pulse OUTP output from the pulse shaping unit 140 of FIG. 2 according to the voltage change during the process conditions, as shown in FIG. 3, the voltage rises to 2V or to 1.6V based on 1.8V. It can be seen that an output pulse OUTP with a substantially constant pulse width is produced.

As another example, as illustrated in FIG. 4, the pulse shaping unit 140 may be configured to generate a pulse OUTP synchronized with a low level period of the shaping signal FIX_SIG using the shaping signal FIX_SIG insensitive to PVT variation.

Specifically, in the pulse shaping unit 140 of FIG. 4, the pull-up operation is controlled by the reset unit 400, the input pulse INP, which makes the circuit before operation an initial state, and the pull-down operation is controlled by the output pulse OUTP fed back. Output to output to output pulse OUTP by synchronizing the controlled driving unit 410, the latching unit 420 latching the output signal of the driving unit 410, and the output signal of the latching unit 420 in the low level section of the shaping signal FIX_SIG. The unit 430 is included.

Here, since the reset unit 400, the driving unit 410, and the latch unit 420 have the same configuration as the reset unit 200, the driving unit 210, and the latch unit 220 of FIG. 2, the description thereof will be described. It will be omitted.

The output unit 430 outputs the pulse latched by the latch unit 420 to the output pulse OUTP in synchronization with the low level period of the shaping signal FIX_SIG, and the output pulse OUTP at the rising edge of the shaping signal FIX_SIG. It includes a feedback unit 432 for feeding back to the driving unit 410.

The above-described pulse generator 431 includes the inverter IV7 for inverting the shaping signal FIX_SIG, the inverter IV4 for inverting the output signal of the inverter IV7, and the node B when the output signal of the inverter IV4 is at a low level. 3 phase inverter (TIV1) that inverts the signal of) and transmits it to the node (C), and 3 phase inverter that inverts the signal of the node (B) and transmits it to the node (D) when the output signal of the inverter (IV4) is high level. Inverter TIV2, NAND gate NA1 that NAND-combines the signal of node C and the signal of node D, and inverter IV5 that inverts the output signal of NAND gate NA1 to output pulse OUTP. It can be configured as.

In addition, the feedback unit 432 inverts the output signal of the inverter IV5 and the node IV by inverting the output signal of the inverter IV6 when the output signal of the inverter IV4 is at a high level. It may be configured as a three-phase inverter (TIV3) to transfer to F).

When the shaping signal FIX_SIG transitions to a low level after the input pulse INP transitions to a high level, the pulse shaping unit 140 having the configuration as shown in FIG. 4 synchronizes the low level section of the shaping signal FIX_SIG to generate a high level pulse. The output pulse OUTP is output.

When the shaping signal FIX_SIG transitions to the high level, the driving unit 220 lowers the node A to the low level by the output pulse OUTP fed back from the feedback unit 242, so that the output pulse OUTP is disabled to the low level. do.

Therefore, since the pulse shaping unit 140 of FIG. 4 generates an output pulse OUTP synchronized with the interval from the predetermined falling edge to the rising edge of the shaping signal FIX_SIG in response to the PVT change, the output pulse OUTP is almost constant regardless of the PVT change. It may have a pulse width.

According to another embodiment of the present invention, the pulse shaping unit 140 may include any one of an output pulse OUTP1 synchronized with a high level section of a shaping signal FIX_SIG and a output pulse OUTP2 synchronized with a low level section, as shown in FIG. 5. Can be configured to output to the output pulse OUTP.

Specifically, the pulse shaping unit 140 of FIG. 5 includes the pulse generator 500 generating the output pulse OUTP1 synchronized with the high level section of the shaping signal FIX_SIG, and the output pulse OUTP2 synchronizing with the low level section of the shaping signal FIX_SIG. And a selector 520 for selecting one of the output pulse OUTP1 and the output pulse OUTP2 and outputting the selected output pulse OUTP2.

Here, the pulse generator 500 has the same configuration as that of FIG. 2, and the pulse generator 510 has the same configuration as that of FIG. 4. In addition, the selector 520 may include a NOR gate NR that combines the output pulse OUTP1 and the output pulse OUTP2 with a NOR, and an inverter IV8 that inverts the output of the NOR gate NR.

The pulse shaping unit 140 of FIG. 5 having such a configuration selects one of the output pulse OUTP1 and the output pulse OUTP2 according to the input shaping signal FIX_SIG, and outputs the output pulse OUTP.

That is, when the shaping signal FIX_SIG transitions from the low level to the high level after the input pulse INP is input to the high level, the output pulse OUTP1 is output to the output pulse OUTP, and the shaping signal FIX_SIG transitions from the high level to the low level, Output pulse OUTP2 is output as output pulse OUTP.

The output pulse OUTP is similarly generated in synchronization with the shaping signal FIX_SIG which is invariant with the process condition change, and thus maintains a constant pulse width with little influence from the process condition change.

As described above, the present invention generates a pulse that is synchronized to a high or low level interval of the shaping signal FIX_SIG, which is an internal clock, an external clock, or another external input, so that the pulse has a substantially constant pulse width regardless of process condition changes. Can be generated.

In addition, since the present invention generates a pulse synchronized with the shaping signal FIX_SIG using the shaping signal FIX_SIG, it is possible to generate a pulse which is invariant to the process condition change without using a large area of resistance and a MOS capacitor.

On the other hand, the present invention is applicable to all circuits that always require a pulse having a constant width.

For example, when applied to a semiconductor memory device, a column select transistor for transferring data amplified by a write driver to a corresponding bit line during a write operation transfers a large amount of charge to the bit line as the pulse width of the column select signal is larger.

In this case, the gate of the column select transistor is insensitive to the gate of the column select transistor because the current of the segment input / output line may affect the bit line sense amplifier and cause noise defects when the column select transistor is turned on by the column select signal. Is designed.

Such a gate-insensitive column select transistor may not be sufficiently turned on when the pulse width of the column select signal decreases due to a change in process conditions. As a result, data may not be properly transferred to a bit line or a segment input / output line. have.

However, when the pulse generated in the present invention is used as the column select signal, an embodiment of the present invention generates a column select signal having a pulse width invariant to the process condition change, so that sufficient charge is transferred to the bit line regardless of the process condition change. There is an effect that can be delivered.

As described above, since the present invention generates a pulse synchronized with the clock by using a signal invariant with a change in the process condition, there is an effect that a pulse having a substantially constant pulse width can be generated regardless of the change in the process condition.

In addition, since the present invention generates a pulse synchronized with the clock by using a signal that is invariant to process conditions without using a resistor and a capacitor that occupies a large area, an area of a circuit for generating a pulse that is invariant to process conditions may be reduced. It works.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (52)

A pulse input unit for inputting a pulse; And And a pulse shaping unit for outputting the input pulse as an output pulse in synchronization with the shaping signal. The method of claim 1, And the pulse input unit inputs a column selection signal for controlling data transfer between a bit line and an input / output line connected to a selected memory cell during a read or write operation of a semiconductor memory device as the input pulse. The method of claim 1, And said shaped signal is a clock having a constant duty cycle. The method of claim 1, And the shaped signal is an external clock. The method of claim 1, And the shaping signal is an internal clock generated by an external clock. The method of claim 5, wherein And wherein the internal clock is a clock whose external clock is inverted and delayed. The method of claim 5, wherein And the internal clock is an internal clock used for an address latch in a semiconductor memory device. The method of claim 1, And the shaped signal is a toggled external signal input to a semiconductor memory device. The method of claim 8, And the toggled external signal is a chip select signal. The method of claim 1, The pulse shaping unit, A driver for controlling a pull-up operation by the input pulse and controlling a pull-down operation by the output pulse fed back; A latch unit for latching an output signal of the driving unit; And And an output unit configured to output the output signal as the output pulse in synchronization with the shaping signal. A level shift of the output pulse corresponding to a signal latched in the pull-up operation in synchronization with a first edge of the shaping signal occurs, and in a signal latched in the pull-down operation in synchronization with a second edge of the shaping signal And a level shift of the corresponding output pulse occurs. The method of claim 10, And the input pulse is enabled before the first edge of the shaped signal. The method of claim 10, The driving unit, MOS transistor type pull-up means for pulling up an output stage by said input pulse; And And a MOS transistor type pull down means for pulling down the output stage by the output pulse. The method of claim 10, The output unit generates the output pulse shifted from the low level to the high level at the rising edge of the shaping signal, and generates the output pulse shifted from the high level to the low level at the falling edge of the shaping signal. Pulse generating circuit. The method of claim 10, The output unit generates the output pulse shifted from a low level to a high level at a falling edge of the shaped signal, and generates the output pulse shifted from a high level to a low level at a rising edge of the shaped signal. Pulse generating circuit. The method of claim 10, The output unit, A pulse generator for outputting the output signal as the output pulse in synchronization with the shaping signal; And And a feedback unit for feeding back the output pulse to the driving unit in accordance with the state of the shaping signal. The method of claim 15, The pulse generator, First switching means for transferring a latched signal to a first node in the pull-up operation when the shaped signal is in a first state; Second switching means for transferring a latched signal to a second node in the pull-down operation when the shaped signal is in a second state; And And transfer means for outputting the signals transmitted to the first and second nodes as the output pulses. The method of claim 16, And said first and second switching means each comprise a three-phase inverter, wherein each three-phase inverter of said first and second switching means switches oppositely by said shaped signal. The method of claim 16, And the transfer means comprises a NAND gate NAND combining the signal of the first node and the signal of the second node. The method of claim 15, And the feedback unit includes third switching means for transmitting the output pulse to the driving unit according to the state of the shaping signal. The method of claim 17 or 19, The third switching means includes a three-phase inverter for switching according to the state of the shaping signal, wherein each three-phase inverter of the second and third switching means has the same switching timing by the shaping signal. Pulse generating circuit. The method of claim 10, And a reset means for initialization is further connected to a node connecting the drive unit and the latch unit, a node inside the output unit, and a node connecting the drive unit and the output unit, respectively. The method of claim 16 or 21, A reset means connected to a node inside said output portion is connected to a node between said first switch means and said transfer means. The method of claim 21, And said reset means comprises MOS transistor type pull down means which is turned on by a reset signal enabled during initial operation to pull down each node. A first pulse generator configured to operate by an input pulse to generate a first output pulse synchronized with the first state of the shaping signal; A second pulse generator configured to operate by the input pulse to generate a second output pulse synchronized with a second state of the shaping signal; And And a selector configured to select one of the first output pulse and the second output pulse and output the third output pulse as a third output pulse. The method of claim 24, And the input pulse is a column select signal for controlling data transfer between a bit line connected to a selected memory cell and an input / output line during a read or write operation of a semiconductor memory device. The method of claim 24, And said shaped signal is a clock having a constant duty cycle. The method of claim 24, And the shaped signal is an external clock. The method of claim 24, The shaping signal is a pulse generating circuit characterized in that for receiving an internal clock generated by an external clock, respectively. The method of claim 28, And wherein the internal clock is a clock whose external clock is inverted and delayed. The method of claim 28, And the internal clock is an internal clock used for an address latch in a semiconductor memory device. The method of claim 24, And the shaped signal is a toggled external signal input to a semiconductor memory device. The method of claim 31, wherein And the toggled external signal is a chip select signal. The method of claim 24, The first pulse generator, A first driver controlling a pull-up operation by the input pulse and controlling a pull-down operation by the first output pulse fed back; A first latch unit for latching an output signal of the first driver; A first output pulse that is shifted from a low level to a high level in response to a signal latched in the pull-up operation at the rising edge of the shaping signal and latched in the pull-down operation at the falling edge of the shaping signal A first output unit configured to generate the first output pulse shifted from a high level to a low level corresponding to the first output pulse; A first feedback unit feeding back the first output pulse to the first driver at the falling edge of the shaped signal; And A node for initializing a node between the first driver and the first latch unit, a node inside the first output unit, and a node between the first feedback unit and the first driver by a reset signal enabled during an initial operation; 1 reset unit; pulse generating circuit comprising a. The method of claim 33, wherein The first driving unit, First MOS transistor type pull-up means for pulling up an output stage by the input pulse; And And a first MOS transistor type pull down means for pulling down the output terminal by the output pulse. The method of claim 33, wherein The first output unit, First switching means for transferring a latched signal to the pull-up operation at the rising edge of the shaped signal; Second switching means for transferring a latched signal in the pull down operation at the falling edge of the shaped signal; And And first transmission means for outputting the signals transmitted from the first and second switching means as the first output pulses. 36. The method of claim 35 wherein Wherein the first and second switching means each include a three-phase inverter for switching by the shaping signal and inverting and transmitting the latched signal in the pull-up operation and the latched signal in the pull-down operation, respectively. Generation circuit. 36. The method of claim 35 wherein And said first transfer means comprises a NAND gate for NAND combining the signals transmitted from said first and second switching means. The method of claim 33, wherein And the first feedback unit comprises third switching means for transmitting the first output pulse to the first driver at the falling edge of the shaped signal. The method of claim 38, And the third switching means includes a three-phase inverter for inverting the second output pulse and transferring the second output pulse to the second driver in accordance with the state of the shaping signal. The method of claim 33, wherein The first reset unit pulls down a node between the first driver and the first latch unit, a node inside the first output unit, and a node between the first feedback unit and the first driver by the reset signal. Pulse generating circuitry comprising a plurality of pull-down means. 41. The method of claim 35 or 40, A pull down means for pulling down a node inside said first output portion is connected to a node between said first switching means and said transfer means. The method of claim 24, The second pulse generator, A second driver for controlling a pull-up operation by the input pulse and controlling a pull-down operation by the second output pulse fed back; A second latch unit for latching an output signal of the second driver; A second output pulse shifted from a low level to a high level corresponding to the signal latched in the pull-up operation at the falling edge of the shaped signal, and latched in the pull-down operation at the rising edge of the shaped signal A second output unit configured to generate the second output pulse shifted from a high level to a low level corresponding to the second output pulse; A second feedback unit feeding back the second output pulse to the second driver at the rising edge of the shaped signal; And Initializing a node between the second driver and the second latch unit, a node inside the second pulse generator, and a node between the second feedback unit and the second driver by a reset signal enabled during an initial operation. And a second reset unit. The method of claim 42, The second drive unit, Second MOS transistor type pull-up means for pulling up an output stage by said input pulse; And And a second MOS transistor type pull down means for pulling down the output terminal by the output pulse. The method of claim 42, The second output unit, Fourth switching means for delivering a latched signal to the pull-up operation at the falling edge of the shaped signal; Fifth switching means for transferring a latched signal in the pull-down operation at the rising edge of the shaped signal; And And second transmission means for outputting the signals transmitted from the fourth and fifth switching means as the second output pulses. The method of claim 44, And the fourth and fifth switching means each include a three-phase inverter for inverting and transmitting the signal latched by the pull-up operation and the signal latched by the pull-down operation according to the state of the shaping signal. Generation circuit. The method of claim 44, And said second transfer means comprises a NAND gate for NAND combining the signals transmitted from said fourth and fifth switching means. The method of claim 42, And the second feedback part comprises sixth switching means for transmitting the second output pulse to the second driver at the rising edge of the shaped signal. The method of claim 47, And the sixth switching means includes a three-phase inverter inverting the second output pulse and transferring the second output pulse to the second driver in accordance with the state of the shaping signal. The method of claim 42, The second reset unit pulls down a node between the second driver and the second latch unit, a node inside the second output unit, and a node between the second feedback unit and the second driver by the reset signal. Pulse generating circuitry comprising a plurality of pull-down means. The method of claim 44 or 49, A pull-down means for pulling down the node inside the second output part is connected to a node between the fourth switching means and the transfer means. The method of claim 24, And the selector outputs the third output pulse enabled when either one of the first output pulse and the second output pulse is enabled. The method of claim 51 wherein The selection unit, A NOR gate for NOR combining the first output pulse and the second output pulse; And And an inverter for inverting the output signal of the NOR gate and outputting the third output pulse as the third output pulse.

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