KR20080061870A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20080061870A
KR20080061870A KR1020060137024A KR20060137024A KR20080061870A KR 20080061870 A KR20080061870 A KR 20080061870A KR 1020060137024 A KR1020060137024 A KR 1020060137024A KR 20060137024 A KR20060137024 A KR 20060137024A KR 20080061870 A KR20080061870 A KR 20080061870A
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KR
South Korea
Prior art keywords
pattern
gate
layer
hard mask
semiconductor device
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Application number
KR1020060137024A
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Korean (ko)
Inventor
김세진
김재영
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주식회사 하이닉스반도체
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Priority to KR1020060137024A priority Critical patent/KR20080061870A/en
Publication of KR20080061870A publication Critical patent/KR20080061870A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to reduce the line-width of a gate pattern and to improve ID(Isolation/Dense) bias between a cell and a peripheral regions by using a trimming process. A gate conductive layer, a gate hard mask layer and an anti-reflection layer are sequentially formed on a substrate(200). An anti-reflection pattern is formed by etching the anti-reflection layer using a photoresist pattern. By performing a trimming process, the line-width(D2) of the photoresist pattern and the anti-reflection pattern is reduced. A hard mask pattern is formed by etching the gate hard mask layer using the reduced photoresist pattern(270a) and anti-reflection pattern(260b) as a mask. After the photoresist pattern and the anti-reflection pattern are removed, a gate pattern is formed by etching the gate conductive layer using the hard mask pattern as a mask.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1D are cross-sectional views illustrating a gate pattern forming method of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a gate pattern forming method of a semiconductor device according to the present invention.

3A and 3B are SEM photographs showing gate pattern profiles before and after performing a trimming process.

<Description of Symbols for Major Parts of Drawings>

100, 200: semiconductor substrate 110, 210: gate oxide film

120, 220: gate polysilicon layer 130: tungsten silicide

140, 240: hard mask layer 150, 250: silicon oxynitride film

160, 260: antireflection film 170: photosensitive film pattern

143, 245: gate pattern 230: gate metal layer

243: spacer 210a: gate oxide film pattern

260a: first antireflection film pattern 270: first photoresist film pattern

270a: second photoresist film pattern 260b: second antireflection film pattern

250a: silicon oxynitride film pattern 240a: hard mask layer pattern

230a: gate metal layer pattern 220a: gate polysilicon layer pattern

The present invention relates to a method for manufacturing a semiconductor device, the method comprising: forming a gate material layer, a gate hard mask layer, and an antireflection film on a semiconductor substrate; forming a photoresist pattern on the antireflection film;

Etching the anti-reflection film by using the photoresist pattern as a mask to form an anti-reflection film pattern, and performing a trimming process on the resultant to reduce line widths of the photoresist pattern and the anti-reflection film pattern; Forming a gate hard mask layer pattern by etching the gate hard mask layer using the photoresist pattern and the anti-reflection film pattern having a reduced line width, removing the photoresist pattern and the anti-reflection film pattern, and the gate hard mask layer A method of forming a gate pattern by etching the gate material layer using a pattern as a mask is disclosed, and a technique of improving ID isolation (Dense Bias) characteristics between a cell region and a peripheral circuit region is disclosed.

In general, a semiconductor device includes a plurality of unit cells therein. As semiconductor devices are highly integrated, semiconductor devices must be formed at a high density on a predetermined cell area. As a result, the size of unit devices such as transistors and capacitors is gradually reduced. In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule is reduced, the size of semiconductor devices formed inside the cell is gradually decreasing.

As the semiconductor device becomes more integrated, the cell pattern becomes denser, which increases the difference in etching bias between the isolation pattern of the cell region and the dense pattern of the peripheral circuit region. This deterioration problem occurs.

1A to 1D are cross-sectional views illustrating a gate pattern forming method of a semiconductor device according to the prior art.

Referring to FIG. 1A, a gate oxide layer 110, a gate polysilicon layer 120, a tungsten silicide layer (Wsix, 130), a hard mask nitride layer 140, and a silicon oxynitride layer (SiON) 150 are formed on a semiconductor substrate 100. ) And an antireflection film (Organic Bottom ARC, 160) are sequentially formed.

Next, a photoresist pattern 170 defining a gate pattern is formed on the resultant.

Referring to FIG. 1B, the anti-reflection film 160 is etched using the photoresist pattern 170 as a mask to form the anti-reflection film pattern 160a.

Next, the silicon oxynitride film 150 and the hard mask nitride film 140 are sequentially etched using the photoresist pattern 170 and the antireflection film pattern 160a as a mask to sequentially etch the silicon oxynitride film pattern 150a and the hard mask nitride film pattern 140a. ).

Next, the photoresist pattern 170 is removed.

Referring to FIG. 1C, the photoresist pattern 170, the antireflection film pattern 160a, and the silicon oxynitride film pattern 150a are removed.

Referring to FIG. 1D, the tungsten silicide layer 130, the gate polysilicon layer 120, and the gate oxide layer 110 are sequentially etched using the hard mask nitride layer pattern 140a as a mask to form the gate oxide layer pattern 110a and the gate poly. A gate pattern 143 including the silicon layer pattern 120a, the tungsten silicide layer pattern 130a, and the hard mask nitride layer pattern 140a is formed.

At this time, during the etching process of the anti-reflection film 160 or the hard mask nitride film 140, the amount of 02 gas was increased to simultaneously control the critical dimension of the gate pattern of the cell region and the peripheral circuit region. However, due to the high integration of the device, the space margin between the dense patterns of the cell region is insufficient, and when the threshold dimension of the peripheral circuit region gate pattern is reduced, the threshold dimension of the cell region gate pattern is further reduced compared to the peripheral circuit region. do.

In the method of manufacturing a semiconductor device according to the related art described above, when the threshold of the dense pattern of the cell region is reduced by 1 nm, the isolation pattern of the peripheral circuit region is further reduced by 1.5 to 3 times. Phenomenon occurs. At this time, in order to simultaneously adjust the pattern threshold of the cell region and the peripheral circuit region, the threshold of the cell region should be increased during the exposure process for forming the gate pattern, which is caused by a pattern bridge due to lack of process margin. There is a problem that the characteristics of the device is deteriorated.

In order to solve the above problem, after the anti-reflection film is etched, the cell region is applied by applying a trimming process of isotropically etching the photoresist pattern by mixing a low pressure of 1.5 mT or less and O2, HBr and Ar gas in a ratio of 1: 4: 7. An object of the present invention is to provide a method for manufacturing a semiconductor device that improves the ID bias (Dense Bias) characteristics between the circuit and the peripheral circuit region.

Method for manufacturing a semiconductor device according to the present invention

Forming a gate material layer, a gate hard mask layer, and an antireflection film on the semiconductor substrate;

Forming a photoresist pattern on the anti-reflection film;

Etching the anti-reflection film using the photoresist pattern as a mask to form an anti-reflection film pattern;

Performing a trimming process on the resultant to reduce line widths of the photoresist pattern and the anti-reflection film pattern;

Forming a gate hard mask layer pattern by etching the gate hard mask layer using the photoresist pattern and the anti-reflection film pattern having the reduced line width as a mask;

Removing the photoresist pattern and the anti-reflection film pattern;

And etching the gate material layer using the gate hard mask layer pattern as a mask to form a gate pattern.

The gate material layer is formed of a laminated structure of a polysilicon layer and a tungsten silicide layer,

The gate hard mask layer is formed of a nitride film,

The trimming process is performed at a pressure of 0.5 to 1.5 mT,

The trimming process is to proceed with a dry etching (Dry Etch) method,

The trimming process may be performed using any one selected from O 2, HBr, Ar, and a combination thereof.

The mixed gas is a ratio of O2: HBr: Ar is 1: 3 to 5: 6 to 8,

The mixed gas is that the ratio of O2: HBr: Ar is 1: 4: 7,

The method may further include forming a spacer on the sidewall of the gate pattern.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2E are cross-sectional views illustrating a gate pattern forming method of a semiconductor device according to the present invention.

Referring to FIG. 2A, a gate oxide layer 210, a gate polysilicon layer 220, a gate metal layer 230, a hard mask layer 240, a silicon oxynitride layer (SiON) 250, and a reflection may be formed on the semiconductor substrate 200. An organic bottom ARC (260) is sequentially formed.

Next, a photoresist layer (not shown) is formed on the resultant, and then a first photoresist layer pattern 270 defining a gate pattern is formed by performing an exposure and development process using a gate exposure mask.

Here, the line width of the first photoresist pattern 270 is defined as 'D1'.

In this case, the gate metal layer 230 may be formed of tungsten silicide (Wsix), and the hard mask layer 240 may be formed of any one of a nitride film, an amorphous carbon layer (a-Carbon), and a combination thereof.

2B and 2C, the anti-reflection film 260 is etched using the first photoresist pattern 270 as a mask to form a first anti-reflection film pattern 260a, and then a trimming process is performed on the resultant. The second photosensitive film pattern 270a having a line width of 'D2' smaller than the line width 'D1' of the first photosensitive film pattern 270 is formed.

The second photoresist pattern 270a and the second anti-reflection film pattern 260b having reduced line widths are formed.

Here, the trimming process refers to a technique of determining the line width of a desired fine pattern by reducing the line width of the photosensitive film through dry etching.

The trimming process is performed at a pressure of 0.5 to 1.5 mT to prevent excessive etching of the sidewalls of the first photoresist pattern 270, and an isotropic etching method using any one selected from O 2, HBr, Ar, and a combination thereof. It is preferable to proceed by performing.

At this time, the mixed gas is preferably prepared by mixing O2, HBr and Ar gas in a ratio of 0.5 to 1.5: 3 to 5: 6 to 8, more preferably in a ratio of 1: 4: 7: do.

Here, by forming the first anti-reflection film pattern 260a and performing the trimming process, the ID bias difference between the isolation pattern of the cell region and the dense pattern of the peripheral circuit region is reduced.

The ID bias refers to the critical dimension bias of the peripheral circuit region when the critical dimension of the cell region after the etching process using the etching mask is '0' bias.

Referring to FIG. 2D, the silicon oxynitride layer 250 and the hard mask layer 240 are etched using the second photoresist layer pattern 270a and the second anti-reflection layer pattern 260b having the line width reduced by the trimming process. The silicon oxynitride layer pattern 250a and the hard mask layer pattern 240a are formed.

Referring to FIG. 2E, the second photoresist layer pattern 270a, the second antireflection layer pattern 260b, and the silicon oxynitride layer pattern 250a are removed.

Next, the gate metal layer 230, the gate polysilicon layer 220, and the gate oxide layer 210 are sequentially etched using the hard mask layer pattern 240a as a mask to form the gate oxide layer pattern 210a and the gate polysilicon layer pattern ( 220a), a gate pattern 245 including a gate metal layer pattern 230a and a hard mask layer pattern 240a is formed.

Next, a gate spacer layer (not shown) is formed on the entire surface including the gate pattern 245, and the gate spacer 243 is formed on both sides of the gate pattern 245 by performing an entire surface etching process.

Here, since the line width of the gate pattern of the peripheral circuit area is reduced compared to the pattern of the cell area, the line width of the gate spacer 243 is formed to be relatively thicker than in the related art.

Therefore, the line width of the gate pattern is reduced when the channel is open, thereby improving the operation speed of the device and increasing the line width of the gate spacer when the channel is closed, thereby preventing tunneling. There is an advantage that the characteristics of the improved.

3A and 3B are SEM (Scanning Electron Microcopy) photographs showing the gate pattern cross-sectional profile before and after the trimming process is applied.

FIG. 3A illustrates a profile of a pattern before performing a trimming process. FIG. 3B illustrates a profile of a pattern after applying a trimming process to reduce the line width of the photoresist pattern. A pattern (Isolation Pattern) is shown, and (ii) shows a dense pattern of the peripheral circuit area.

Referring to FIGS. 3A and 3B and Table 1 below, the average value of the critical dimension of the hard mask layer pattern before the trimming process is 54 nm in the cell region, and 122 nm in the peripheral circuit region, and the ID bias difference is 68 nm. In comparison, the average value of the critical dimension of the hard mask layer pattern after the trimming process is 53 nm in the cell region, 110 nm in the peripheral circuit region, and 57 nm in the ID bias difference.

Figure 112006097914314-PAT00001

Therefore, it can be seen that the ID bias difference is reduced by performing the trimming process.

In the method of manufacturing a semiconductor device according to the present invention, an ID bias between a cell region and a peripheral circuit region is applied by applying a trimming process of isotropically etching the photoresist pattern by mixing O2, HBr and Ar gas with a low pressure of 1.5 mT or less of the photoresist pattern. Isolation / Dense Bias) is improved, the operation characteristics of the device are improved by reducing the line width of the gate pattern, and the thickness of the spacer is increased on both sides of the gate pattern, thereby preventing tunneling, thereby improving the device characteristics.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (9)

Forming a gate material layer, a gate hard mask layer, and an anti-reflection film over the semiconductor substrate; Forming a photoresist pattern on the anti-reflection film; Etching the anti-reflection film using the photoresist pattern as a mask to form an anti-reflection film pattern; Performing a trimming process on the resultant to reduce line widths of the photoresist pattern and the anti-reflection film pattern; Forming a gate hard mask layer pattern by etching the gate hard mask layer using the photoresist pattern and the anti-reflection film pattern having the reduced line width as a mask; Removing the photoresist pattern and the anti-reflection film pattern; And Etching the gate material layer using the gate hard mask layer pattern as a mask to form a gate pattern Method of manufacturing a semiconductor device comprising a. The method of claim 1, The gate material layer is a semiconductor device manufacturing method, characterized in that formed in a laminated structure of a polysilicon layer and a tungsten silicide layer. The method of claim 1, The gate hard mask layer is formed of any one of a nitride film, an amorphous carbon layer, a silicon oxynitride film and a combination thereof. The method of claim 1, The trimming process is a method of manufacturing a semiconductor device, characterized in that at a pressure of 0.5 to 1.5 mT. The method of claim 1, The trimming process is a manufacturing method of a semiconductor device, characterized in that the dry etching (Dry Etch) process. The method of claim 1, The trimming process is a semiconductor device manufacturing method characterized in that the progress using any one selected from O2, HBr, Ar and combinations thereof. The method of claim 6, The mixed gas is a method of manufacturing a semiconductor device, characterized in that the ratio of O2: HBr: Ar is 1: 3-5: 6-8. The method of claim 6, The mixed gas is a method of manufacturing a semiconductor device, characterized in that the ratio of O2: HBr: Ar is 1: 4: 7. The method of claim 1, And forming a spacer on the sidewalls of the gate pattern.
KR1020060137024A 2006-12-28 2006-12-28 Method for manufacturing semiconductor device KR20080061870A (en)

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