KR100877109B1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR100877109B1
KR100877109B1 KR1020070065862A KR20070065862A KR100877109B1 KR 100877109 B1 KR100877109 B1 KR 100877109B1 KR 1020070065862 A KR1020070065862 A KR 1020070065862A KR 20070065862 A KR20070065862 A KR 20070065862A KR 100877109 B1 KR100877109 B1 KR 100877109B1
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KR
South Korea
Prior art keywords
film
layer
hard mask
pattern
capping
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KR1020070065862A
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Korean (ko)
Inventor
이진열
Original Assignee
주식회사 하이닉스반도체
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/7607—Making of isolation regions between components between components manufactured in an active substrate comprising AIIBVI compounds

Abstract

A method of manufacturing a semiconductor device of the present invention includes forming a recess trench in a semiconductor substrate; Forming a gate insulating film, a conductive film, a barrier metal film, a metal film, and a hard mask film on the bulb type trench; Forming a photoresist pattern on the hard mask layer by applying and patterning the photoresist layer to partially block the hard mask layer; Etching the metal layer by a predetermined thickness while performing a first etching with the photoresist layer pattern as a mask to form a hard mask layer pattern; Depositing a first capping layer on the semiconductor substrate on which the first etching is performed; Forming a metal layer pattern and a barrier metal layer pattern by performing a second etching process using the first capping layer and the hard mask layer pattern as a mask; Depositing a second capping layer on the semiconductor substrate subjected to the second etching; And forming a gate stack by performing a third etching on the semiconductor substrate on which the second capping layer is formed.

Description

Method for manufacturing semiconductor device

1 to 10 are views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device.

Recently, as the degree of integration of semiconductor devices increases, the gate pattern is becoming more and more dense as the design rule rapidly decreases to 60 nm or less. Therefore, the hard mask film used as a mask for forming such a gate pattern also becomes thick. As the thickness of the hard mask film becomes thicker, the aspect ratio of the gate pattern increases, and the lining of the gate pattern inclined in one direction is different due to different thermal properties or different properties between materials. leaning phenomenon is occurring.

This lining phenomenon is mainly caused by different stress characteristics between the metal layer and the material forming the hard mask layer due to the heat applied to the gate pattern in the process of forming the capping layer on the gate pattern. That is, the stress difference between the two materials due to the thermal change is causing the lining phenomenon. In addition, when the capping film is formed on the gate pattern, the critical dimension of the metal film is reduced because the thickness of the capping film is included in the pattern critical dimension (CD), which leads to an increase in the gate resistance. As the gate pattern becomes dense, the problems of gate lining and gate resistance increase are inevitable.

As described above, the phenomenon in which the gate pattern is inclined may cause a contact defect not to be formed in a subsequent landing plug forming process or a bridge defect in which adjacent patterns are connected. Such a lining phenomenon and a bridge defect may cause self alignment contact (SAC) defects during pattern formation, thereby degrading semiconductor device characteristics.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device capable of improving a phenomenon in which a gate is tilted by relieving stress between a hard mask film and a metal film in advance.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device according to the present invention, forming a recess trench in a semiconductor substrate; Forming a gate insulating film, a conductive film, a barrier metal film, a metal film, and a hard mask film on the bulb type trench; Forming a photoresist pattern on the hard mask layer by applying and patterning the photoresist layer to partially block the hard mask layer; Etching the metal layer by a predetermined thickness while performing a first etching with the photoresist layer pattern as a mask to form a hard mask layer pattern; Depositing a first capping layer on the semiconductor substrate on which the first etching is performed; Forming a metal layer pattern and a barrier metal layer pattern by performing a second etching process using the first capping layer and the hard mask layer pattern as a mask; Depositing a second capping layer on the semiconductor substrate subjected to the second etching; And forming a gate stack by performing a third etching on the semiconductor substrate on which the second capping layer is formed.

In the present invention, the recess trench may be formed by including a bulb type trench including a sphere type trench at the bottom.

The photoresist layer pattern may be formed to have a value of 20 m to 30 m smaller than the critical dimension CD of the gate stack to be finally formed.

In the first etching, the metal film may be etched by a thickness of 30 ms to 40 ms.

The first capping film is preferably formed of a nitride film having a thickness of 20 kPa to 30 kPa.

The first capping layer is preferably deposited at a temperature of 710 ℃ to 730 ℃.

The second capping layer is preferably deposited at a lower temperature than the first capping layer.

The second capping film is preferably deposited at a temperature of 600 ℃ to 650 ℃.

The method may further include performing a selective oxidation process after forming the gate stack.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1 to 10 are views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a trench isolation layer 110 defining an active region is formed on a semiconductor substrate 100.

Specifically, the pad oxide film (not shown) and the pad nitride film (not shown) are sequentially deposited and then selectively removed to expose the device isolation region of the semiconductor substrate 100. Subsequently, the device isolation region of the exposed semiconductor substrate 100 is etched to form a trench 105 having a predetermined depth. The trench 105 is formed to have a depth of 2000-3000 mm from the surface of the semiconductor substrate 100. Next, an insulating film filling the trench 105 is formed, and after the planarization process is performed, the trench isolation film 110 is formed by removing the pad nitride film and the pad oxide film. Next, a threshold voltage screen oxide (Vt screen) 115 is formed on the surface of the active region to be used as a pad in the ion implantation process for adjusting the threshold voltage, and ion implantation is performed on the cell region and the peripheral circuit region. do.

Referring to FIG. 2, a hard mask layer 130 is deposited on the semiconductor substrate 100. The hard mask film 130 may be formed as a multilayer film in which at least one oxide film 120 and an amorphous carbon film 125 are stacked. The oxide film 120 is formed to a thickness of 200 kPa to 500 kPa, and the amorphous carbon film 125 is formed to a thickness of 1000 kPa to 2000 kPa. Subsequently, a photoresist film is applied and patterned on the hard mask film 130 to form a photoresist film pattern 135 exposing a portion of the surface of the hard mask film 130.

Referring to FIG. 3, an etching process is performed using the photoresist layer pattern 135 as a mask to form a hard mask layer pattern 145 that selectively exposes the surface of the semiconductor substrate 100. The hard mask layer pattern 145 has a structure in which an oxide layer pattern 140 and an amorphous carbon layer pattern 142 are stacked. The exposed region of the semiconductor substrate 100 is a region where a bulb type trench is to be formed later. The photoresist film pattern 135 is removed using a strip process.

Referring to FIG. 4, the semiconductor substrate 100 exposing the hard mask layer pattern 145 as a mask is etched to form a bulb type trench 160.

In detail, the first trench 150 is formed by performing first etching on the semiconductor substrate 100 exposed by the hard mask layer pattern 145. The first trench 150 corresponds to a neck portion of the bulb type trench. The first trench 150 is formed to an appropriate depth in consideration of the size of the bulb to be formed later.

Next, a second etching is performed on the semiconductor substrate 100 to form a second trench 155 having a sphere shape at the lower end of the first trench 150. Then, the bulb type trench 160 including the first trench 150 and the spherical second trench 155 is formed. The second trench 155 may be etched from the bottom surface of the first trench 150. The etching process of forming the spherical second trench 155 may be etched at the same speed in all directions to proceed to isotropic etching having a curved surface after etching. As described above, the bulb type trench 160 including the first trench 150 and the spherical second trench 155 is formed to have a depth of 1200 mm to 1800 mm. Afterwards, the cleaning process is performed to remove foreign substances and residual oxide film generated in the etching process.

Referring to FIG. 5, the gate insulating layer 165 is deposited on the semiconductor substrate 100 on which the bulb type trench 160 is formed. The gate insulating layer 165 may be formed to have a thickness of 30 to 60 Å including an oxide film. Next, a conductive film 170 is deposited on the gate insulating film 165. The conductive film 170 may be a doped polysilicon film having a thickness of 400 kPa to 700 kPa. Subsequently, a barrier metal film 175 and a metal film 180 are deposited on the conductive film 170. The barrier metal film 175 may form a tungsten nitride (WN) film with a thickness of 50 kPa to 300 kPa, and the metal film 180 may be formed of a tungsten (W) film with a thickness of 300 kPa to 600 kPa. The metal layer 180 is formed of a tungsten silicide (WSix) layer in the related art, but a tungsten (W) layer is applied as the metal layer 180 to improve the gate resistance. Next, a hard mask film 185 is formed on the metal film 180. The hard mask layer 185 may be formed to a thickness of 2000 GPa to 2500 GPa, and may be formed as a multilayer film in which at least one nitride film and an amorphous carbon film are deposited.

Next, a photoresist film pattern 190 is formed on the hard mask film 185 to partially block the hard mask film 185. The region blocked by the photoresist layer pattern 190 is a region where a gate pattern is to be formed later. In this case, the photoresist layer pattern 190 may be formed to have a value of 20 μs to 30 μs smaller than the critical dimension CD of the gate stack to be finally formed.

Referring to FIG. 6, the first mask is etched using the photoresist layer pattern 190 as a mask to form a hard mask layer pattern 195. Next, the photoresist film pattern 190 is removed using a strip process.

In the process of performing the first etching, the metal layer 180 is overetched by a part of thickness a, for example, 30 μs to 40 μs from the exposed surface. The hard mask layer pattern 195 and the metal layer 180 may be relaxed by over-etching the interface between the hard mask layer pattern 195 and the adjacent metal layer 180 by a thickness (a). release). The hard mask film pattern 195 formed by the first etching is formed to have a value of 20 μs to 30 μs smaller than the critical dimension CD of the conventional hard mask film pattern.

Referring to FIG. 7, the first capping layer 200 is deposited on the semiconductor substrate 100 on which the hard mask layer pattern 195 is formed. The first capping film 200 is deposited to a thickness of 20 kPa to 30 kPa with a nitride film at a deposition temperature of 710 ° C to 730 ° C. As such, the stress of the first capping layer 200 and the metal layer 180 is alleviated in the process of depositing the first capping layer 200 at a high temperature, and the metal layer 180 is formed in the entire film having a bulk shape. Stress relief can be achieved.

When the tungsten (W) film is applied as the gate metal film to improve the resistance characteristics of the gate, when the tungsten (W) film is exposed to the external atmosphere, the tungsten (W) film is abnormally oxidized or tungsten (W) during the oxidation process. Problems such as the generation of abnormal interfaces on the film may occur. Accordingly, when the gate pattern is covered with the capping film to block the tungsten (W) film from the external atmosphere, a high temperature, for example, a temperature of 650 ° C. or higher is applied to the gate pattern in the process of forming the capping film. W) A stress is generated between the films, causing a gate lining phenomenon. In addition, the thickness of the capping layer is included in the critical dimension CD of the gate pattern, thereby decreasing the critical dimension of the tungsten (W) film, which causes the gate resistance to increase.

In addition, when the tungsten nitride (WN) film and the tungsten film are used as electrodes, an insulating film in the form of a silicon nitride (Si x N y ) film is formed at the interface between the tungsten (W) film and the conductive film, and the ring oscillator ) May be delayed. In order to improve such a delay phenomenon, a barrier metal film having excellent delay phenomenon and excellent interfacial resistance is applied, but is formed in a complicated stack structure. As a result, the gate etch margin is quite insufficient, and various problems such as interlayer critical dimension variation are exposed, which can eventually cause the gate line to collapse more easily due to thermal stress in this weak gate profile state.

Accordingly, in the exemplary embodiment of the present invention, unlike etching the hard mask layer pattern to the conductive layer in the prior art and then depositing the capping layer, the first etching process of forming the hard mask layer pattern 195 is performed, followed by 710 ° C. to 730. The first capping layer 200 is covered at a high temperature of 占 폚 to mitigate stress between the hard mask layer pattern 195 and the metal layer 180 in advance.

Referring to FIG. 8, a second etching is performed using the first capping layer 200 and the hard mask layer pattern 195 as a mask to form the metal layer pattern 205 and the barrier metal layer pattern 215. In the process of performing the second etching, the conductive layer 170 may be etched by a part of thickness c from the exposed surface.

Next, a second capping layer 215 is deposited on the semiconductor substrate 100 subjected to the second etching. The second capping film 215 is deposited to a thickness of 50 kPa to 70 kPa with a nitride film at a deposition temperature lower than that of the first capping film 200, for example, at a temperature of 650 ° C. In this case, in the conventional case, a stress occurs between the hard mask layer pattern and the tungsten (W) layer in the process of forming the capping layer, thereby causing a gate lining phenomenon. However, in the exemplary embodiment of the present invention, in the process of forming the first capping layer 200, the stress is alleviated in the bulk state of the metal layer 180 (see FIG. 7) to form the second capping layer 215. No stress change occurs. Accordingly, the gate lining phenomenon caused by thermal stress can be prevented.

Referring to FIG. 9, the gate stack 230 is formed by performing a third etching process of etching the lower conductive layer 170 and the gate insulating layer 165 using the second capping layer 215 as a mask. The gate stack 230 overlaps the bulb type trench 160, and includes a gate insulating layer pattern 225, a conductive layer pattern 220, a barrier metal layer pattern 210, a metal layer pattern 205, and a hard mask. Film pattern 195. The hard mask layer pattern 195 may be covered by a double layer of the first capping layer 200 and the second capping layer 215, and may include a metal layer pattern 205, a barrier metal layer pattern 210, and a conductive layer pattern ( Some side surfaces of 220 are covered with a second capping film 215. Side surfaces of the conductive layer pattern 220 and the gate insulating layer pattern 225 that are not covered by the second capping layer 215 are exposed.

Referring to FIG. 10, a selective oxidation process is performed on the semiconductor substrate 100 on which the gate stack 230 is formed to expose the gate insulating layer pattern 225, the conductive layer pattern 220, and the semiconductor substrate. A silicon oxide film 235 is formed on the exposed surface of 100. The silicon oxide layer 235 cures the side surfaces of the gate insulating layer pattern and the conductive layer pattern damaged by the etching process.

In the method of manufacturing a semiconductor device having a bulb type recess channel according to the present invention, a hard mask layer pattern and a metal are formed by forming a hard mask layer pattern and then covering the hard mask layer pattern using a first capping layer deposited at a high temperature. Relieve stress in the membrane in advance. As a result, since the stress change does not occur during the deposition of the second capping layer at a temperature lower than the first capping layer after the gate pattern is formed, the gate lining phenomenon may be suppressed. In addition, it is possible to prevent the critical dimension of the hard mask film pattern from increasing by performing a subsequent process after etching by adjusting the critical dimension of the hard mask film pattern low.

As described so far, according to the method of manufacturing a semiconductor device according to the present invention, the capping film is formed as a double film to prevent the gate lining phenomenon due to thermal stress between the metal film and the hard mask film. By forming a high temperature primary capping film to relieve stress in advance, it is possible to suppress the stress generated when forming the secondary capping film.

Claims (10)

Forming a recess trench in the semiconductor substrate; Forming a gate insulating film, a conductive film, a barrier metal film, a metal film, and a hard mask film on the recess trenches; Forming a photoresist pattern on the hard mask layer by applying and patterning the photoresist layer to partially block the hard mask layer; Etching the metal layer by a predetermined thickness while performing a first etching with the photoresist layer pattern as a mask to form a hard mask layer pattern; Depositing a first capping layer on the semiconductor substrate on which the first etching is performed; Forming a metal layer pattern and a barrier metal layer pattern by performing a second etching process using the first capping layer and the hard mask layer pattern as a mask; Depositing a second capping layer on the semiconductor substrate subjected to the second etching; And And forming a gate stack by performing a third etching process on the semiconductor substrate on which the second capping layer is formed. The method of claim 1, The recess trench includes a bulb type trench including a spherical trench at the bottom thereof. The method of claim 1, The photoresist pattern is a semiconductor device manufacturing method, characterized in that formed to a value of 20 ~ 30 Å less than the critical dimension (CD) of the gate stack to be finally formed. The method of claim 1, The method of claim 1, wherein the metal layer is etched by a thickness of about 30 μs to about 40 μs. The method of claim 1, The first capping film is a semiconductor device manufacturing method, characterized in that formed as a nitride film. The method of claim 1, The first capping film is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 20 ~ 30Å. The method of claim 1, The first capping film is a method of manufacturing a semiconductor device, characterized in that for depositing at a temperature of 710 ℃ to 730 ℃. The method of claim 1, And the second capping layer is deposited at a lower temperature than the first capping layer. The method of claim 1, The second capping film is a method of manufacturing a semiconductor device, characterized in that for depositing at a temperature of 600 ℃ to 650 ℃. The method of claim 1, And performing a selective oxidation process after the forming of the gate stack.
KR1020070065862A 2007-06-29 2007-06-29 Method for manufacturing semiconductor device KR100877109B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101031471B1 (en) 2008-08-11 2011-04-26 주식회사 하이닉스반도체 semiconductor device and method for forming the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070066485A (en) * 2005-12-22 2007-06-27 주식회사 하이닉스반도체 Method for fabricating the same of semiconductor device with bulb recess gate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070066485A (en) * 2005-12-22 2007-06-27 주식회사 하이닉스반도체 Method for fabricating the same of semiconductor device with bulb recess gate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101031471B1 (en) 2008-08-11 2011-04-26 주식회사 하이닉스반도체 semiconductor device and method for forming the same

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