KR20080061781A

KR20080061781A - An electro-luminescence display device

Info

Publication number: KR20080061781A
Application number: KR1020060136872A
Authority: KR
Inventors: 박영주; 오두환
Original assignee: 엘지디스플레이 주식회사
Priority date: 2006-12-28
Filing date: 2006-12-28
Publication date: 2008-07-03

Abstract

An electro-luminescence display device is provided to reduce the number of output terminals of a data driver by supplying sequentially data signals to plural data lines through multiplexers. An electro-luminescence display device includes first, second, third, fourth, and fifth switching elements, a second source voltage line, and a capacitor(C). The first and second switching elements(Tr1,Tr2), which are controlled by a scan signal from gate lines, are connected between a data line and a first node. The third switching element(Tr3), which is controlled by the scan signal, is connected between first and second nodes. The fourth switching element(Tr4), which is controlled by a voltage of the first node, is connected between a first source voltage line for supplying a first voltage and the second node. The fifth switching element(Tr5), which is controlled by the voltage of the first node, is connected to the second node and an illumination element(OLED). The second source voltage line for supplying a second voltage is connected to the illumination element. The capacitor is connected between the first node and the first source voltage line.

Description

An electroluminescence display device

1 is a view showing a light emitting display device according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating first to third pixel cells connected to the first gate line and the first to third data lines of FIG. 1.

3 is a timing diagram illustrating scan signals, data signals, and selection signals supplied to the first to third pixel cells of FIG. 2.

* Explanation of symbols on the main parts of the drawings

DD: data driver GD: gate driver

101: selection unit PXL: pixel cell

GL: Gate Line DL: Data Line

SEL: Selection signal DO, SO: Output terminal

111: display unit

The present invention relates to a light emitting display device, and more particularly, to a light emitting display device capable of reducing the number of output terminals of a data driver and preventing a luminance difference between pixel cells.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include a liquid crystal display, a field emission display, a plasma display panel, and an electro-luminescence (hereinafter, referred to as "EL"). Display). The flat panel display may be divided into a voltage driver and a current driver.

An EL display device is a self-light emitting device that emits a fluorescent material by recombination of electrons and holes, and is classified into inorganic EL and organic EL depending on materials and structures. This EL display device has an advantage that the response speed is as fast as that of a cathode ray tube compared to a passive light emitting device requiring a separate light source like a liquid crystal display device. Such an EL display device has a current driving method and a voltage driving method.

The data driver provided in the conventional EL display device has a plurality of output terminals, and each output line is connected one-to-one to each data line. That is, the number of output terminals of the data driver matches the number of data lines.

As the EL display device becomes larger, the number of data lines increases, and as a result, the number of output terminals of the data driver increases. This causes a problem of increasing the cost of the data driver.

The present invention has been made to solve the above problems, the data signal is sequentially output through a single output terminal, and the data driver by sequentially supplying the output data signal to a plurality of data lines through a multiplexer It is an object of the present invention to provide a light emitting display device capable of reducing the number of output terminals.

A light emitting display device according to the present invention for achieving the above object, a plurality of data lines; A plurality of pixel cells connected to each of the data lines and commonly connected to one gate line; A data driver sequentially outputting data signals required for the pixel cells of each data line through one output line; A multiplexer configured to receive a data signal through the output line of the data driver, select one of the data lines according to a control signal from an external device, and supply a data signal from the data driver to the selected data line; To; Each pixel cell being controlled by a scan signal from said gate line, said first switching element being connected between a data line and a first node; A second switching element controlled by the scan signal from the gate line and connected between the data line and the first node; A third switching element controlled by the control signal and connected between the first node and a second node; A fourth switching element controlled according to the voltage of the first node and connected between the first power line to which the first voltage source is supplied and the second node; A fifth switching element controlled according to the voltage of the first node and connected between the second node and one end of the light emitting element; A second power source supplying a second voltage source and connected to the other end of the light emitting device; And a capacitor connected between the first node and the first power line.

Hereinafter, a light emitting display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a light emitting display device according to an embodiment of the present invention.

As shown in FIG. 1, a light emitting display device according to an exemplary embodiment of the present invention includes a display unit 111 including a plurality of pixel cells PXL, and pixel cells PXL formed on the display unit 111. And a gate driver GD and a data driver DD for driving.

Each pixel cell PXL is connected to each gate line GL1 to GLn and each data line DL1 to DLm.

In this case, each of the pixel cells PXL arranged along one pixel row is independently connected to each of the data lines DL1 to DLm and is commonly connected to one gate line.

For example, each of the pixel cells PXL included in the first pixel row is independently connected to the first to mth data lines DL1 to DLm and is commonly connected to the first gate line GL1. .

The data driver DD includes a plurality of output terminals DO1 to DOp, and each output terminal DO1 to DOp is connected to the selector 101. The data driver DD outputs a data signal through the output terminals DO1 to DOp. The data driver DD is a data driver DD of a current driving method. The data driver DD supplies a current to each of the data lines DL1 to DLm as a data signal or each of the data lines DL1 to. Sink current from DLm). The data driver DD includes a plurality of data drive ICs, and the output terminals of the data driver DD mean output terminals DO1 to DOp of the data drive ICs.

The selector 101 includes a plurality of output terminals SO1 to SOp, and each output terminal SO1 to SOp is commonly connected to a plurality of data lines. The selector 101 outputs a data signal through the output terminals SO1 to SOp. That is, the selector 101 selects one of a plurality of data lines connected to each output terminal SO1 to SOp according to selection signals SEL1 to SEL3 from the outside, and selects one of the plurality of data lines. Supply the data signal.

For example, the selector 101 may include a first data line of the first to third data lines DL1 to DL3 connected to the first output terminal SO1 according to the first selection signal SEL1. DL1) is selected to supply a data signal to the first data line DL1. The selector 101 may further include a second data line DL2 of the first to third data lines DL1 to DL3 connected to the first output terminal SO1 according to the second selection signal SEL2. Select to supply a data signal to the second data line DL2. The selector 101 may further include a third data line DL3 of the first to third data lines DL1 to DL3 connected to the first output terminal SO1 according to the third selection signal SEL3. ) Is supplied to supply the data signal to the third data line DL3.

At this time, since three pixel cells of the pixel cells PXL connected to one gate line are sequentially supplied with data signals from one output terminal, the one gate line is connected to the gate line when the gate line is driven. The pixel cells are driven in 1/3 horizontal periods.

For example, in the pixel cells PXL and fourth data lines DL4 connected to the first data line DL1 among the pixel cells PXL connected to the first gate line GL1 in a 1/3 period. The connected pixel cells PXL, ..., and pixel cells connected to the m-th data line DLm-2 simultaneously display an image. Thereafter, among the pixel cells PXL connected to the first gate line GL1 in a 2/3 period, the pixel cells PXL connected to the second data line DL2 and the fifth data line DL5 are connected. The pixel cells PXL connected to the pixel cells PXL, ..., m-th data line DLm-1 are driven simultaneously. Thereafter, among the pixel cells PXL connected to the first gate line GL1 in a 3/3 period, the pixel cells PXL connected to the third data line DL3 and the sixth data line DL6 are connected. The pixel cells PXL connected to the pixel cells PXL, ..., m-th data line DLm are simultaneously driven.

The gate lines GL1 to GLn are sequentially driven from the first gate line GL1 to the nth gate line GLn. To this end, the gate driver GD sequentially outputs the first scan signal to the nth scan signal, and sequentially outputs the first to nth scan signals to the first to nth gate lines GL1 to GLn. Supply in turn.

Herein, the configuration of each pixel cell PXL will be described in more detail.

Each pixel cell PXL includes a light emitting element OLED, first to fifth switching elements Tr1 to Tr5, a first power line 211 transmitting a first voltage VDD, and a second voltage VSS. It includes a second power line 212, and a capacitor (C) for transmitting. Here, the first to fifth switching devices Tr1 to Tr5 may be any type of N-type metal-oxide semiconductor (MOS) transistors or P-type metal-oxide semiconductor (MOS) transistors. 2 shows an example in which each of the first to fifth switching devices Tr1 to Tr5 is used as a P-type MOS transistor.

The first switching element Tr1 is controlled by the scan signal from the gate line and is connected to the corresponding data line and the first node n1.

For example, the gate terminal of the first switching element Tr1 included in the first pixel cell PXL1 is connected to the first gate line GL1, and the source terminal is connected to the first data line DL1. The drain terminal is connected to the first node n1 of the first pixel cell PXL1.

The second switching element Tr2 is controlled by the scan signal from the gate line and is connected between the data line and the first node n1.

For example, a gate terminal of the second switching element Tr2 provided in the first pixel cell PXL1 is connected to the first gate line GL1, and a source terminal is connected to the first node n1. The drain terminal is connected to the first data line DL1.

The third switching element Tr3 is controlled by any one of the selection signals SEL1 to SEL3, and is connected between the first node n1 and the second node n2.

For example, the gate terminal of the third switching element Tr3 of the first pixel cell PXL1 is connected to the first selection signal SEL1 line that transmits the first selection signal SEL1, and has a source. The terminal is connected to one node of the first pixel cell PXL1, and the drain terminal is connected to the second node n2 of the first pixel cell PXL1.

The fourth switching device Tr4 is controlled according to the voltage of the first node n1 and is connected between the first power line 211 and the second node n2.

For example, a gate terminal of the fourth switching element Tr4 of the first pixel cell PXL1 is connected to a first node n1 of the first pixel cell PXL1, and a source terminal of the fourth switching element Tr4 is connected to the first node n1 of the first pixel cell PXL1. The first power line 211 is connected, and the drain terminal is connected to the second node n2 of the first pixel cell PXL1.

The fifth switching device Tr5 is controlled according to the voltage of the first node n1 and is connected to the second node n2 and the anode of the light emitting device OLED.

For example, the gate terminal of the fifth switching device Tr5 of the first pixel cell PXL1 is connected to the first node n1 of the first pixel cell PXL1, and the source terminal of the fifth pixel PXL1 is connected to the first node n1 of the first pixel cell PXL1. It is connected to the first node n1 of one pixel cell PXL1, and the drain terminal is connected to the anode of the light emitting element OLED provided in the first pixel cell PXL1.

The second power line 212 is connected to the cathode of the light emitting device OLED. A ground terminal may be connected to the cathode of the light emitting device OLED instead of the second power line 212.

The capacitor C is connected between the first node n1 and the first power line 211.

The first to third pixel cells PXL1 to PXL3 are pixel cells that receive data signals from the first to third data lines DL1 to DL3 commonly connected to the first output terminal SO1. The first to third pixel cells PXL1 to PXL3 have the above-described circuit configuration.

However, the third switching device Tr3 provided in the first pixel cell PXL1 is controlled by the first selection signal SEL1 and the third switching device Tr3 provided in the second pixel cell PXL2. Is controlled by the second select signal SEL2, and the third switching element Tr3 included in the third pixel cell PXL3 is controlled by the third select signal SEL3.

Meanwhile, the selector 101 includes a plurality of multiplexers. In FIG. 2, the selector 101 supplies a data signal from the first output terminal SO1 to one of the first to third data lines DL1 to DL3. One multiplexer is shown.

The multiplexer MUX includes a plurality of output selection switching elements Tr1 to Tr3 for selecting any one of a plurality of data lines connected to one output terminal according to each of the selection signals SEL1 to SEL3. .

For example, the multiplexer MUX illustrated in FIG. 2 may include a first output selection switching element connecting the first output terminal SO1 and the first data line DL1 according to the first selection signal SEL1. A second output selection switching element TrS2 for connecting between the first output terminal SO1 and the second data line DL2 according to TrS1, the second selection signal SEL2, and a third selection signal ( And a third output selection switching element TrS3 for connecting the first output terminal SO1 and the third data line DL3 according to SEL3.

The operation of the first to third pixel cells PXL1 to PXL3 configured as described above is as follows.

First, the operation of the first period T1 will be described.

In the first period T1, as shown in FIG. 3, the scan signal Vout and the first selection signal SEL1 are kept low, and the remaining selection signals SEL2 and SEL3 are kept high. . In addition, the first data signal D1 is supplied to the first output terminal SO1 in the first period T1. This first data signal D1 is a data signal required for the first pixel cell PXL1.

The scan signal Vout is supplied to the first gate line GL1. The scan signal Vout supplied to the first gate line GL1 is supplied to the first and second switching devices Tr1 and Tr2 provided in the first pixel cell PXL1. That is, it is supplied to each gate terminal of the first and second switching elements Tr1 and Tr2.

The first selection signal SEL1 is supplied to the third switching element Tr3 of the first pixel cell PXL1 and the first output selection switching element TrS1 of the multiplexer MUX. That is, the gate terminal of the third switching element Tr3 and the gate terminal of the first output selection switching element TrS1 are supplied.

Then, the first to third switching elements Tr1 to Tr3 and the first output selection switching element TrS1 are turned on.

As the first output selection switching element TrS1 is turned on, the first output terminal SO1 and the first data line DL1 are connected to each other. Accordingly, the first data signal D1 is supplied to the first data line DL1.

As the first to third switching devices Tr1 to Tr3 are turned on, the first data line DL1 and the first and second nodes n1 and n2 are connected to each other. Accordingly, the first and second nodes n1 and n2 are charged with the voltage according to the first data signal.

Accordingly, the capacitor C of the first pixel cell PXL1 is charged with a difference voltage according to the voltage and the first voltage VDD (hereinafter referred to as 'first driving voltage').

Here, as the third switching device Tr3 is turned on, the fourth switching device Tr4 and the fifth switching device Tr5 are connected to each other in the form of a diode in a reverse direction. Accordingly, a current cannot be supplied to the light emitting device OLED of the first pixel cell PXL1. Therefore, the light emitting element OLED of the first pixel cell PXL1 does not emit light in the first period T1.

On the other hand, since the second and third output selection switching elements TrS2 and TrS3 are turned off in the first period T1, first data is stored in the second and third pixel cells PXL2 and PXL3. The signal D1 is not supplied.

As described above, the first driving voltage is charged in the capacitor C of the first pixel cell PXL1 in the first period T1. In this case, since the first driving voltage is determined by the first data signal D1 regardless of the threshold voltage of the fourth switching device Tr4, the first driving voltage is determined by the fourth switching device Tr4. It is not affected by the characteristics.

Next, the operation during the second period T2 will be described.

In the second period T2, as shown in FIG. 3, the scan signal Vout and the second select signal SEL2 are kept low, and the remaining select signals SEL1 and SEL3 are kept high. . In addition, the second data signal D2 is supplied to the first output terminal SO1 in the second period T2. This second data signal D2 is a data signal required for the second pixel cell PXL2.

In the second period T2, as the second output selection switching device TrS2, which receives the second selection signal SEL2 in the low state, is turned on, the second pixel cell PXL2 receives second data. The signal D2 is supplied.

Therefore, in the second period T2, the second pixel cell PXL2 stores the second driving voltage according to the second data signal D2 in the capacitor C. FIG.

Meanwhile, as the first selection signal SEL1 remains high in the second period T2, the third switching device Tr3 of the first pixel cell PXL1 supplied with the first selection signal SEL1 is turned on. Is off. Accordingly, the fourth switching device Tr4 and the fifth switching device Tr5 included in the first pixel cell PXL1 are connected in a forward diode form. Then, a current path is formed between the fourth switching element Tr4 and the fifth switching element Tr5 included in the first pixel cell PXL1, and the light emission of the first pixel cell PXL1 is generated through the current path. The first driving current is supplied to the element OLED. The first driving current is a current generated according to the first driving voltage stored in the capacitor C of the first pixel cell PXL1.

Therefore, in the second period T2, the light emitting device OLED of the first pixel cell PXL1 emits light according to the first driving current.

Subsequently, in the third period T3, as illustrated in FIG. 3, the scan signal Vout and the third select signal SEL3 remain low, and the remaining select signals SEL1 and SEL2 remain high. maintain. In addition, the third data signal D3 is supplied to the first output terminal SO1 in the third period T3. This third data signal D3 is a data signal required for the third pixel cell PXL3.

In the third period T3, as the third output selection switching device TrS3, which is supplied with the third selection signal SEL3 in the low state, is turned on, the third pixel cell PXL3 receives the third data. The signal D3 is supplied.

Accordingly, in the third period T3, the third pixel cell PXL3 stores the third driving voltage according to the third data signal D3 in the capacitor C. FIG.

On the other hand, as the second selection signal SEL2 remains high in the third period T3, the third switching device Tr3 provided in the second pixel cell PXL2 supplied with the second selection signal SEL2 is turned on. Is off. Accordingly, the fourth switching device Tr4 and the fifth switching device Tr5 included in the second pixel cell PXL2 are connected in a forward diode form. Then, a current path is formed between the fourth switching element Tr4 and the fifth switching element Tr5 included in the second pixel cell PXL2, and the light emission of the second pixel cell PXL2 is generated through the current path. The second driving current is supplied to the device OLED. The second driving current is a current generated according to the second driving voltage stored in the capacitor C of the second pixel cell PXL2.

Therefore, in the third period T3, the light emitting device OLED of the second pixel cell PXL2 emits light according to the second driving current.

In this manner, the light emitting element OLED provided in the third pixel cell PXL3 emits light in the fourth period (not shown).

As described above, in the present invention, the data signals are sequentially output through one output terminal, and the output data signals are sequentially supplied to the plurality of data lines through the multiplexer MUX to output terminals DO1 to DD of the data driver DD. The number of DOp) can be reduced.

For example, in the present invention, since three data lines are connected to one output terminal, the number of output terminals DO1 to DOp can be reduced to 1/3 by applying the structure according to the present invention.

In addition, since the driving voltage is determined by the data signal irrespective of the threshold voltage of the fourth switching device Tr4, the driving voltage is not affected by the characteristics of the fourth switching device Tr4. Therefore, the luminance difference does not occur according to the characteristics of the fourth switching elements Tr4 provided between the pixel cells.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The light emitting display device according to the present invention as described above has the following advantages.

First, the number of output terminals of the data driver may be reduced by sequentially outputting data signals through one output terminal and sequentially supplying the output data signals to a plurality of data lines through a multiplexer.

Second, since the driving voltage source is determined by the first data signal irrespective of the threshold voltage of the fourth switching device, the driving voltage source is not affected by the characteristics of the fourth switching device. Therefore, the luminance difference does not occur according to the characteristics of each of the fourth switching elements provided between the pixel cells.

Claims

Multiple data lines;

A plurality of pixel cells connected to each of the data lines and commonly connected to one gate line;

A data driver sequentially outputting data signals required for the pixel cells of each data line through one output terminal;

A multiplexer configured to receive a data signal through the output terminal of the data driver, select one of the data lines according to a control signal from an external device, and supply a data signal from the data driver to the selected data line; ;

Each pixel cell

A first switching element controlled by a scan signal from the gate line and connected between the data line and the first node;

A second switching element controlled by the scan signal from the gate line and connected between the data line and the first node;

A third switching element controlled by the control signal and connected between the first node and a second node;

A fourth switching element controlled according to the voltage of the first node and connected between the first power line to which the first voltage source is supplied and the second node;

A fifth switching element controlled according to the voltage of the first node and connected between the second node and one end of the light emitting element;

A second power source supplying a second voltage source and connected to the other end of the light emitting device; And,

And a capacitor connected between the first node and the first power line.

The method of claim 1,

The control signal includes a plurality of selection signals having different phase differences;

The third switching device provided in each pixel cell is controlled by different selection signals.

The method of claim 2,

The multiplexer includes a plurality of output selection switching elements corresponding to the number of the selection signals;

Each output selection switching element is controlled by a different selection signal and is connected between any one of the data lines and the output terminal.

The method of claim 2,

And a scan signal supplied to the gate line remains active during each active period of the selection signals.

The method of claim 1,

And the second voltage source is a ground voltage source.