KR20080061547A - Plane display panel and method for fabricating thereof - Google Patents

Abstract

A flat display panel and a method for fabricating the same are provided to increase contact reliability between a pad unit and a signal line by forming an additional dummy electrode in contact with the signal line in the pad unit. A flat display panel(100) includes a gate pad unit(180), a data pad unit(190), and a protection film. The gate pad unit is connected to a gate line(110). The data pad unit is connected to a data line(130). The protection film has an open hole for opening the gate pad unit and the data pad unit. The protection film covers a partial area of each pad unit exposed by the open hole. The flat display panel displays an image through light emitted from an organic light emitting layer.

Description

Flat display panel and method for fabricating thereof

1 is a plan view of a conventional flat panel display panel.

FIG. 2 is a cross-sectional view of the flat panel display panel illustrated in FIG. 1. FIG.

3 is a plan view of a flat panel display panel according to the present invention;

4 is a cross-sectional view of a flat panel display panel according to the present invention;

5 is a view showing a configuration of an organic light emitting layer formed in a light emitting area according to the present invention.

6A to 6H are diagrams illustrating a manufacturing process of a flat panel display panel according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100: flat panel display panel 102: substrate

104: buffer layer 106: active layer

108: gate insulating film 110: gate line

112 gate electrode 120 interlayer insulating film

122: first contact hole 124: second contact hole

126: third contact hole 128: fourth contact hole

129: fifth contact hole 130: data line

132: source electrode 134: drain electrode

140: first electrode 150: protective film

152: first open hole 154: second open hole

156: third open hole 160: organic light emitting layer

T: thin film transistor 170: second electrode

180: gate pad portion 182: gate pad lower electrode

184: gate pad dummy electrode 186: gate pad upper electrode

190: data pad part 192: data pad lower electrode

194: Data pad dummy electrode 196: Data pad upper electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display panel and a method of manufacturing the same, and more particularly, to a flat panel display panel having a high contact reliability between a signal line and a pad portion and a method of manufacturing the same.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (FEDs), plasma display panels (hereinafter referred to as PDPs), and electric fields. And an EL-Electro-luminescence Display Device using a light emitting device ("Electro-luminescence Device" (hereinafter referred to as "EL element")). Studies are being actively conducted to increase and to screen large screens.

Among them, PDP is attracting attention as a display device which is light and small and is most advantageous for large screen because of its simple structure and manufacturing process. However, PDP has low luminous efficiency, low luminance and high power consumption. On the other hand, an active matrix LCD having a thin film transistor (hereinafter referred to as a TFT) as a switching element has a disadvantage in that it is difficult to large screen due to the semiconductor process and consumes a lot of power due to the backlight unit. , Optical prism sheet, diffusion plate, etc. are characterized by high optical loss and narrow viewing angle.

In contrast, the EL display device is classified into an inorganic EL display device and an organic EL display device according to the material of the light emitting layer. The EL display device is a self-luminous device that emits light by itself, and has a high response speed and high luminous efficiency, luminance, and viewing angle. Inorganic EL display devices have higher power consumption and higher luminance than organic EL display devices, and cannot emit various colors of R, G, and B. On the other hand, the organic EL device is driven at a low DC voltage of several tens of volts, has a fast response speed, obtains high brightness, and emits various colors of R, G, and B, which is suitable for next-generation flat panel display devices.

The method of driving such an organic EL display device may be classified into a passive matrix type and an active matrix type.

The passive matrix type organic EL display device has a simple structure and a simple manufacturing method. However, the passive matrix type organic EL display device has a high power consumption and a large area of the display device, and the opening ratio decreases as the number of wires increases.

On the other hand, an active matrix organic EL display device has an advantage of providing high luminous efficiency and high image quality.

Hereinafter, the structure of a conventional flat panel display panel will be described with reference to FIGS. 1 and 2.

As shown in FIG. 1 and FIG. 2, the conventional flat panel display panel is formed in the buffer layer 4 on the substrate 2 to form an active layer 6 and a gate insulating film 8 covering the active layer 6. The thin film transistor T formed in an intersection region of the two lines 10 and 30 and the data line 30 intersecting the gate line 10 with the gate line 10 formed thereon and the interlayer insulating layer 20 therebetween. ), The first electrode 40 formed on the interlayer insulating film 20 and connected to the thin film transistor T, and the first electrode 40 on the passivation layer 50 covering the thin film transistor T. The organic light emitting layer 60 and the second organic light emitting layer 60 are formed to overlap each other, and include a second electrode 70 that forms a potential for emitting the organic light emitting layer 60 together with the first electrode 40. It is configured by.

Here, the conventional flat panel display panel further includes a gate pad 80 connected to the gate line and a data pad 90 connected to the data line 30 as shown in FIGS. 3 and 4.

In this case, the gate pad 80 is connected to the gate pad lower electrode 82 through the gate pad lower electrode 82 connected to the gate line 10 and the contact hole 26 penetrating through the interlayer insulating layer 20. The pad upper electrode 86 is configured.

In addition, the data pad 90 is connected to the data pad lower electrode 92 through the data pad lower electrode 92 connected to the data line 30 and the contact hole 28 penetrating through the interlayer insulating layer 20. The pad upper electrode 96 is configured.

In the case of the conventional flat panel display panel configured as described above, corrosion is generated as the gate and the data pad upper electrodes 86 and 96 constituting the pad portions 80 and 90 are all exposed. There was a problem that the contact reliability of each pad portion 80,90 and an external circuit was lowered.

In addition, when the gate and data pad upper electrodes 86 and 96 constituting the pad portions 80 and 90 are damaged by an external shock, the gate and data lines 10 and 30 and the pad portions 80 and 90 are damaged. There was also a problem that a poor contact occurred.

Accordingly, an object of the present invention is to provide a flat panel display panel and a method of manufacturing the same, by which a portion of the pad portion connected to the signal line is covered with a protective film, thereby preventing corrosion of the pad portion and increasing connection reliability with the signal line. There is.

In addition, an object of the present invention is to provide a flat panel display panel having a high contact reliability between a pad part and a signal line by forming a separate dummy electrode in contact with the signal line on the pad part, and a manufacturing method thereof.

In order to achieve the above object, a flat panel display panel for displaying an image through the light emitted from the organic light emitting layer according to the present invention, comprising: a gate pad portion connected to the gate line; A data pad section connected to a data line; And a protective film having an open hole for opening the gate pad part and the data pad part, wherein the protective film is formed to cover a portion of each pad part exposed to the outside by the open hole.

The gate pad unit according to the present invention includes a gate pad lower electrode connected to a gate line; An interlayer insulating layer having a contact hole exposing the gate pad lower electrode; A gate pad dummy electrode formed on the interlayer insulating layer to be spaced apart from each other with a contact hole interposed therebetween; And a gate pad upper electrode connected to the gate pad lower electrode through the contact hole.

The gate pad upper electrode according to the present invention is formed to partially overlap the gate pad dummy electrode.

The gate pad upper electrode according to the present invention is formed so that a part of the upper electrode is covered by the passivation layer.

The data pad unit according to the present invention includes: a data pad lower electrode connected to a data line intersecting a gate line via a gate insulating layer; An interlayer insulating layer having contact holes exposing the data pad lower electrodes; A data pad dummy electrode formed on the interlayer insulating layer to be spaced apart from each other with a contact hole interposed therebetween; And a data pad upper electrode connected to the data pad lower electrode through the contact hole.

The data pad dummy electrode according to the present invention is characterized in that it is electrically connected to the data line.

The data pad upper electrode according to the present invention is formed to partially overlap the data pad dummy electrode.

The data pad upper electrode according to the present invention is formed so that a part of the upper electrode is covered by the passivation layer.

A method of manufacturing a flat panel display panel for displaying an image through light emitted from an organic light emitting layer, the method comprising: forming a gate pad portion connected to a gate line and a data pad portion connected to a data line; And forming a protective film having an open hole for exposing the gate pad part and the data pad part, wherein the protective film is formed to cover a portion of each pad part exposed to the outside by the open hole. .

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, a flat panel display panel and a manufacturing method thereof according to the present invention will be described with reference to the accompanying drawings.

First, a configuration of a flat panel display panel according to the present invention will be described in detail with reference to FIGS. 3 and 4.

According to an exemplary embodiment of the present invention, a flat panel display panel displays a screen using a property in which an organic light emitting layer made of organic material emits light by an applied voltage. As shown in FIGS. A gate line 110 and an interlayer insulating layer 120 formed on the active layer 106 and the gate insulating layer 108 covering the active layer 106 and intersecting the gate line 110. The thin film transistor T formed at the intersection of the data line 130, the two lines 110 and 130, the first electrode 140 formed on the interlayer insulating layer 120 and connected to the thin film transistor T, and the thin film. The organic light emitting layer 160 formed on the passivation layer 150 covering the transistor T in a form overlapping with the first electrode 140, and the organic light emitting layer 160 overlapping the first electrode 140, is formed. And a second to form a potential for emitting the organic light emitting layer 160 together. It is configured to include an electrode 170.

The flat panel display panel according to the present invention further includes a gate pad 180 connected to the gate line 110 and a data pad 190 connected to the data line 130.

The active layer 106 forms a channel between the source electrode 132 and the drain electrode 134 of the thin film transistor T. The active layer 106 is formed of polysilicon on the buffer film 104 formed entirely on the substrate 102. do.

Here, the active layer 106 is a full-deposited a-Si layer having a thickness of 200 ~ 2000 A ^{O on} the buffer film 104 by a deposition method such as PECVD, and then laser annealing or solid phase to the a-Si layer It is composed of polysilicon formed through SPC (solid phase crystallization) process.

The gate line 110 is formed on the gate insulating layer 108 covering the active layer 106, and the gate electrode 112 constituting the thin film transistor T receives a gate signal supplied from a gate driver connected to the gate pad 180. ).

Here, the gate line 110 is formed of a gate metal composed of aluminum (Al) -based metal, copper (Cu), chromium (Cr), molybdenum (Mo), or the like.

The data line 130 crosses the gate line 110 with the interlayer insulating layer 120 interposed therebetween, and is supplied from a data driver connected to the data pad 190 in association with the on / off of the gate electrode 112. The data signal is transferred to the source electrode 132 and the drain electrode 134 of the thin film transistor T.

The thin film transistor T serves to transfer the data signal of the data line 130 to the first electrode 140 in response to the gate signal of the gate line 110. The thin film transistor T is provided through the gate insulating layer 108. The source electrode 132 connected to the active layer 106 through the gate electrode 112 formed to overlap the 106 and the first contact hole 122 penetrating through the interlayer insulating film 120 and the gate insulating film 108. And a drain electrode 134 connected to the active layer 106 and simultaneously to the first electrode 140 through the second contact hole 124 passing through the interlayer insulating film 120 and the gate insulating film 108. do.

The first electrode 140 serves to form a potential for emitting the organic light emitting layer 106. The first electrode 140 is connected to the active layer 106 through the second contact hole 124 on the interlayer insulating layer 120. 134 and some overlapping form.

The passivation layer 150 is formed in a mesh shape to cover the thin film transistor T and expose the first electrode 140 formed in the emission region.

The protective layer 150 may include a first open hole 152 that exposes the first electrode 140 formed in the emission region, a second open hole 154 that opens the gate pad 180, and a data pad that opens the data pad. Three open holes 156 are formed.

In this case, in order to prevent a decrease in contact reliability with the gate line due to corrosion generated as the gate pad 180 is exposed through the second open hole 154, the passivation layer 150 may be a partial region of the gate pad 180. It is formed in the form of covering.

The organic emission layer 160 is formed to overlap the first electrode 140 formed in the emission region, and serves to emit light in association with a potential formed between the first and second electrodes 140 and 170. .

The second electrode 170 is entirely deposited on the passivation layer 150 while being overlapped with the organic light emitting layer 160 to form a potential for emitting the organic light emitting layer 160 together with the first electrode 140. .

That is, when a potential is formed between the first and second electrodes 140 and 170 formed with the organic emission layer 160 interposed therebetween, as illustrated in FIG. 5, holes generated from the first electrode 140 are formed. Is moved toward the light emitting layer 160c through the hole injection layer 160e and the hole transport layer 160d, and electrons generated from the second electrode 170 pass through the electron injection layer 160a and the electron transport layer 160b. 160c),

Accordingly, in the light emitting layer 160c, light is generated by collision and recombination of electrons and holes supplied from the electron transporting layer 160b and the hole transporting layer 160d, and the light is emitted to the outside through the second electrode 170. The image is displayed.

The gate pad 180 has a gate pad lower electrode 182 extending from the gate line 110 on the gate insulating layer 108 and a third contact hole 126 penetrating through the interlayer insulating layer 120. The gate pad upper electrode 186 which is connected to the gate pad lower electrode 182 through the formed gate pad dummy electrode 184 and the third contact hole 126 and partially overlaps the gate pad dummy electrode 184. It is configured to include).

In this case, the gate pad upper electrode 186 is connected to the gate pad lower electrode 182 through various contact paths, for example, the third contact hole 126, and is formed to partially overlap the gate pad dummy electrode 184. Accordingly, the contact reliability between the gate line 110 and the gate pad 180 is greatly improved.

Here, the gate pad lower electrode 182 constituting the gate pad 180 is made of a gate metal, the gate pad dummy electrode 184 is formed of a transparent conductive material (ITO), and the gate pad upper electrode 186 is formed of data. It is composed of metal.

The data pad 190 includes a data pad lower electrode 192 formed on the gate insulating layer 108 and a data pad dummy electrode 194 having a fourth contact hole 128 penetrating through the interlayer insulating layer 120. And the data pad upper electrode 196 connected to the data pad lower electrode 192 through the fourth contact hole 124 and partially overlapped with the data pad dummy electrode 194.

Here, the data pad lower electrode 192 constituting the data pad 190 is made of a gate metal, the data pad dummy electrode 194 is formed of a transparent conductive material (ITO), and the data pad upper electrode 196 is formed of data. It is composed of metal.

In this case, the data pad lower electrode 192 is connected to the data line 130 through the fifth contact hole 129 penetrating the interlayer insulating layer 120, and the data pad dummy electrode 194 is connected to the data line 130. It is also connected in some nested form.

As described above, as the data pad 190 is connected to the data line 130 through various contact paths, contact reliability between the data line 130 and the data pad 190 is greatly improved.

Hereinafter, a method of manufacturing a flat panel display panel according to the present invention will be described in detail with reference to FIGS. 6A to 6H.

First, an active layer 106 for forming a channel is formed on the buffer layer 104 on the substrate 102 through the first mask process according to the present invention.

In more detail, after forming the polysilicon layer on the buffer layer 104 formed on the substrate 102, a photoresist pattern exposing the polysilicon is formed through a photolithography process using a first mask.

Thereafter, by etching the polysilicon layer exposed by the photoresist pattern, as shown in FIG. 6A, an active layer 106 is formed over the buffer layer 104 formed on the substrate 102.

After the active layer is formed as described above, the gate electrode 112, the gate pad lower electrode 182, and the data pad lower electrode 192 are connected to the gate line 110 through the second mask process according to the present invention. A first conductive pattern is formed.

In more detail, after depositing the gate insulating film 108 on the substrate 102 on which the active layer 106 is formed, the gate metal layer is entirely deposited on the gate insulating film 108 through a deposition process such as PECVD. Let's do it.

In this case, a photoresist pattern is formed by exposing the entire surface of the photoresist on the gate metal layer and then performing a photolithography process using a second mask to expose the gate metal layer.

  Thereafter, by etching the gate metal layer exposed by the photoresist pattern, as shown in FIG. 6B, the gate electrode 110 connected to the gate line 110 and the gate line 110 on the gate insulating film 108 and A first conductive pattern including the gate pad lower electrode 182 and the data pad lower electrode 192 is formed.

After the first conductive pattern is formed as described above, the first electrode 140, the gate pad dummy electrode 184, and the data pad dummy electrode connected to the thin film transistor T through the third mask process according to the present invention. A second conductive pattern composed of 194 is formed.

More specifically, after the entire surface of the interlayer insulating film 120 is deposited on the substrate 102 on which the first conductive pattern is formed, the entire surface of the transparent conductive layer is deposited on the interlayer insulating film 120 through a deposition process such as sputtering. Deposit.

Thereafter, after the photoresist is entirely deposited on the transparent conductive layer, a photoresist pattern using a third mask is performed to form a photoresist pattern exposing the transparent conductive layer.

At this time, by etching the transparent conductive layer exposed by the photoresist pattern, as shown in Figure 6c, the first electrode 140, which is connected to the thin film transistor (T) and positioned in the light emitting region, the gate constituting each pad A second conductive pattern including the pad dummy electrode 184 and the data pad dummy electrode 194 is formed.

In this case, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) may be used as the transparent conductive layer constituting the first electrode 140.

The gate pad dummy electrode 184 is partially overlapped with the gate pad upper electrode 186 formed by a mask process to be described later, thereby contacting the gate pad lower electrode 182 and the upper electrode 186. It plays a role of increasing reliability.

The data pad dummy electrode 194 is partially overlapped with the data pad upper electrode 196 formed by a mask process to be described later, thereby contacting the data pad lower electrode 192 and the upper electrode 196. It plays a role of increasing reliability.

After forming the second conductive pattern as described above, a contact hole exposing the active layer 106, the gate pad lower electrode 182, and the data pad lower electrode 192 is formed through a fourth mask process according to the present invention. Form.

In more detail, the photoresist pattern exposing the entire photoresist on the interlayer insulating layer 120 on which the second conductive pattern is formed, and then exposing the interlayer insulating layer 120 through a photolithography process using a fourth mask. To form.

Thereafter, etching is performed on the interlayer insulating film 120 exposed by the photoresist pattern, the dummy electrodes 184 and 194 and the gate insulating film 108 formed in each pad portion, as shown in FIG. 6D. First to fifth contact holes 122, 124, 126, 128, and 129 are formed on the 120.

Here, the first contact hole 122 penetrates the interlayer insulating film 120 and the gate insulating film 108 to expose the source region of the active layer 106, and the second contact hole 124 is the interlayer insulating film 120 and the gate. The drain region of the active layer 106 is exposed through the insulating layer 108, and the third contact hole 126 penetrates the gate pad dummy electrode 184 and the interlayer insulating layer 120 to open the gate pad lower electrode 182. The fourth contact hole 128 exposes the data pad lower electrode 192 through the data pad dummy electrode 194 and the interlayer insulating layer 120, and the fifth contact hole 129 has the interlayer insulating layer 120. ) Exposes the data pad lower electrode 192 connected to the data line 130.

As described above, after the first to fifth contact holes are formed, the data line 130, the source electrode 132, the drain electrode 134, and the gate pad upper electrode 186 are formed through a fifth mask process according to the present invention. ) And a data pad upper electrode 196 is formed.

In more detail, the data metal layer is entirely deposited on the interlayer insulating layer 120 having the first to fifth contact holes through a deposition process such as PECVD.

At this time, the photoresist is deposited on the data metal layer and then the photolithography process using the fifth mask is performed to form a photoresist pattern exposing the data metal layer.

 Thereafter, by etching the data metal layer exposed by the photoresist pattern, as shown in FIG. 6E, the data line 130, the source electrode 132 and the gate electrode 112 connected to the data line 130 are removed. A drain electrode 134 facing the source electrode 132, a gate pad upper electrode 186 connected to the gate pad lower electrode 182, and a data pad upper electrode connected to the data pad lower electrode 192 between the drain electrode 134 and the data pad lower electrode 192. A third conductive pattern composed of 196 is formed.

Here, the data line 130 is connected to the data pad lower electrode 182 through the fifth contact hole 129 as shown in region A, and at the same time, the data pad upper electrode 196 through the data pad dummy electrode 194. ) Is also connected.

That is, as the data line 130 and the data pad 190 are connected through various contact paths as described above, the contact reliability between the data line 130 and the data pad 190 is greatly improved.

The source electrode 132 is connected to the source region of the active layer 106 through the first contact hole 122 penetrating through the interlayer insulating layer 120 and the gate insulating layer 108.

The drain electrode 134 is connected to the drain region of the active layer 106 through the second contact hole 124 penetrating the interlayer insulating film 120 and the gate insulating film 108, and partially overlaps the first electrode 140. Connected in the form.

The gate pad upper electrode 186 is connected to the gate pad lower electrode 192 through the third contact hole 126 and is also partially overlapped with the gate pad dummy electrode 184.

That is, as the gate pad upper electrode 186 contacts the gate pad lower electrode 182 through various contact paths, the contact reliability between the gate line 110 and the gate pad 180 is greatly improved.

The data pad upper electrode 196 is connected to the data pad lower electrode 192 through the fourth contact hole 128 and partially overlaps the data pad dummy electrode 194 connected to the data line 130. Connected.

That is, as the data pad upper electrode 196 contacts the data pad lower electrode 192 and the data line 130 through various contact paths, the contact reliability between the data line 130 and the data pad 190 is greatly increased. Is improved.

After the third conductive layer is formed as described above, the passivation layer 150 having the first electrodes and the first to third open holes for opening the respective pad portions is formed through the sixth mask process according to the present invention.

In more detail, the protective film 150 is entirely deposited on the substrate 102 on which the third conductive pattern is formed.

Thereafter, the photoresist is entirely formed on the passivation layer 150 and then a photolithography process using a sixth mask is performed to form a photoresist pattern exposing the passivation layer 150.

At this time, by etching the protective film 150 exposed by the photoresist pattern, as shown in FIG. A passivation layer having a mesh structure having first and third open holes 152, 154, and 156 exposing the 186 and the data pad upper electrode 196 is formed.

In this case, the protective layer 150 may prevent a decrease in contact reliability due to corrosion generated as the gate and data pad upper electrodes 186 and 196 are exposed to the outside through the second and third open holes 152 and 154. For example, as illustrated in region B, the gate and data pad upper electrodes 186 and 196 may be formed to cover a portion of the region.

After the protective film 150 is formed as described above, as shown in FIG. 6G, the organic light emitting layer 160 is formed on the protective film 150 by using a deposition method such as vacuum deposition or thermal deposition.

In this case, the organic light emitting layer 160 emits light to the outside through the light emitting region by the voltage applied between the first and second electrodes to display an image.

After the organic light emitting layer 160 is formed as described above, as illustrated in FIG. 6H, the conductive material is entirely deposited on the organic light emitting layer 160 through a deposition process such as sputtering.

Here, the second electrode 170 serves to apply a potential to the organic light emitting layer 160 together with the first electrode 140, and selected from aluminum (Al), calcium (Ca), and magnesium (Mg). Or a double metal layer of lithium fluorine / aluminum (LIF / Al).

As described above, the flat panel display panel and the manufacturing method thereof according to the present invention are configured so that a portion of the pad portion connected to the signal line is covered with a protective film, thereby preventing corrosion of the pad portion, thereby increasing connection reliability with the signal line. It provides the effect that it can be done.

In addition, the present invention provides an effect of increasing the contact reliability of the pad portion and the signal line by forming a separate dummy electrode in contact with the signal line in the pad portion.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (20)

A flat panel display panel that displays an image through light emitted from an organic light emitting layer, A gate pad portion connected to the gate line; A data pad section connected to a data line; And And a protective film having an open hole for opening the gate pad part and the data pad part. And the passivation layer is formed to cover a portion of each pad portion exposed to the outside by the open hole. The method of claim 1, The gate pad part, A gate pad lower electrode connected to the gate line; An interlayer insulating layer having a contact hole exposing the gate pad lower electrode; A gate pad dummy electrode formed on the interlayer insulating layer to be spaced apart from each other with a contact hole interposed therebetween; And And a gate pad upper electrode connected to the gate pad lower electrode through the contact hole. The method of claim 2, The gate pad dummy electrode is made of a transparent conductive material (ITO). The method of claim 2, And the gate pad upper electrode partially overlaps the gate pad dummy electrode. The method of claim 4, wherein And the gate pad upper electrode is partially covered by the passivation layer. The method of claim 1, The data pad, A data pad lower electrode connected to a data line crossing the gate line through a gate insulating layer; An interlayer insulating layer having contact holes exposing the data pad lower electrodes; A data pad dummy electrode formed on the interlayer insulating layer to be spaced apart from each other with the contact hole interposed therebetween; And And an upper electrode on the data pad connected to the lower electrode of the data pad through the contact hole. The method of claim 6, And the data pad dummy electrode is electrically connected to the data line. The method of claim 7, wherein The data pad dummy electrode is formed of a transparent conductive material (ITO). The method of claim 6, And the data pad upper electrode is partially overlapped with the data pad dummy electrode. The method of claim 6, And the data pad upper electrode is partially covered by the passivation layer. In the manufacturing method of a flat panel display panel for displaying an image through the light emitted from the organic light emitting layer, Forming a gate pad portion connected to the gate line and a data pad portion connected to the data line; And And forming a protective film having an open hole exposing the gate pad part and the data pad part. And the passivation layer is formed to cover a portion of each pad portion exposed to the outside by the open hole. The method of claim 11, Forming the gate pad portion, Forming a gate pad lower electrode connected to the gate line; Forming an interlayer insulating layer having a contact hole exposing the gate pad lower electrode; Forming a gate pad dummy electrode on the interlayer insulating layer to be spaced apart from each other with the contact hole interposed therebetween; And And forming a gate pad upper electrode connected to the gate pad lower electrode through the contact hole. The method of claim 12, The gate pad dummy electrode is formed of a transparent conductive material (ITO). The method of claim 12, And the gate pad upper electrode partially overlaps the gate pad dummy electrode. The method of claim 12, And the gate pad upper electrode is partially covered by the passivation layer. The method of claim 11, The forming of the data pad part may include: Forming a data pad lower electrode connected to the data line crossing the gate line through the gate insulating layer; Forming an interlayer insulating layer having a contact hole exposing the data pad lower electrode; Forming a data pad dummy electrode formed on the interlayer insulating layer and spaced apart from each other with the contact hole interposed therebetween; And And forming a data pad upper electrode connected to the data pad lower electrode through the contact hole. The method of claim 16, And the data pad dummy electrode is electrically connected to the data line. The method of claim 17, The data pad dummy electrode is formed of a transparent conductive material (ITO). The method of claim 16, And the data pad upper electrode is partially overlapped with the data pad dummy electrode. The method of claim 19, The data pad upper electrode is formed to be partially covered by the passivation layer.

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