KR20080055564A - Flat-type chip varistor - Google Patents

Abstract

A flat type chip varistor is provided to prevent a ceramic wave from being bent in a sintering process by sintering a single bare chip. A flat type chip varistor includes a flat type varistor ceramic(100), a first electrode(210), and a plurality of second electrodes(220). The first electrode is contacted with a whole rear plane of the flat type varistor ceramic. The second electrodes are partitioned and contacted with a predetermined interval on a surface of the flat type varistor ceramic. The predetermined interval is more than a thickness of the flat type varistor ceramic. The thickness of the flat type varistor ceramic is 40% to 100% of a length or a width of the flat type varistor ceramic.

Description

Flat Chip Varistors {Flat-type chip varistor}

1 is a perspective view showing the configuration of a flat chip varistor according to an embodiment of the present invention.

2 (a) and 2 (b) are perspective views showing the configuration of a flat chip varistor according to another embodiment of the present invention.

3 is a flowchart illustrating a method of manufacturing a flat chip varistor according to the present invention.

4 is a manufacturing process diagram of the flowchart of FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar chip varistor and a method of manufacturing the same, and more particularly, to a technique capable of producing a high yield of such chip varistors while implementing a plurality of varistors in a single bare chip.

Recently, light emitting diodes (LEDs) have emerged as leading players in the next lighting market to replace light sources and light bulbs of various electronic devices such as electronic signs, mobile phones, and computers, and the demand of the market is exploding. Since LEDs are very vulnerable to electrostatic discharge (ESD), Zener diodes or SMD varistors have been used as protection devices.

Zener diodes and SMD varistors, which are used as static protection devices, have some problems in application to high-brightness white LEDs and LED arrays, which are recently being issued.

In the case of a Zener diode, there is a problem of being a unidirectional protection device against overvoltage. That is, unidirectional means a characteristic that allows electricity to flow in only one direction, but when used in parallel with the LED chip, there is a problem in that it does not exhibit any protection against ESD from the opposite direction. In addition, in a white LED or an LED array implemented by a combination of RGB LEDs, in order to protect a large number of LED elements from static electricity, multiple zener diodes must be used. In this case, space costs and work costs increase. And, there is a disadvantage that the brightness is lowered.

Although many attempts have been made to apply the planar varistor to compensate for the problem of the Zener diode, the planar chip varistor has not been applied so far due to the following technical problems in manufacturing.

Specifically, as a method of manufacturing a planar chip varistor, a bare chip manufacturing of a general NTC thermistor is applied, and such a method is made by firing a green wafer having a length of 50 mm, a width of 50 mm, and a thickness of 5 mm to match flatness. After lapping, electrodes are attached and die sawing is used to form unit chips.

However, in this manufacturing process, the warpage of the wafer due to shrinkage of the ceramic during the firing process is always a problem, it is difficult to lower the thickness of the green wafer. In addition, yield and process costs are problematic in controlling the thickness of the ceramic wafer in the range of 100 μm to 150 μm during the lapping process. In addition, in the process of cutting the ceramic wafer into a single chip, there is a disadvantage in that a cracking phenomenon occurs in the bonding surface and the cutting surface of the electrode and the ceramic by a dicing blade which rotates at a high speed. In particular, when the size of a single chip cut by the die sawing method is 250 μm in length, 250 μm in width, and 150 μm in thickness like a general zener diode, the above-mentioned crack failure phenomenon occurs severely.

In addition, some LED package companies are applying SMD varistors instead of Zener diodes, but when multiple electrostatic protection devices are required, such as in RGB LEDs, there are dimensional constraints on SMD varistors, making it difficult to apply to this field. .

Accordingly, an object of the present invention is to provide a chip varistor that can implement a plurality of varistors on a single chip to solve the spatial problem and at the same time increase the work efficiency.

Another object of the present invention is to provide a manufacturing method capable of minimizing a defect in ceramic in a die sawing process and minimizing warpage of a ceramic in a firing process.

The above object is a planar varistor ceramic; It is achieved by a planar chip varistor including a primary electrode integrally bonded to the front surface of the back surface of the planar varistor ceramic; and a plurality of secondary electrodes partitioned and bonded to the surface of the planar varistor ceramic at regular intervals.

In addition, the above object is a flat varistor ceramic; A plurality of primary electrodes partitioned and bonded to the rear surface of the plate-type varistor ceramic at regular intervals; And a plurality of secondary electrodes partitioned and joined at regular intervals on the surface of the planar varistor ceramic to correspond to the primary electrodes.

Preferably, the predetermined interval may be greater than or equal to the thickness of the varistor ceramic.

In addition, the varistor ceramic may have a thickness of 40% to 100% of its length or width.

In addition, an insulating material may be interposed in the space formed by the predetermined interval.

The varistor ceramic may be composed of a composition containing one of zinc oxide and strontium titanate as a main component, and the electrode may include any one of gold, palladium, platinum, silver, nickel, and copper.

The above object is to prepare a varistor green sheet laminate; Forming a primary electrode on a surface of the green sheet laminate; Forming a secondary electrode corresponding to the primary electrode on the rear surface of the green sheet laminate; Pressing the green sheet laminate and the primary and secondary electrodes to be in close contact with each other; Cutting the compressed green sheet stack to a single chip size; A debinding step of burning off the binder included in the cut single chip; And baking the de-binded single chip under conditions corresponding to the varistor.

The primary and secondary electrodes may be formed by any one of screen printing, sputtering, and etching.

In addition, the green sheet laminate including the primary and secondary electrodes may be vacuum-packed and compressed by isothermal isostatic pressure before the pressing.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view showing the configuration of a flat chip varistor according to an embodiment of the present invention.

Referring to FIG. 1, a planar chip varistor according to the present invention includes a varistor ceramic 100 and electrodes 210 and 220 bonded to the front and rear surfaces of the varistor ceramic 100, respectively.

In this embodiment, the electrode 210 bonded to the surface of the varistor ceramic 100 is divided into four, but the number of divisions is not limited thereto. In addition, the electrode 220 bonded to the back surface of the varistor ceramic 100 is formed in a single body.

According to such a structure, a plurality of varistors having a vertical structure formed by each of the single electrodes 220 formed on the rear surface and the plurality of electrodes 210 formed on the surface of the varistor ceramic 100 are formed on one bare chip. Therefore, it is possible to solve the spatial problem by increasing the efficiency of the bare chip area.

2 (a) and 2 (b) are perspective views showing the configuration of a flat chip varistor according to another embodiment of the present invention.

2 (a) and 2 (b), the electrodes 210 and 210 'bonded to the surface of the varistor ceramic 100 and the electrodes 230 and 240 bonded to the rear surface of the varistor ceramic 100 have the same shape and number, respectively. Corresponds. In other words, the electrodes 210 and 210 ′ bonded to the surface have a symmetrical structure with respect to the electrodes 230 and 240 and the varistor ceramic 100 bonded to the rear surface.

Bonding of the varistor ceramic 100 and the electrodes 210, 210 ′, 220, 230, 240 is performed on the upper and lower surfaces of the green sheet laminate (1100 of FIG. 4) corresponding to the varistor ceramic 100. , 220, 230, 240 to form an electrode paste by the screen printing method, etc., after drying it is made through the process of simultaneous firing after pressing and de-binder of isothermal isostatic pressure. This will be described later.

The varistor ceramic 100 in FIGS. 1, 2 (a) and 2 (b) is a ceramic having various dielectric constants depending on the range of capacitance (hereinafter referred to as Cp) required for the final flat chip varistor. Composition groups are optionally applied.

Preferably, when Cp is less than 10 pF, a composition group mainly comprising zinc oxide (ZnO) having a dielectric constant in the range of 400 to 1000 is applied, and when Cp is more than 10 pF, strontium titanate (SrTiO) having a dielectric constant in the range of 5,000 to 20,000. _The composition group whose main component is ₃ ) can be applied.

In the chip varistor of the present invention, the material of the electrodes 210, 210 ′, 220, 230, and 240 may be any one of gold, platinum, palladium, silver, nickel, and copper, and the firing temperature range of the varistor ceramic 100 may be It should be selected in consideration of the firing atmosphere conditions and the bonding property of the electrodes 210, 210 ', 220, 230, 240 and the varistor ceramic 100.

The electrodes 210, 210 ′, 220, 230, and 240 formed on the front and back surfaces of the varistor ceramic 100 may be applied by selecting a vacuum deposition method such as paste printing, sputtering, or an etching process. In particular, in the case of using the paste printing method, a high temperature glass frit may be included in the electrode paste in order to increase the bonding force between the electrode paste and the varistor ceramic 100 during the co-firing process.

In addition, the spaces 212 and 214 between the electrodes and the electrodes arranged on the surface or the rear surface of the planar varistors shown in FIGS. 1, 2A and 2B may have the thickness of the varistor ceramic 100. It must be formed equal to or longer than this to effectively protect the circuit against electrostatic discharge. However, if a highly insulating material is present in the final planar chip varistor, the design consideration for the space between the electrode and the varistor ceramic thickness can be ruled out.

The manufacturing method of this invention which has such a structure is demonstrated below.

FIG. 3 is a flowchart illustrating a method of manufacturing a flat chip varistor according to the present invention, and FIG. 4 is a manufacturing process diagram of the flowchart of FIG. 3.

First, as shown in FIG. 4A, a green sheet laminate 1100 corresponding to the varistor ceramic 100 is prepared (step S31). For convenience of description, although shown to be reduced to the size corresponding to four unit chips, in actual manufacturing, there are more than 20,000 unit chips in the green sheet stack 1100.

The thickness of the green sheet laminate 1100 should be selected under conditions in which warpage does not occur during firing with a single chip.

Preferably, the thickness of the finished flat plate varistor is designed to be in the range of 40% to 100% of the length or width size to prevent the occurrence of warpage. For example, when the length and width of the finished flat chip varistor are 300 μm each, the thickness is preferably in the range of 120 μm to 300 μm, and the thickness of the green sheet laminate 1100 is designed in consideration of shrinkage. .

Subsequently, as shown in FIG. 4B, the electrode paste is applied to the entire surface of the green sheet laminate 1100 by screen printing to form a primary electrode 2220 (step S32), and in FIG. 4C. As described above, the secondary electrode 2210 is formed on the surface of the green sheet laminate 1100 in the same pattern as that of FIG. 1 by using the screen printing method to form the ceramic wafer 10 (step S33).

Subsequently, in order to pressurize the green sheet laminate 1100 on which the primary and secondary electrodes 2220 and 2210 are formed using water pressure (step S34), isothermal isostatic pressing is performed (step S35) 1 The adhesion between the secondary and secondary electrodes 2220 and 2210 and the green sheet laminate 1100 is increased.

Next, as shown in FIG. 4D, the ceramic wafer 10 is cut into single chip sizes (step S36), divided into single chips 11, 12, 13, and 14, and subjected to a binder removal process (step S37). It bakes at the temperature, time, and atmospheric conditions corresponding to a varistor (step S38), and manufactures a flat chip varistor as shown in FIG.4 (e).

As such, since the chips are cut to a single chip size before firing, cracking failure due to cutting can be minimized. In addition, since the firing is performed in a single chip state, the warpage phenomenon can be minimized even if the thickness of the varistor ceramic is thin.

In the above description, but with reference to the preferred embodiment of the present invention various modifications are possible at the level of those skilled in the art.

For example, the number and shape of the secondary electrodes can be changed as appropriate. In addition, the pressurization during the manufacturing process does not necessarily use a hydraulic pressure, and thus the vacuum packaging process may be omitted.

Therefore, the scope of the present invention should not be limited to the above embodiment, but should be construed according to the claims described below.

As described above, the present invention has various advantages.

First, since the plate-type chip varistor is fired in a single chip state, even if the thickness of the ceramic is thin, it is possible to prevent the warpage phenomenon occurring during the firing process of the ceramic wafer in the existing bare chip manufacturing process. It can be manufactured so that the surface roughness of a joining surface and a cut surface is uniform.

In addition, since a single chip is cut and fired, productivity is higher than that of a bare chip manufacturing method using a conventional die sawing method, and a lot of process costs can be reduced.

In addition, a plurality of flat chip varistors can be manufactured by dividing the electrodes of the flat chip varistor into two or more, so that when a large number of protection elements are required, there is an advantage of minimizing space and reducing process costs. In particular, for red-green-blue LEDs and LED arrays, multiple flat chip varistors can be used very efficiently.

Claims (10)

Flat varistor ceramics; A primary electrode integrally bonded to the front surface of the back surface of the planar varistor ceramic; and And a plurality of secondary electrodes partitioned and bonded to the surface of the planar varistor ceramic at regular intervals. Flat varistor ceramics; A plurality of primary electrodes partitioned and bonded to the rear surface of the plate-type varistor ceramic at regular intervals; And And a plurality of secondary electrodes which are partitioned and joined at regular intervals on the surface of the planar varistor ceramic to correspond to the primary electrodes. The method according to claim 1 or 2, The predetermined interval is a flat chip varistor, characterized in that more than the thickness of the varistor ceramic. The method according to claim 3, And the thickness of the varistor ceramic is 40% to 100% of its length or width. The method according to claim 1 or 2, Flat chip varistor, characterized in that the insulating material is interposed in the space formed by the predetermined interval. The method according to claim 1 or 2, The varistor ceramic is a planar chip varistor, characterized in that the composition consisting of a zinc oxide, strontium titanate as a main component. The method according to claim 1 or 2. The electrode is a flat chip varistor, comprising any one of gold, palladium, platinum, silver, nickel, copper. Preparing a varistor green sheet laminate; Forming a primary electrode on a surface of the green sheet laminate; Forming a secondary electrode corresponding to the primary electrode on the rear surface of the green sheet laminate; Pressing the green sheet laminate and the primary and secondary electrodes to be in close contact with each other; Cutting the compressed green sheet stack to a single chip size; A debinding step of burning off the binder included in the cut single chip; And And baking the debonded single chip under conditions corresponding to the varistor. The method according to claim 8, The method of claim 1, wherein the primary and secondary electrodes are formed by any one of screen printing, sputtering, and etching. The method according to claim 8, A method of manufacturing a flat chip varistor, wherein the green sheet laminate including the primary and secondary electrodes is vacuum-packed and compressed by isothermal isostatic pressure before the pressing.

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