KR20080054927A - Manufacturing mathod of organic light emitting diode display - Google Patents

Abstract

A manufacturing method of an organic light emitting diode display is provided to improve Ion and Ioff characteristics of a thin film transistor through plasma treatment. A manufacturing method of an organic light emitting diode display includes the steps of: forming a gate line including a first control electrode(124a) and a second control electrode(124b) on a substrate; forming a gate insulating layer on the gate line and the second control electrode; forming an amorphous silicon layer on the gate insulating layer; forming a polycrystalline silicon layer by annealing the amorphous silicon layer; performing H2 plasma treatment on the polycrystalline silicon layer; forming first and second semiconductors(154a,154b) by patterning the polycrystalline silicon layer; forming a data line(171) having a first input electrode(173a), a driving voltage line(172) having a second input electrode(173b), and first and second output electrodes(175a,175b) on the first and second semiconductors; forming a passivation layer on the data line, the driving voltage line, and the first and second output electrodes; forming a connecting member(85) to connect the first output electrode and the second input electrode and a first electrode(191) connected to the second output electrode on the passivation layer; forming a partition including an opening on the first electrode; forming a light emitting member on the opening; and forming a second electrode on the light emitting member.

Description

MANUFACTURING MATHOD OF ORGANIC LIGHT EMITTING DIODE DISPLAY}

1 is an equivalent circuit diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention.

2 is a layout view of an organic light emitting diode display according to an exemplary embodiment.

3 is a cross-sectional view of the organic light emitting diode display of FIG. 2 taken along the line III-III.

4 is a cross-sectional view of the organic light emitting diode display of FIG. 2 taken along the line IV-IV.

FIG. 5 is a layout view at an intermediate stage of a method of manufacturing an organic light emitting display device according to an embodiment. FIG.

6 and 7 are cross-sectional views taken along the lines VI-VI and VII-VII of FIG. 5, respectively.

8 and 9 are cross-sectional views taken along the lines VI-VI and VII-VII of FIG. 5 as cross-sectional views in the next steps of FIGS. 6 and 7.

FIG. 10 is a layout view at the next step of FIG. 5.

11 and 12 are cross-sectional views taken along the lines XI-XI and XII-XII of FIG. 10, respectively.

FIG. 13 is a layout view in the next step of FIG. 10.

14 and 15 are cross-sectional views taken along the lines XIV-XIV and XV-XV of FIG. 13.

FIG. 16 is a layout view at the next step of FIG. 13.

17 and 18 are cross-sectional views taken along the lines XVII-XVII and XVIII-XVIII of FIG. 16.

19 and 20 are graphs showing Id values according to Vg changes when plasma processing is performed according to an embodiment of the present invention.

The present invention relates to a method of manufacturing an organic light emitting display device.

Recently, there is a demand for weight reduction and thinning of a monitor or a television, and according to such a demand, a cathode ray tube (CRT) has been replaced by a liquid crystal display (LCD).

However, the liquid crystal display device requires not only a separate backlight as a light emitting device, but also has many problems in response speed and viewing angle.

Recently, as a display device capable of overcoming such a problem, an organic light emitting diode display (OLED display) has attracted attention.

The organic light emitting diode display includes two electrodes and a light emitting layer interposed therebetween, and electrons injected from one electrode and holes injected from another electrode are combined in the light emitting layer to form excitons. The excitons emit light while releasing energy.

The OLED display is self-luminous and does not require a separate light source, which is advantageous in terms of power consumption, and also has excellent response speed, viewing angle, and contrast ratio.

The organic light emitting diode display may be classified into a passive matrix OLED display of a simple matrix type and an active matrix OLED display of an active matrix type according to a driving method.

Among these, an active matrix type organic light emitting display device is a driving thin film transistor that is connected to a signal line to control a data voltage and a data voltage received therefrom as a gate voltage to drive current through the light emitting device. And driving thin film transistors.

 The semiconductor of the thin film transistor is made of polycrystalline silicon (polysilicon) or amorphous silicon (amorphous silicon).

In general, silicon may be divided into amorphous silicon and crystalline silicon according to the crystal state. Amorphous silicon can be deposited at a low temperature to form a thin film, and thus is mainly used in display devices using glass having a low melting point as a substrate. However, due to the low field effect mobility of amorphous silicon, polysilicon is required to have high field effect mobility, high frequency operating characteristics, and low leakage current electrical properties.

Polycrystalline silicon can be formed by crystallizing amorphous silicon by methods such as ELA (eximer laser anneal), solid phase crystallization (SPC), sequential lateral solidification (SLS), and the like.

However, since the solid phase crystallization process proceeds at high temperature, dehydrogenation occurs in the polysilicon film during heat treatment. At this time, due to the position where hydrogen escapes from the polycrystalline silicon film, electrical characteristics such as Ion and Ioff of the thin film transistor are reduced.

Therefore, the technical problem to be achieved by the present invention is to minimize the damage of the polycrystalline silicon film due to the heat treatment.

According to an aspect of the present invention, there is provided a method of manufacturing an organic light emitting display device, including forming a gate line and a second control electrode including a first control electrode on a substrate, and forming a gate on the gate line and the second control electrode. Forming an insulating film, forming an amorphous silicon film on the gate insulating film, heat treating the amorphous silicon film to form a polycrystalline silicon film, subjecting the polycrystalline silicon film to H ₂ plasma treatment, patterning the polycrystalline silicon film to form the first and second semiconductors Forming a data line having a first input electrode, a driving voltage line having a second input electrode, forming a first output electrode and a second output electrode on the first and second semiconductors, a data line, a driving voltage line, and Forming a passivation layer on the first output electrode and the second output electrode, and connecting the first output electrode and the second input electrode on the passivation layer; Forming a first electrode, the first electrode connected to the second output electrode, forming a partition including an opening on the first electrode, forming a light emitting member in the opening, and forming a second electrode on the light emitting member. It includes a step.

The H ₂ plasma treatment step may be performed for 30 to 120 sec by maintaining the chamber power density at 0.25 ~ 4W / ㎠ in H ₂ atmosphere, maintaining the pressure at 1,000 ~ 5,000mT.

Crystallization can be crystallized by the solid phase crystallization method.

According to another aspect of the present invention, there is provided a method of manufacturing an organic light emitting display device, including forming a gate line and a second control electrode including a first control electrode on a substrate, and forming a gate insulating layer on the gate line and the second control electrode. Forming a first amorphous silicon film and a second amorphous silicon film on the gate insulating film, and thermally treating the first amorphous silicon film and the second amorphous silicon film to form first and second polycrystalline silicon films; Patterning the second polycrystalline silicon film and the first polycrystalline silicon film to form the ohmic contact layer pattern and the first and second semiconductors; Forming a driving voltage line, a first output electrode and a second output electrode, a data line, a driving voltage line, a first output electrode and a second output electrode Steps to the ohmic contact layer pattern etched as a mask to form the ohmic contact members, the forming a protection film on the first semiconductor and further comprising: a second semiconductor processing H ₂ plasma, a data line, a driving voltage line, the first output electrode and second output electrode Forming a connecting member connecting the first output electrode and the second input electrode on the passivation layer; forming a first electrode connected to the second output electrode; forming a partition wall including an opening on the first electrode; Forming a light emitting member on the substrate, and forming a second electrode on the light emitting member.

The H ₂ plasma treatment may be performed for 30 to 120 sec by maintaining the chamber power density at 0.25-4 W / cm 2 and maintaining the pressure at 1,000-5,000 mT in the H ₂ atmosphere.

Crystallization can be crystallized by the solid phase crystallization method.

In the second amorphous silicon film, n-type impurities such as phosphorus may be doped with high concentration.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, an organic light emitting diode display according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 1.

1 is an equivalent circuit diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the organic light emitting diode display according to the present exemplary embodiment includes a plurality of signal lines 121, 171, and 172, and a plurality of pixels connected to them and arranged in a substantially matrix form. do.

The signal line includes a plurality of gate lines 121 for transmitting a gate signal (or scan signal), a plurality of data lines 171 for transmitting a data signal, and a plurality of driving voltage lines for transmitting a driving voltage. and a driving voltage line 172. The gate lines 121 extend substantially in the row direction, and are substantially parallel to each other, and the data line 171 and the driving voltage line 172 extend substantially in the column direction, and are substantially parallel to each other.

Each pixel PX includes a switching transistor Qs, a driving transistor Qd, a storage capacitor Cst, and an organic light emitting diode OLED. It includes.

The switching transistor Qs has a control terminal, an input terminal and an output terminal, respectively, and the control terminal is connected to the gate line 121, and the input terminal is connected to the data line ( The output terminal is connected to the driving thin film transistor Qd. The switching transistor Qs transfers the data signal applied to the data line 171 to the driving transistor Qd in response to the scan signal applied to the gate line 121.

The driving transistor Qd also has a control terminal, an input terminal and an output terminal, the control terminal being connected to the switching transistor Qs, the input terminal being connected to the driving voltage line 172, and the output terminal being the organic light emitting diode. It is connected to (LD). The driving transistor Qd flows an output current I _LD whose magnitude varies depending on the voltage applied between the control terminal and the output terminal.

The capacitor Cst is connected between the control terminal and the input terminal of the driving transistor Qd. The capacitor Cst charges the data signal applied to the control terminal of the driving transistor Qd and maintains it even after the switching transistor Qs is turned off.

The organic light emitting diode LD has an anode connected to the output terminal of the driving transistor Qd and a cathode connected to the common voltage Vss. The organic light emitting diode LD displays an image by emitting light having a different intensity depending on the output current I _LD of the driving transistor Qd.

The switching transistor Qs and the driving transistor Qd are n-channel field effect transistors (FETs). However, at least one of the switching transistor Qs and the driving transistor Qd may be a p-channel field effect transistor. In addition, the connection relationship between the transistors Qs and Qd, the capacitor Cst, and the organic light emitting diode LD may be changed.

Next, the detailed structure of the organic light emitting diode display illustrated in FIG. 1 will be described in detail with reference to FIGS. 2 to 4 and FIG. 1.

FIG. 2 is a layout view of an organic light emitting diode display according to an exemplary embodiment. FIG. 3 is a cross-sectional view of the organic light emitting diode display of FIG. 2 taken along a line III-III. FIG. 4 is an organic light emitting diode of FIG. A cross-sectional view of the display device taken along the line IV-IV.

A plurality of gate conductors including a gate line 121 including a first control electrode 124a and a plurality of second control electrodes 124b on an insulating substrate 110 made of transparent glass or plastic. (gate conductor) is formed.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a wide end portion (not shown) for connection with another layer or an external driving circuit, and the first control electrode 124a extends upward from the gate line 121. When a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The second control electrode 124b is separated from the gate line 121 and includes a storage electrode 127 extending downward and briefly changing to the right and extending upward.

The gate conductors 121 and 124b are made of copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), and titanium (Ti). Can lose. However, they may have a multilayer structure including two conductive films (not shown) having different physical properties.

Side surfaces of the gate conductors 121 and 124b are inclined with respect to the substrate 110 surface, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) is formed on the gate conductors 121 and 124b.

The first semiconductor 154a and the second semiconductor 154b are formed on the gate insulating layer 140. The first semiconductor 154a overlaps the first control electrode 124a, and the second semiconductor 154b overlaps the second control electrode 124b.

The first and second semiconductors 154a and 154b may be microcrystalline or polycrystalline semiconductors.

A plurality of pairs of island-like ohmic contacts 163a, 165a, 163b, and 165b are formed on the first semiconductor 151 and the second semiconductor 154b, respectively. The ohmic contacts 163 and 165 may be made of polycrystalline silicon doped with a high concentration of n-type impurities such as phosphorus.

The plurality of data lines 171, the plurality of driving voltage lines 172, and the plurality of first and second output electrodes 175a and 175b are disposed on the ohmic contacts 163a, 165a, 163b, and 165b and the gate insulating layer 140. A plurality of data conductors including the data conductors is formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 has a wide end portion (not shown) for connecting a plurality of first input electrodes 173a extending toward the first control electrode 124a with another layer or an external driving circuit. Not included). When a data driving circuit (not shown) generating a data signal is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The driving voltage line 172 transfers a driving voltage and mainly extends in the vertical direction to cross the gate line 121. Each driving voltage line 172 includes a plurality of second input electrodes 173b extending toward the second control electrode 124b. The driving voltage line 172 overlaps the sustain electrode 127.

The first and second output electrodes 175a and 175b are separated from each other and separated from the data line 171 and the driving voltage line 172. The first input electrode 173a and the first output electrode 175a face each other with respect to the first control electrode 124a, and the second input electrode 173b and the second output electrode 175b are the second control electrode. Facing each other around 124b.

The data conductors 171, 172, 175a, and 175b are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film (not shown). It may have a multi-layer structure including).

Like the gate conductors 121 and 124b, the data conductors 171, 172, 175a and 175b also preferably have their side surfaces inclined at an inclination angle of about 30 ° to 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 163a, 165a, 163b, and 165b include the semiconductors 154a and 154b below and the first and second input electrodes 173a and 173b and the first and second output electrodes 173a and 173b thereon. , Only between 175a and 175b) and lowers the contact resistance between them.

The passivation layer 180 is formed on the data conductors 171, 172, 175a, and 175b.

The passivation layer 180 is made of an inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, or a low dielectric insulator. The dielectric constant of the organic insulator and the low dielectric insulator is preferably 4.0 or less. Examples of the low dielectric insulator include a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). : F, etc. can be mentioned. The passivation layer 180 may be formed by having photosensitivity among the organic insulators, and the surface of the passivation layer 180 may be flat.

The passivation layer 180 is formed with a plurality of contact holes 185a and 185b exposing the first and second output electrodes 175a and 175b, respectively. The passivation layer 180 and the gate insulating layer 140 have a second control electrode ( A plurality of contact holes 184 are formed to expose 124b.

A plurality of pixel electrodes 191 and a plurality of connecting members 85 are formed on the passivation layer 180. These may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the second output electrode 175b through the contact hole 185b, and the connection member 85 is connected to the second control electrode 124b through the contact holes 184 and 185a. ) And the first output electrode 175a.

A partition 361 is formed on the pixel electrode 191. The partition 361 defines an opening 365 by surrounding a periphery of the pixel electrode 191 like a bank and is made of an organic insulator or an inorganic insulator. The partition 361 may also be made of a photosensitizer including a black pigment, in which case the partition 361 serves as a light blocking member and the forming process is simple.

An organic light emitting member 370 is formed in the opening 365 on the pixel electrode 191 defined by the partition 361. The organic light emitting member 370 is made of an organic material that uniquely emits light of any one of primary colors such as three primary colors of red, green, and blue. The organic light emitting diode display displays a desired image by using a spatial sum of the primary color light emitted by the organic light emitting members 370.

The organic light emitting member 370 may have a multilayer structure including an auxiliary layer (not shown) for improving the light emitting efficiency of the light emitting layer in addition to the light emitting layer (not shown) for emitting light. The auxiliary layer includes an electron transport layer (not shown) and a hole transport layer (not shown) for balancing electrons and holes, and an electron injection layer for enhancing the injection of electrons and holes ( electron injecting layers (not shown) and hole injecting layers (not shown).

The common electrode 270 is formed on the organic light emitting member 370. The common electrode 270 receives a common voltage Vss and is made of a transparent conductive material such as ITO or IZO.

In the organic light emitting diode display, the first control electrode 124a connected to the gate line 121, the first input electrode 173a and the first output electrode 175a connected to the data line 171 may be formed. 1 together with the semiconductor 154a, a switching TFT Qs is formed, and a channel of the switching TFT Qs is formed between the first input electrode 173a and the first output electrode 175a. 1 is formed in the semiconductor 154a.

The second control electrode 124b connected to the first output electrode 175a, the second input electrode 173b connected to the driving voltage line 172, and the second output electrode connected to the pixel electrode 191 ( 175b forms a driving TFT Qd together with the second semiconductor 154b, and a channel of the driving TFT Qd is formed between the second input electrode 173b and the second output electrode 175b. It is formed in the second semiconductor 154b. The pixel electrode 191, the organic light emitting member 370, and the common electrode 270 form an organic light emitting diode LD, and the pixel electrode 191 is an anode and the common electrode 270 is a cathode. Alternatively, the pixel electrode 191 becomes a cathode and the common electrode 270 becomes an anode. The storage electrode 127 and the driving voltage line 172 overlapping each other form a storage capacitor Cst.

The organic light emitting diode display emits light toward the top or the bottom of the substrate 110 to display an image. The opaque pixel electrode 191 and the transparent common electrode 270 are applied to a top emission type organic light emitting display device that displays an image in an upward direction of the substrate 110. The opaque common electrode 270 is applied to a bottom emission organic light emitting display device that displays an image in a downward direction of the substrate 110.

Next, a method of manufacturing the OLED display illustrated in FIGS. 2 to 4 will be described in detail with reference to FIGS. 5 to 18.

5 is a layout view at an intermediate stage of a method of manufacturing an organic light emitting diode display according to an exemplary embodiment, and FIGS. 6 and 7 are cut along the lines VI-VI and VII-VII of FIG. 5, respectively. 8 and 9 are cross-sectional views taken along the lines VI-VI and VII-VII of FIG. 5 in cross-sectional views in the next steps of FIGS. 6 and 7, and FIG. 10 is a cross-sectional view taken in the next step of FIG. 11 and 12 are cross-sectional views taken along line XI-XI and XII-XII of FIG. 10, respectively, and FIG. 13 is a layout view of the next step of FIG. 10, and FIGS. 14 and 15 are FIG. 13. Fig. 16 is a cross sectional view taken along the lines XIV-XIV and XV-XV of Fig. 16, and Fig. 16 is a layout view of the next step of Fig. 13 and Figs. It is sectional drawing.

5 to 7, metal is deposited on the substrate 110 by sputtering to form a metal film. Subsequently, the metal layer is patterned to form a gate line 121 including the first control electrode 124a and a second control electrode 124b including the sustain electrode 127.

Next, as shown in FIGS. 8 and 9, the gate insulating layer 140 is formed on the substrate 110. The gate insulating layer 140 may form silicon nitride or silicon oxide by plasma enhanced chemical vapor deposition (PECVD).

Thereafter, the first doped amorphous silicon film and the doped second amorphous silicon film are formed by chemical vapor deposition. The first and second amorphous silicon films are crystallized by heat treatment to form first and second polycrystalline silicon films 150 and 160. Crystallization may be performed by solid phase crystallization (SPC), excimer laser annealing (ELA), or metal induced lateral crystallization (MILC), of which solid phase crystallization is preferred. .

Then, the surface of the polycrystalline silicon film is stabilized by H ₂ plasma treatment.

The H ₂ plasma treatment proceeds in a chemical vapor deposition machine, while maintaining the chamber power density at 0.25-4 W / cm ₂ in H ₂ atmosphere, and maintaining the pressure at 1,000-5,000 mT for 30-120 sec.

Next, as shown in FIGS. 10 to 12, the second polycrystalline silicon film 160 and the first polycrystalline silicon film 150 are etched to form the ohmic contact member pattern 164, the first semiconductor 154a, and the second semiconductor. 154b is formed.

Next, as shown in FIGS. 13 to 15, after forming a metal film on the substrate 110 such as sputtering and patterning, the data line 171 and the second input electrode 173b including the first input electrode 173a are patterned. A data conductor including a driving voltage line 172, a first output electrode 175a, and a second output electrode 175b is formed.

Subsequently, the ohmic contacts 163a, 163b, 165a and 165b are etched by etching the ohmic contacts 164 exposed with the data conductor as a mask.

The H ₂ plasma treatment in the steps of FIGS. 8 and 9 may be performed after the ohmic contact is formed, rather than the steps of FIGS. 8 and 9.

Next, as shown in FIGS. 16 to 18, the interlayer insulating layer 180 is stacked on the data conductors 171, 172, 175a, and 175b and photo-etched to form a plurality of contact holes 184, 185a, and 185b. .

The metal layer is formed on the interlayer insulating layer 180 and then patterned to form a plurality of pixel electrodes 191 and a plurality of connection members 85.

Next, as shown in FIGS. 2 to 4, the photosensitive organic insulating layer is coated, exposed, and developed to form a partition 361 having an opening 365 on the pixel electrode 191.

The light emitting member 370 is formed in the opening 365. The light emitting member 370 may be formed by a solution process or evaporation, such as an inkjet printing method, and an inkjet printing method is preferable.

Next, a common electrode 270 is formed on the partition 361 and the light emitting member 370.

Plasma treatment as in the embodiment of the present invention improves the Ion and Ioff characteristics of the thin film transistor, which can be confirmed through the graphs of FIGS. 19 and 20.

19 and 20 are graphs showing Id values according to Vg change when plasma treatment is performed according to an embodiment of the present invention.

Referring to FIG. 19, the graphs of plasma processing for 10 sec, 30 sec, and 120 sec while maintaining the chamber power density at 0.25-4 W / cm 2, and the ion current increases as the treatment time increases from 10 sec to 120 sec, and Ioff It can be seen that the current decreases.

20 is a graph of 10 sec, 30 sec, and 120 sec, respectively, after increasing the chamber power density to 1.25 W / cm 2 as compared with the embodiment of FIG. 19 having a chamber power density of 0.25 to 4 W / cm 2. It can be seen that as Ion increases to 120sec, Ion current increases and Ioff current decreases further.

That is, when the H ₂ plasma treatment is performed for a predetermined time as in the embodiment of the present invention, the semiconductor surface damaged by the dehydrogenation phenomenon during the heat treatment is stabilized. Therefore, the Ion current of the thin film transistor increases and the Ioff current decreases.

As described above, the present invention can provide an organic display device including a high quality thin film transistor by improving Ion and Ioff characteristics by plasma treatment.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

Claims (7)

Forming a gate line including a first control electrode and a second control electrode on the substrate; Forming a gate insulating film on the gate line and the second control electrode; Forming an amorphous silicon film on the gate insulating film, Heat treating the amorphous silicon film to form a polycrystalline silicon film, H ₂ plasma treatment of the polycrystalline silicon film, Patterning the polycrystalline silicon film to form first and second semiconductors, Forming a data line having a first input electrode, a driving voltage line having a second input electrode, a first output electrode, and a second output electrode on the first and second semiconductors; Forming a passivation layer on the data line, the driving voltage line, the first output electrode, and the second output electrode; Forming a connecting member connecting the first output electrode and the second input electrode on the passivation layer, and a first electrode connected to the second output electrode; Forming a partition wall including an opening on the first electrode; Forming a light emitting member in the opening, and Forming a second electrode on the light emitting member Method of manufacturing an organic light emitting display device comprising a. In claim 1, In the H ₂ plasma treatment step, the chamber power density is maintained at 0.25-4 W / cm ₂ in H ₂ atmosphere, and the pressure is maintained at 1,000-5,000 mT for 30-120 sec. In claim 1, And the crystallization is crystallized by a solid phase crystallization method. Forming a gate line including a first control electrode and a second control electrode on the substrate; Forming a gate insulating film on the gate line and the second control electrode; Forming a first amorphous silicon film and a second amorphous silicon film on the gate insulating film, Heat treatment to crystallize the first amorphous silicon film and the second amorphous silicon film to form first and second polycrystalline silicon films; Patterning the second polycrystalline silicon film and the first polycrystalline silicon film to form an ohmic contact layer pattern and first and second semiconductors, Forming a data line having a first input electrode, a driving voltage line having a second input electrode, a first output electrode, and a second output electrode on the ohmic contact pattern and the gate insulating layer; Forming a resistive contact member by etching the resistive contact layer pattern using the data line, the driving voltage line, the first output electrode, and the second output electrode as a mask; H ₂ plasma treatment of the first semiconductor and the second semiconductor, Forming a passivation layer on the data line, the driving voltage line, the first output electrode, and the second output electrode; Forming a connecting member connecting the first output electrode and the second input electrode on the passivation layer, and a first electrode connected to the second output electrode; Forming a partition wall including an opening on the first electrode; Forming a light emitting member in the opening, and Forming a second electrode on the light emitting member Method of manufacturing an organic light emitting display device comprising a. In claim 4, The H ₂ plasma process maintains the chamber power density at 0.25-4 W / cm ₂ in H ₂ atmosphere and maintains the pressure at 1,000-5,000 mT for 30-120 sec. In claim 4, And the crystallization is crystallized by a solid phase crystallization method. In claim 4, The second amorphous silicon film has a high concentration of n-type impurities such as phosphorus.

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