KR20080062281A - Organic light emitting diode display and method for manufacturing the same - Google Patents

Abstract

An organic light emitting diode display and a method of manufacturing the same are provided to form a data conductor of an exact size by forming a data line through lift-off of a photosensitive film pattern. First and second semiconductors(154a,154b) are formed on a substrate. An insulating layer is formed on the first and second semiconductors and has openings to expose the first and second semiconductors. Ohmic contact members are formed in the openings. A data line(171) having a first input electrode(173a), a driving voltage line(172) having a second input electrode(173b), and first and second output electrodes(175a,175b) are formed on the ohmic contact members. A gate insulating film is formed on the data line, the driving voltage line, and the first and second output electrodes. A gate line(121) having a first control electrode(124a) and a second control electrode(124b) are formed on the gate insulating film. A passivation layer is formed on the gate line and the second control electrode. A first electrode(191) is formed on the passivation layer. A light emitting member(370) is formed on the first electrode. A second electrode is formed on the light emitting member. The ohmic contact member is buried in the opening and has the same pattern as the opening.

Description

Organic light-emitting display device and manufacturing method therefor {ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME}

1 is an equivalent circuit diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention.

2 is a layout view of an organic light emitting diode display according to an exemplary embodiment.

3 is a cross-sectional view of the organic light emitting diode display of FIG. 2 taken along the line III-III.

4 is a cross-sectional view of the organic light emitting diode display of FIG. 2 taken along the line IV-IV.

FIG. 5 is a layout view at an intermediate stage of a method of manufacturing an organic light emitting display device according to an embodiment. FIG.

6 and 7 are cross-sectional views taken along the lines VI-VI and VII-VII of FIG. 5, respectively.

FIG. 8 is a layout view at the next step of FIG. 5.

9 and 10 are cross-sectional views taken along the lines IX-IX and X-X of FIG. 8.

11 and 12 are cross-sectional views taken along the lines IX-IX and X-X of FIG. 8 as cross-sectional views in the next steps of FIGS. 9 and 10.

FIG. 13 is a layout view in the next step of FIG. 8.

14 and 15 are cross-sectional views taken along the lines XIV-XIV and XV-XV of FIG. 13.

FIG. 16 is a layout view at the next step of FIG. 13.

17 and 18 are cross-sectional views taken along the lines XVII-XVII and XVIII-XVIII of FIG. 16.

FIG. 19 is a layout view at the next step of FIG. 16.

20 and 21 are cross-sectional views taken along the lines XX-XX and XXI-XXI of FIG. 19.

22 is a layout view of an organic light emitting diode display according to another exemplary embodiment of the present invention.

FIG. 23 is a cross-sectional view of the organic light emitting diode display of FIG. 22 taken along the line XXIII-XXIII.

FIG. 24 is a cross-sectional view of the organic light emitting diode display of FIG. 22 taken along the line XIV-XIV.

The present invention relates to an organic light emitting display device and a manufacturing method thereof.

Recently, there is a demand for weight reduction and thinning of a monitor or a television, and according to such a demand, a cathode ray tube (CRT) has been replaced by a liquid crystal display (LCD).

However, the liquid crystal display device requires not only a separate backlight as a light emitting device, but also has many problems in response speed and viewing angle.

Recently, as a display device capable of overcoming such a problem, an organic light emitting diode display (OLED display) has attracted attention.

The organic light emitting diode display includes two electrodes and a light emitting layer interposed therebetween, and electrons injected from one electrode and holes injected from another electrode are combined in the light emitting layer to form excitons. The excitons emit light while releasing energy.

The OLED display is self-luminous and does not require a separate light source, which is advantageous in terms of power consumption, and also has excellent response speed, viewing angle, and contrast ratio.

The organic light emitting diode display may be classified into a passive matrix OLED display of a simple matrix type and an active matrix OLED display of an active matrix type according to a driving method.

Among these, an active matrix type organic light emitting display device is a driving thin film transistor that is connected to a signal line to control a data voltage and a data voltage received therefrom as a gate voltage to drive current through the light emitting device. And driving thin film transistors.

 The semiconductor of the thin film transistor is made of polycrystalline silicon (polysilicon) or amorphous silicon (amorphous silicon).

In general, silicon may be divided into amorphous silicon and crystalline silicon according to the crystal state. Amorphous silicon can be deposited at a low temperature to form a thin film, and thus is mainly used in display devices using glass having a low melting point as a substrate. However, due to the low field effect mobility of amorphous silicon, polysilicon having high field effect mobility, high frequency operating characteristics, and low leakage current electrical characteristics is required.

However, the electrical characteristics of the thin film transistor including polycrystalline silicon are affected by the interface characteristics of the semiconductor.

Therefore, the technical problem to be achieved by the present invention is to improve the interface characteristics of the semiconductor.

The organic light emitting diode display according to the present invention for achieving the above technical problem is formed on the first and second semiconductor, the first semiconductor and the second semiconductor formed on the substrate and exposes the first semiconductor and the second semiconductor. An insulating layer including an opening, an ohmic contact member formed in the opening, a data line formed on the ohmic contact member, having a first input electrode, a driving voltage line having a second input electrode, first and second output electrodes, and data A line, a driving voltage line, a gate insulating film formed on the first and second output electrodes, a gate line including a first control electrode formed on the gate insulating film, and a second control electrode, a gate line, and a second control electrode. Protective film, a first electrode formed on the protective film, a light emitting member formed on the first electrode, a second formed on the light emitting member And an electrode, wherein the ohmic contact is embedded in the opening and has the same planar pattern as the opening.

The data line, the driving voltage line, the first and second output electrodes may be buried in the opening to have the same planar pattern as the ohmic contact member.

The first input electrode and the first output electrode may face each other on the first semiconductor with respect to the first control electrode, and the second input electrode and the second output electrode may face each other on the second semiconductor with respect to the second control electrode. have.

The capping layer may further include a capping layer formed on the first and second semiconductors and disposed between the first input electrode and the second output electrode and between the second input electrode and the second output electrode.

The first semiconductor and the second semiconductor may be made of polycrystalline silicon.

Another organic light emitting diode display for achieving the above object is an insulating layer formed on a substrate and formed of a first semiconductor made of polycrystalline silicon, a first semiconductor formed on the first semiconductor, and including first and second openings exposing the first semiconductor. First and second ohmic contacts formed in the first and second openings, the first ohmic contact formed on the first ohmic contact, and the first driving voltage line having the first input electrode and the first ohmic contact formed on the second ohmic contact. A first gate insulating film formed on the output electrode, the driving voltage line, and the first output electrode; and a first control electrode formed on the first gate insulating film and overlapping the first semiconductor; A second gate insulating layer formed on the gate line, the gate line, and the first control electrode having a second control electrode, A second semiconductor layer formed over the second gate insulating layer and overlapping the second control electrode; and third and fourth ohmic contacts overlapping and separated from the second semiconductor; The branch has a data line, a second output electrode formed on the fourth ohmic contact member, a protective film formed on the data line and the second output electrode, a first electrode formed on the protective film, a light emitting member formed on the first electrode, The second electrode may be formed on the light emitting member, and the ohmic contact may be embedded in the opening to have the same planar pattern as the opening.

The driving voltage line and the first output electrode may be buried in the opening to have the same planar pattern as the first and second ohmic contacts.

The second semiconductor may be made of amorphous silicon or polycrystalline silicon.

The capping layer may further include a capping layer formed on the first semiconductor and positioned between the first output electrode and the first input electrode.

According to another aspect of the present invention, there is provided a method of manufacturing an organic light emitting display device, including forming a first semiconductor and a second semiconductor on a substrate, forming an insulating layer on the first and second semiconductors, and an insulating layer. Forming a photoresist pattern thereon; forming an insulating layer including first and second openings exposing the first semiconductor and a third and fourth openings exposing the second semiconductor using the photoresist pattern as a mask; And forming an amorphous silicon film and a metal film doped with impurities in the first to fourth openings, and removing the photoresist pattern to form the ohmic contact member, the data line, the driving voltage line, the first output electrode, and the first to fourth openings. Forming an output electrode, forming a gate insulating film on the data line, the driving voltage line, the first output electrode and the second output electrode, and forming a gate insulating film on the gate insulating film. Forming a gate line including the first control electrode, a second control electrode overlapping the second semiconductor, forming a passivation layer on the gate line and the second control electrode, and forming the passivation layer on the passivation layer. The method may include forming a connection member connecting the electrode, a first electrode connected to the second output electrode, forming a light emitting member on the first electrode, and forming a second electrode on the light emitting member.

The photoresist pattern may be thicker than the doped amorphous silicon film and the metal film.

The forming of the first semiconductor and the second semiconductor may include forming an amorphous silicon film on the substrate, forming a polycrystalline silicon film by solidifying the amorphous silicon film, and patterning the polycrystalline silicon film.

The method may further include forming a capping layer on the amorphous silicon film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, an organic light emitting diode display according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 1.

1 is an equivalent circuit diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the organic light emitting diode display according to the present exemplary embodiment includes a plurality of signal lines 121, 171, and 172, and a plurality of pixels connected to them and arranged in a substantially matrix form. do.

The signal line includes a plurality of gate lines 121 for transmitting a gate signal (or scan signal), a plurality of data lines 171 for transmitting a data signal, and a plurality of driving voltage lines for transmitting a driving voltage. and a driving voltage line 172. The gate lines 121 extend substantially in the row direction, and are substantially parallel to each other, and the data line 171 and the driving voltage line 172 extend substantially in the column direction, and are substantially parallel to each other.

Each pixel PX includes a switching transistor Qs, a driving transistor Qd, a storage capacitor Cst, and an organic light emitting diode OLED. ).

The switching transistor Qs has a control terminal, an input terminal, and an output terminal, respectively, and the control terminal is connected to the gate line 121, and the input terminal is a data line ( The output terminal is connected to the driving thin film transistor Qd. The switching transistor Qs transfers the data signal applied to the data line 171 to the driving transistor Qd in response to the scan signal applied to the gate line 121.

The driving transistor Qd also has a control terminal, an input terminal and an output terminal, the control terminal being connected to the switching transistor Qs, the input terminal being connected to the driving voltage line 172, and the output terminal being the organic light emitting diode. It is connected to (LD). The driving transistor Qd flows an output current I _LD whose magnitude varies depending on the voltage applied between the control terminal and the output terminal.

The capacitor Cst is connected between the control terminal and the input terminal of the driving transistor Qd. The capacitor Cst charges the data signal applied to the control terminal of the driving transistor Qd and maintains it even after the switching transistor Qs is turned off.

The organic light emitting diode LD has an anode connected to the output terminal of the driving transistor Qd and a cathode connected to the common voltage Vss. The organic light emitting diode LD emits light of varying intensities according to the output current I _LD of the driving transistor Qd to display an image.

The switching transistor Qs and the driving transistor Qd are n-channel field effect transistors (FETs). However, at least one of the switching transistor Qs and the driving transistor Qd may be a p-channel field effect transistor. In addition, the connection relationship between the transistors Qs and Qd, the capacitor Cst, and the organic light emitting diode LD may be changed.

Next, the detailed structure of the organic light emitting diode display illustrated in FIG. 1 will be described in detail with reference to FIGS. 2 to 4 and FIG. 1.

FIG. 2 is a layout view of an organic light emitting diode display according to an exemplary embodiment. FIG. 3 is a cross-sectional view of the organic light emitting diode display of FIG. 2 taken along a line III-III. FIG. 4 is an organic light emitting diode of FIG. A cross-sectional view of the display device taken along the line IV-IV.

A blocking film 111 made of silicon oxide or silicon nitride is formed on an insulating substrate 110 made of transparent glass or plastic. The blocking film 111 may have a multilayer structure.

The first semiconductor 154a and the second semiconductor 154b are formed on the blocking film 111. The first semiconductor 154a and the second semiconductor 154b are made of polycrystalline silicon.

A capping layer 50 is formed on the first semiconductor 154a, the second semiconductor 154b, and the blocking layer 111. The capping layer 50 is positioned in a predetermined region of the first semiconductor 154a and the second semiconductor 154b, that is, a channel portion in which a channel of the thin film transistor is formed. The capping layer 50 may be omitted to protect the surfaces of the first semiconductor 154a and the second semiconductor 154b.

An insulating layer 60 having an opening 601 is formed on the capping layer 50 and the blocking layer 111. The opening 601 defines a region where a data conductor, which will be described later, is formed, and exposes the first and second semiconductors 154a and 154b in which the capping layer 50 is not formed.

A plurality of first and second linear ohmic contacts 161 and 165 and a plurality of first and second island type ohmic contact members 165a and 165b are formed in the opening 601 of the insulating layer 60. It is.

The ohmic contacts 161, 162, 165a, and 165b may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide. The first and second linear ohmic contacts 161 and 162 have a plurality of protrusions 163a and 163b, respectively, and the protrusions 163a and 163b and the island-like resistive contact members 165a and 165b are paired, respectively. It is disposed on the first and second semiconductors 154a and 154b.

The ohmic contacts 161, 162, 165a and 165b are filled in the openings 601 so that the ohmic contacts 161, 162, 165a and 165b have the same planar pattern.

A plurality of data conductive layers including a plurality of data lines 171, a plurality of driving voltage lines 172, and a plurality of first and second output electrodes 175a and 175b on the ohmic contacts 161, 162, 165a, and 165b. A data conductor is formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction. Each data line 171 has a wide end portion (not shown) for connecting a plurality of first input electrodes 173a extending toward the first semiconductor 154a with another layer or an external driving circuit. ). When a data driving circuit (not shown) generating a data signal is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The driving voltage line 172 transmits a driving voltage and mainly extends in the vertical direction. Each driving voltage line 172 includes a plurality of second input electrodes 173b extending toward the second semiconductor 154b.

The first and second output electrodes 175a and 175b are separated from each other and separated from the data line 171 and the driving voltage line 172. The first input electrode 173a and the first output electrode 175a face each other on the first semiconductor 154a, and the second input electrode 173b and the second output electrode 175b are on the second semiconductor 154b. Face each other

The data conductors 171, 172, 175a, and 175b are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film (not shown). It may have a multi-layer structure including).

It is preferable that the side surfaces of the data conductors 171, 172, 175a, and 175b be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The openings 601 are filled with the ohmic contacts 161, 162, 165a, and 165b and the data conductors 171, 172, 175a, and 175b, and their planar patterns are the same.

The gate insulating layer 140 made of silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) is formed on the data conductors 171, 172, 175a, and 175b and the insulating layer 60.

On the gate insulating layer 140, a plurality of gate conductors including a gate line 121 including a first control electrode 124a and a plurality of second control electrodes 124b are formed. have.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction to cross the data line 171 and the driving voltage line 172. Each gate line 121 includes an end portion (not shown) having a large area for connection with another layer or an external driving circuit, and the first control electrode 124a is connected to the first semiconductor (from the gate line 121). 154a). When a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The second control electrode 124b overlaps the second semiconductor 154b and is separated from the gate line 121. The storage electrode extends in a downward direction, changes in a direction to the right, and extends upwardly. 127). The storage electrode 127 overlaps the driving voltage line 172.

The gate conductors 121 and 124b are made of copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), and titanium (Ti). Can lose. However, they may have a multilayer structure including two conductive films (not shown) having different physical properties.

Side surfaces of the gate conductors 121 and 124b are inclined with respect to the substrate 110 surface, and the inclination angle is preferably about 30 ° to about 80 °.

The passivation layer 180 is formed on the gate conductors 121 and 124b.

The passivation layer 180 is made of an inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, or a low dielectric insulator. The dielectric constant of the organic insulator and the low dielectric insulator is preferably 4.0 or less. Examples of the low dielectric insulator include a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). : F, etc. can be mentioned. The passivation layer 180 may be formed by having photosensitivity among the organic insulators, and the surface of the passivation layer 180 may be flat.

The passivation layer 180 is formed with a plurality of contact holes 185a and 185b exposing the first and second output electrodes 175a and 175b, respectively. The passivation layer 180 and the gate insulating layer 140 have a second control electrode ( A plurality of contact holes 184 are formed to expose 124b.

A plurality of pixel electrodes 191 and a plurality of connecting members 85 are formed on the passivation layer 180. These may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the second output electrode 175b through the contact hole 185b, and the connection member 85 is connected to the second control electrode 124b through the contact holes 184 and 185a. ) And the first output electrode 175a.

A partition 361 is formed on the pixel electrode 191. The partition 361 defines an opening 365 by surrounding a periphery of the pixel electrode 191 like a bank and is made of an organic insulator or an inorganic insulator. The partition 361 may also be made of a photosensitizer including a black pigment, in which case the partition 361 serves as a light blocking member and the forming process is simple.

An organic light emitting member 370 is formed in the opening 365 on the pixel electrode 191 defined by the partition 361. The organic light emitting member 370 is made of an organic material that uniquely emits light of any one of primary colors such as three primary colors of red, green, and blue. The organic light emitting diode display displays a desired image by using a spatial sum of the primary color light emitted by the organic light emitting members 370.

The organic light emitting member 370 may have a multilayer structure including an auxiliary layer (not shown) for improving the light emitting efficiency of the light emitting layer in addition to the light emitting layer (not shown) for emitting light. The auxiliary layer includes an electron transport layer (not shown) and a hole transport layer (not shown) for balancing electrons and holes, and an electron injection layer for enhancing the injection of electrons and holes ( electron injecting layers (not shown) and hole injecting layers (not shown).

The common electrode 270 is formed on the organic light emitting member 370. The common electrode 270 receives a common voltage Vss and is made of a transparent conductive material such as ITO or IZO.

In the organic light emitting diode display, the first control electrode 124a connected to the gate line 121, the first input electrode 173a and the first output electrode 175a connected to the data line 171 may be formed. 1 together with the semiconductor 154a, a switching TFT Qs is formed, and a channel of the switching TFT Qs is formed between the first input electrode 173a and the first output electrode 175a. 1 is formed in the semiconductor 154a.

The second control electrode 124b connected to the first output electrode 175a, the second input electrode 173b connected to the driving voltage line 172, and the second output electrode connected to the pixel electrode 191 ( 175b forms a driving TFT Qd together with the second semiconductor 154b, and a channel of the driving TFT Qd is formed between the second input electrode 173b and the second output electrode 175b. It is formed in the second semiconductor 154b. The pixel electrode 191, the organic light emitting member 370, and the common electrode 270 form an organic light emitting diode LD, and the pixel electrode 191 is an anode and the common electrode 270 is a cathode. Alternatively, the pixel electrode 191 becomes a cathode and the common electrode 270 becomes an anode. The storage electrode 127 and the driving voltage line 172 overlapping each other form a storage capacitor Cst.

The organic light emitting diode display emits light toward the top or the bottom of the substrate 110 to display an image. The opaque pixel electrode 191 and the transparent common electrode 270 are applied to a top emission type organic light emitting display device that displays an image in an upward direction of the substrate 110. The opaque common electrode 270 is applied to a bottom emission organic light emitting display device that displays an image in a downward direction of the substrate 110.

Next, a method of manufacturing the organic light emitting diode display illustrated in FIGS. 2 to 4 will be described in detail with reference to FIGS. 5 to 21.

5 is a layout view at an intermediate stage of a method of manufacturing an organic light emitting diode display according to an exemplary embodiment, and FIGS. 6 and 7 are cut along the lines VI-VI and VII-VII of FIG. 5, respectively. 8 is a layout view of the next step of FIG. 5, FIGS. 9 and 10 are cross-sectional views taken along the line IX-IX and XX of FIG. 8, and FIGS. 11 and 12 are FIGS. 9 and 10. 8 is a cross-sectional view taken along line IX-IX and XX of FIG. 8, and FIG. 13 is a layout view of the next step of FIG. 8, and FIGS. 14 and 15 are XIV-XIV of FIG. 13. 16 is a cross-sectional view taken along the line XV-XV, FIG. 16 is a layout view at the next stage of FIG. 13, and FIGS. 17 and 18 are cross-sectional views taken along the line XVII-XVII and XVIII-XVIII in FIG. 16, FIG. 19 is a layout view of the next step of FIG. 16, and FIGS. 20 and 21 are cross-sectional views taken along the lines XX-XX and XXI-XXI of FIG. 19.

5 to 7, a silicon oxide or the like is deposited on the substrate 110 to form a blocking film 111. Silicon oxide is formed by chemical vapor deposition (CVD).

Thereafter, an amorphous silicon film and an insulating film are stacked on the blocking film 111, and the amorphous silicon film is crystallized by heat treatment to form a polycrystalline silicon film. The insulating film is formed of silicon nitride, silicon oxide, or the like to a thickness of 100 to 200 GPa or less. The insulating film is for protecting the surface of the amorphous silicon film and can be omitted.

Crystallization may be performed by solid phase crystallization (SPC), excimer laser annealing (ELA), or metal induced lateral crystallization (MILC), of which solid phase crystallization is preferred. .

Subsequently, the insulating layer and the polysilicon layer are patterned by a photolithography process to form the capping layer 50 and the first and second semiconductors 154a and 154b.

Next, as shown in FIGS. 8 to 10, an insulating film 60 is formed on the capping layer 50 and the substrate 110.

After the photoresist pattern PR is formed on the insulating layer 60, an opening 601 is formed in the insulating layer 60. The photoresist pattern PR is used to define a region where the data conductor is formed in a subsequent process, and the data conductor is formed in the opening 601 of the insulating layer. It is preferable to form the photoresist pattern PR about 2 to 6 times thicker than the thickness of the data conductor.

Since the photoresist pattern PR does not directly contact the first and second semiconductors 154a and 154b, the surfaces of the first and second semiconductors 154a and 154b due to the photoresist pattern PR are not contaminated.

The opening 601 may be formed and a portion of the first semiconductor 154a and the second semiconductor 154b may be removed by removing a portion of the capping layer 50 formed on the first semiconductor 154a and the second semiconductor 154b. Expose The first semiconductor 154a and the second semiconductor 154b protected by the capping layer 50 become channel portions of the thin film transistor.

Next, as shown in FIGS. 11 and 12, the doped amorphous silicon film 160 and the metal film 170 are formed on the photoresist pattern PR and the opening 601. The amorphous silicon film 160 and the metal film are preferably deposited at a low temperature so that the photoresist pattern PR is not damaged.

Since the photoresist pattern PR is thick, the amorphous silicon film 160 and the metal film 170 are connected to the side surfaces of the photoresist pattern PR and are not formed due to the step difference of the photoresist pattern PR.

Next, as shown in FIGS. 13 to 15, the photoresist pattern PR is removed to form the data line 171, the driving voltage line 172, the first and second output electrodes 175a and 175b, and the ohmic contact member 161. 162, 165a, 165b).

Since the side surface of the photoresist pattern PR is exposed, the photoresist pattern PR can be easily removed, and the doped amorphous silicon film and the metal film disposed on the photoresist pattern PR are also removed along with the photoresist pattern PR. .

In one embodiment of the present invention, the data conductor and the ohmic contact member are formed together to reduce the number of masks. However, only the doped amorphous silicon film is formed on the photoresist pattern to form the ohmic contact member, and the data contact is performed using a separate mask. Can form a sieve.

16 to 18, after the substrate 110 is heat treated, silicon nitride or silicon oxide is deposited on the substrate 110 by chemical vapor deposition to form a gate insulating layer 140. The heat treatment proceeds at a temperature of 650 ° C. or less, which prevents shrinkage of the substrate 110.

Subsequently, a metal layer is formed by depositing metal on the gate insulating layer 140 by sputtering, and patterning the second control including the gate line 121 including the first control electrode 124a and the storage electrode 127. The electrode 124b is formed.

Next, as shown in FIGS. 19 and 21, the interlayer insulating layer 180 is stacked on the gate line 121 and the second control electrode 124b and etched to form a plurality of contact holes 184, 185a, and 185b. do.

The metal layer is formed on the interlayer insulating layer 180 and then patterned to form a plurality of pixel electrodes 191 and a plurality of connection members 85.

Next, as shown in FIGS. 2 to 4, the photosensitive organic insulating layer is coated, exposed, and developed to form a partition 361 having an opening 365 on the pixel electrode 191.

The light emitting member 370 is formed in the opening 365. The light emitting member 370 may be formed by a solution process or evaporation, such as an inkjet printing method, and an inkjet printing method is preferable.

Next, a common electrode 270 is formed on the partition 361 and the light emitting member 370.

As described above, in the embodiment of the present invention, the heat conductor for forming the polysilicon film is formed, and then the data conductor and the gate conductor are formed to prevent misalignment due to shrinkage of the substrate during the crystallization heat treatment.

Next, another embodiment of the present invention will be described in detail with reference to FIGS. 22 to 24.

FIG. 22 is a layout view of an organic light emitting diode display according to another exemplary embodiment. FIG. 23 is a cross-sectional view of the organic light emitting diode display of FIG. 22 taken along a line XXIII-XXIII. FIG. 24 is a cross-sectional view of the organic light emitting diode display of FIG. 22. A cross-sectional view of the light emitting display device taken along the line XIV-XIV.

A blocking film 111 made of silicon oxide or silicon nitride is formed on an insulating substrate 110 made of transparent glass or plastic. The blocking film 111 may have a multilayer structure.

An island-like third semiconductor 154c is formed on the blocking film 111, and the third semiconductor 154c is made of polycrystalline silicon.

The capping layer 50 is formed on the third semiconductor 154c. The capping layer 50 is positioned in a predetermined region of the third semiconductor 154c, that is, a channel portion in which a channel of the thin film transistor is formed. The capping layer 50 is to protect the surface of the third semiconductor 154c and may be omitted.

An insulating layer 60 having an opening 601 is formed on the capping layer 50 and the blocking layer 111. The opening 601 defines an area in which the driving voltage line and the third control electrode, which will be described later, are formed, and exposes the third semiconductor 154c in which the capping layer 50 is not formed.

A plurality of third linear ohmic contacts 167 and a plurality of third island-type ohmic contacts 165c are formed in the openings 601 of the insulating layer 60. The ohmic contact member may be formed of the same material as in the embodiment of FIGS. 2 to 4.

The third linear ohmic contact 167 has a plurality of protrusions 163c, and the protrusions 163c and the island-like ohmic contact 165c are paired and disposed on the third semiconductor 154c.

The ohmic contacts 167 and 165c are filled in the openings 601 so that the ohmic contacts 167 and the openings 601 have the same planar pattern.

A plurality of driving voltage lines 172 and a plurality of third output electrodes 175c are formed on the ohmic contact member 167.

The driving voltage line 172 transfers a driving voltage and mainly extends in the vertical direction to overlap the third linear ohmic contact 167. Each driving voltage line 172 includes a plurality of third input electrodes 173c extending toward the third semiconductor 154c.

The third output electrode 175c is separated from the driving voltage line 172. The first input electrode 173a and the first output electrode 175a face each other on the third semiconductor 154c by overlapping the protrusion 163c and the island resistive contact member 165c.

The opening 601, the ohmic contacts 162 and 165c, the driving voltage line 172 and the third output electrode 175c have the same planar pattern.

A first gate insulating layer 140a made of silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) is formed on the insulating layer 60, the driving voltage line 172, and the third output electrode 175c.

A plurality of gate conductors including a gate line 121 including a plurality of third control electrodes 124c and a fourth control electrode 124d is formed on the first gate insulating layer 140a.

The third control electrode 124c overlaps the third semiconductor 154c and is separated from the gate line 121. The third control electrode 124c includes the storage electrode 127 extending downward and briefly changing to the right and extending upward. do. The storage electrode 127 overlaps the driving voltage line 172.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction and crosses the driving voltage line 172. Each gate line 121 includes an end portion (not shown) having a large area for connection with another layer or an external driving circuit, and the fourth control electrode 124d is connected to the fourth semiconductor (from the gate line 121). 154a). When a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The gate conductors 121 and 124c are made of copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), and titanium (Ti). Can lose. However, they may have a multilayer structure including two conductive films (not shown) having different physical properties.

Side surfaces of the gate conductors 121 and 124c are inclined with respect to the substrate 110 surface, and the inclination angle is preferably about 30 ° to about 80 °.

The second gate insulating layer 140b is formed on the gate conductors 121 and 124c. The second gate insulating layer 140b may be formed of the same material as the first gate insulating layer 140a.

A fourth semiconductor 154d overlapping the fourth control electrode 124d is formed on the second gate insulating layer 140b. The fourth semiconductor 154d may be made of polycrystalline silicon or amorphous silicon.

Fourth island-type ohmic contacts 163d and 165d are formed on the fourth semiconductor 154d. The island-like ohmic contacts 163d and 165 are separated and face each other on the fourth semiconductor 154d in pairs.

The data line 171 and the fourth output electrode 175d are formed on the ohmic contacts 163d and 165d and the second gate insulating layer 140b.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 includes a wide end portion (not shown) for connecting a plurality of fourth input electrodes 173d extending toward the fourth control electrode 124d with another layer or an external driving circuit. do. When a data driving circuit (not shown) generating a data signal is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The fourth output electrode 175d is separated from the data line 171. The fourth input electrode 173d and the fourth output electrode 175d face each other on the fourth semiconductor 154d.

The data line 171 and the fourth output electrode 175d are preferably made of a refractory metal such as molybdenum, chromium, tantalum and titanium, or an alloy thereof, and a refractory metal film (not shown) and a low resistance conductive film (not shown). May not have a multilayer structure.

The passivation layer 180 is formed on the data line 171 and the fourth output electrodes 171 and 175d.

The passivation layer 180 is made of an inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, or a low dielectric insulator. The dielectric constant of the organic insulator and the low dielectric insulator is preferably 4.0 or less. Examples of the low dielectric insulator include a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). : F, etc. can be mentioned. The passivation layer 180 may be formed by having photosensitivity among the organic insulators, and the surface of the passivation layer 180 may be flat.

A plurality of contact holes 185a exposing the fourth output electrode 175d in the passivation layer 180, and a plurality of contact holes exposing the third control electrode 124c in the passivation layer 180 and the second gate insulating layer 140b. 184, the passivation layer 180, and the first and second gate insulating layers 140a and 140b have a plurality of contact holes 185b exposing the third output electrode 175c.

A plurality of pixel electrodes 191 and a plurality of connection members 85 are formed on the passivation layer 180. These may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the third output electrode 175c through the contact hole 185b, and the connection member 85 is connected to the third control electrode 124c through the contact holes 184 and 185a. And the fourth output electrode 175d.

2 through 4, a partition 361 having a opening 365 and a common electrode 270 are formed on the pixel electrode 191.

As described above, the present invention can form a data wire by lifting off the photosensitive film pattern to form a data conductor of an accurate size. In addition, by protecting the channel portion of the thin film transistor with a capping layer, it is possible to prevent the surface of the channel portion from being damaged during etching.

Therefore, a high quality organic light emitting display device having excellent interfacial properties can be provided.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

Claims (13)

First and second semiconductors formed on a substrate, An insulating layer formed on the first semiconductor and the second semiconductor and including an opening exposing the first semiconductor and the second semiconductor; An ohmic contact formed in the opening; A data line having a first input electrode, a driving voltage line having a second input electrode, first and second output electrodes formed on the ohmic contact member; A gate insulating film formed on the data line, driving voltage line, first and second output electrodes, A gate line and a second control electrode including a first control electrode formed on the gate insulating layer; A protective film formed on the gate line and the second control electrode; A first electrode formed on the protective film, A light emitting member formed on the first electrode, A second electrode formed on the light emitting member; And the ohmic contact is buried in the opening and has the same planar pattern as the opening. In claim 1, The data line, the driving voltage line, the first and second output electrodes are embedded in the opening and have the same planar pattern as the ohmic contact member. In claim 1, The first input electrode and the first output electrode face each other on the first semiconductor with respect to the first control electrode, The second input electrode and the second output electrode face each other on the second semiconductor with respect to the second control electrode. In claim 3, And a capping layer formed on the first and second semiconductors and disposed between the first input electrode and the second output electrode and between the second input electrode and the second output electrode. . In claim 1, And the first semiconductor and the second semiconductor are made of polycrystalline silicon. A first semiconductor formed on a substrate and made of polycrystalline silicon, An insulating layer formed on the first semiconductor and including first and second openings exposing the first semiconductor; First and second ohmic contacts formed in the first and second openings, respectively, A driving voltage line formed on the first ohmic contact and having a first input electrode and a first output electrode formed on the second ohmic contact; A first gate insulating layer formed on the driving voltage line and the first output electrode, A first control electrode formed on the first gate insulating layer and overlapping the first semiconductor, A gate line formed on the first gate insulating layer and crossing the driving voltage line and having a second control electrode; A second gate insulating film formed on the gate line and the first control electrode, A second semiconductor formed on the second gate insulating layer and overlapping the second control electrode; Third and fourth ohmic contacts overlapping and separated from the second semiconductor; A data line formed on the third ohmic contact and having a second input electrode, a second output electrode formed on the fourth ohmic contact, A protective film formed on the data line and the second output electrode, A first electrode formed on the protective film, A light emitting member formed on the first electrode, A second electrode formed on the light emitting member; And the ohmic contact is buried in the opening and has the same planar pattern as the opening. In claim 6, The driving voltage line and the first output electrode are embedded in the opening to have the same planar pattern as the first and second ohmic contacts. In claim 6, And the second semiconductor is made of amorphous silicon or polycrystalline silicon. In claim 6, And a capping layer formed on the first semiconductor and positioned between the first output electrode and the first input electrode. Forming a first semiconductor and a second semiconductor on the substrate, Forming an insulating layer on the first and second semiconductors, Forming the photoresist pattern on the insulating layer; Forming an insulating layer including first and second openings exposing the first semiconductor and third and fourth openings exposing the second semiconductor by using the photoresist pattern as a mask; Forming an amorphous silicon film and a metal film doped with impurities in the photoresist pattern and the first to fourth openings; Removing the photoresist pattern to form an ohmic contact, a data line, a driving voltage line, a first output electrode and a second output electrode in the first to fourth openings; Forming a gate insulating layer on the data line, the driving voltage line, the first output electrode, and the second output electrode; Forming a gate line including a first control electrode overlapping the first semiconductor and a second control electrode overlapping the second semiconductor on the gate insulating layer; Forming a passivation layer on the gate line and the second control electrode; Forming a connecting member connecting the first output electrode and the second control electrode on the passivation layer, and a first electrode connected to the second output electrode; Forming a light emitting member on the first electrode, and Forming a second electrode on the light emitting member Method of manufacturing an organic light emitting display device comprising a. In claim 10, And forming the photoresist pattern thicker than the doped amorphous silicon layer and the metal layer. In claim 10, Forming the first semiconductor and the second semiconductor, Forming an amorphous silicon film on the substrate, Solid crystallizing the amorphous silicon film to form a polycrystalline silicon film, And patterning the polycrystalline silicon layer. In claim 12, And forming a capping layer on the amorphous silicon film.

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