KR20080054067A - Display device - Google Patents

Abstract

A display device is provided to apply the data voltage of black to a predetermined pixel row at every frame in the RVA(Rubbed Vertical Alignment) mode, thereby removing the afterimage. A display substrate(300) includes plural pixel groups having plural pixel rows. A gate driving member(400) supplies the gate signal to the pixel rows. A data driving member(500) applies the data voltage corresponding to the black to the pixel rows with a predetermined number among each pixel group during one frame. The data driving member supplies the data voltage corresponding to the black to the different pixel rows with a predetermined number of each pixel group at every frame. The data driving member applies the data voltage corresponding to the black at every group with a different order. The continuous two pixel groups receive the data voltage by the opposite order. A gray voltage generator(800) generates two pairs of gray voltage sets related to pixel transmissivity.

Description

Display device {DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3A and 3B are cross-sectional views illustrating alignment of liquid crystals in the liquid crystal panel assembly.

4 is a signal waveform diagram illustrating an operation of a liquid crystal display according to an exemplary embodiment of the present invention.

The present invention relates to a display device.

In recent years, with the reduction in weight and thickness of personal computers and televisions, display devices are also required to be lighter and thinner, and cathode ray tubes (CRTs) are being replaced by flat panel displays.

Such flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), organic light emitting displays, plasma display panels (PDPs), and the like. There is this.

In general, in an active matrix flat panel display, a plurality of pixels are arranged in a matrix form, and an image is displayed by controlling the light intensity of each pixel according to given luminance information. Among them, the liquid crystal display includes two display panels including a pixel electrode and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The liquid crystal display device applies an electric field to the liquid crystal layer, and adjusts the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image.

On the other hand, the liquid crystal display device has a variety of modes according to the alignment state of the liquid crystal, among which the RVA mode is a mode used by rubbing the liquid crystal of the general VA mode, a high viewing angle and high contrast ratio is widely used in high-quality mobile products.

However, in the case of the RVA mode, unlike after the normal VA mode, rubbing occurs in the region where the direction of the electric field and the rubbing direction do not coincide.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of eliminating an afterimage.

According to an aspect of the present invention, there is provided a display device including a display panel including a plurality of pixel groups having a plurality of pixel rows, a gate driver configured to supply a gate signal to the pixel rows, and each of the pixels for one frame. And a data driver for applying a data voltage corresponding to black to a predetermined number of pixel rows in the pixel group.

The data driver may supply the data voltage corresponding to black to a predetermined number of different pixel rows of each pixel group for each frame.

The number of pixel rows displaying black in one frame may satisfy the following equation.

X ㅧ G = N / F

(X is the number of pixel rows representing black in each group, G is the number of pixel groups, N is the total number of pixel rows, and F is the frame frequency.)

The data driver may apply the data voltage corresponding to black in a different order for each pixel group.

Two consecutive pixel groups may receive a data voltage corresponding to the black to the pixel row in a reverse order.

The pixel row may include a plurality of pixels in an RVA mode.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel in the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data voltage ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, is connected to the i-th (i = 1, 2, ..., n) gate line G _i and the j-th (j = 1, 2, ..., m) data line D _j . The pixel PX includes a switching element Q connected to the signal lines G _i and D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst. The thin film transistor may include polycrystalline silicon or amorphous silicon.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary role of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike in FIG. 2, the color filter 230 may be disposed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value. The number of gray voltages included in the set of gray voltages generated by the gray voltage generator 800 may be the same as the number of grays that the liquid crystal display can display.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed of a combination of the gate on voltage Von and the gate off voltage Voff. ₁ -G _n ).

Data driver 500 is connected with the data lines (D ₁ -D _m) of the liquid crystal panel assembly 300, select a gray voltage from the gray voltage generator 800 and the data lines do this as a data voltage (D ₁ -D _m ).

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 is integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor Q. May be Alternatively, these driving devices 400, 500, 600, 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP), or may be mounted on a separate printed circuit board (not shown). In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 applies an analog data voltage to the horizontal synchronizing start signal STH and the data lines D ₁ -D _m indicating the start of transmission of the digital image signal DAT for one row of pixels PX. Includes a load signal LOAD and a data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the analog data voltage relative to the common voltage Vcom (hereinafter referred to as " polarity of the data voltage " RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixel PX in one row and corresponds to each digital image signal DAT. By selecting the gray scale voltage, the digital image signal DAT is converted into an analog data voltage and then applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data voltage applied to the data lines D ₁ -D _m is applied to the pixel PX through the turned-on switching element Q.

The difference between the voltage of the data voltage applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in the transmittance of light by a polarizer attached to the display panel assembly 300, whereby the pixel PX displays the luminance represented by the gray level of the image signal DAT.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied, and the data voltage is applied to all the pixels PX to display an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data voltage applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarities of the data voltages flowing through one data line may be changed (eg, row inversion and point inversion), or polarities of data voltages applied to one pixel row may be different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

Hereinafter, the arrangement of the liquid crystal layer 3 in a rubbed vertical arraignment (RVA) mode will be described with reference to FIGS. 3A and 3B.

3A is a diagram showing the alignment state of the liquid crystal before voltage is applied, and FIG. 3B is a diagram showing the alignment state of the liquid crystal after voltage is applied.

Referring to FIG. 3A, the lower panel 100 includes a pixel electrode 191 on the lower substrate 110, and the pixel electrode 191 is a transparent conductive material such as ITO or IZO, aluminum, silver, chromium, or an alloy thereof. It may be made of a reflective metal such as.

In addition, the upper panel 200 includes a common electrode 270 on the upper substrate 210, and the common electrode 270 is made of a transparent conductor such as ITO or IZO.

Inner surfaces of the display panels 100 and 200 are coated with horizontal alignment layers 11 and 21 which are rubbed in the same direction.

The pixel electrode 191 is connected to the switching element Q to receive a data voltage. The pixel electrode 191 to which the data voltage is applied generates an electric field together with the common electrode 270 of the upper panel 200 to which the common voltage is applied, thereby generating an electric field between the two electrodes 191 and 270. The direction of the liquid crystal molecules 31 of the liquid crystal layer 3 is determined. The polarization of light passing through the liquid crystal layer 3 varies according to the direction of the liquid crystal molecules 31 determined as described above.

In this case, the liquid crystal molecules 31 constituting the liquid crystal layer 3 have negative dielectric anisotropy and have a long axis of the liquid crystal molecules 31 arranged perpendicular to the substrates 110 and 210 as a vertical arraignment (VA) mode.

Referring to FIG. 3A, the liquid crystal molecules 31 near the two alignment layers 11 and 21 are vertically aligned with a pretilt angle in which one end is inclined toward the rubbing direction without applying the data voltage.

In this state, when a data voltage is applied to the pixel electrode 191 and an electric field is applied to the liquid crystal layer 3, the liquid crystal molecules 31 are inclined perpendicular to the direction of the electric field.

However, the liquid crystal molecules 31 are inclined in opposite directions with respect to the electric field formed toward the common electrode 270 near the boundary of the pixel electrode 191, and the liquid crystal molecules 31 in one direction are in the same direction as the rubbing direction. The liquid crystal molecules 31 inclined in the inclined direction are inclined in the direction opposite to the rubbing direction.

As described above, the liquid crystal molecules 31 in the region in which the rubbing direction and the electric field are opposite to each other do not return to the initial state after the electric field disappears.

Since such an afterimage disappears within 1 second, it is not visually recognized. Thus, the afterimage is removed by applying a voltage for turning the liquid crystal molecules 31 to an initial state.

Hereinafter, referring to FIG. 4, a driving method of the liquid crystal display device capable of controlling afterimages will be described.

As shown in FIG. 4, a black data voltage is applied to all pixel rows of the liquid crystal panel assembly 300 within one second to remove an afterimage.

To this end, the plurality of pixels PX of the liquid crystal panel assembly 300 are divided into a plurality of pixel groups GR1 -GRk based on rows.

Each pixel group GR1-GRk includes the same number of pixel rows, where the number of pixel groups GR1-GRk and the number of pixel rows of each pixel group GR1-GRk are determined by the frame frequency and the total number of pixel rows. It depends on the number.

That is, when the frame frequency is f and the number of all pixel rows is n, the number x of pixel rows that should display black in one pixel group GR1-GRk during one frame satisfies the following equation.

x ㅧ k = n / f

For example, if the frame frequency f is 60 Hz and the number n of all pixel rows is 240, the image displayed in one second is 60 frames, and the number of pixel rows displaying black for each frame (x) K) is 4, so it is divided into an appropriate number of pixel groups GR1-GRk.

For example, when the number of pixel groups GR1-GRk is 4 (k = 4), each pixel group GR1-GRk includes one pixel row displaying black in one frame.

The pixel rows of each pixel group GR1-GRk receive black data voltages from the data driver 500 alternately in a predetermined order for each frame to display black.

The liquid crystal molecules 31 in the pixel row supplied with the black data voltage in the corresponding frame return to the initial state by disappearing the electric field according to the black data voltage.

All of the pixel groups GR1 -GRk may display black continuously from the top pixel row for each frame.

On the other hand, when all the pixel groups GR1-GRk display black in the same order, the screen shake phenomenon may be recognized by the harmonic.

Therefore, each pixel group GR1-GRk may display black in a different order.

That is, the odd-numbered pixel groups GR1, CR3, ,,, move upward by displaying black from the bottom pixel row as shown in FIG. 4, and the even-numbered pixel groups GR2, GR4, ..., from the top pixel row. You can proceed down by marking black.

As described above, according to the present invention, an afterimage can be removed by applying a black data voltage to a predetermined pixel row in each frame in the RVA mode.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (6)

A display panel including a plurality of pixel groups having a plurality of pixel rows, A gate driver supplying a gate signal to the pixel row, and A data driver which applies a data voltage corresponding to black to a predetermined number of pixel rows of each pixel group during one frame. Display device comprising a. In claim 1, The data driver And the data voltage corresponding to black to a predetermined number of different pixel rows of each pixel group every frame. In claim 2, The number of pixel rows displaying black in one frame satisfies the following equation. X ㅧ G = N / F (X is the number of pixel rows representing black in each group, G is the number of pixel groups, N is the total number of pixel rows, and F is the frame frequency.) In claim 3, The data driver And applying the data voltage corresponding to black in different order for each pixel group. In claim 4, And two consecutive pixel groups are applied with a data voltage corresponding to the black to the pixel row in a reverse order. In claim 5, The pixel row includes a plurality of pixels in an RVA mode.

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