KR20080054064A - Driving apparatus for display device, display device including the same and driving method of display device - Google Patents

Abstract

A driving device for a display apparatus, a display apparatus including the same, and a method of driving the display apparatus are provided to reduce EMI(Electromagnetic Interference) by processing signals inputted from a signal controller using a spread spectrum scheme. A driving device for a display apparatus includes receivers(610), spread spectrum clock(910), and dual port memories(920). The receivers receive image data inputted from outside. The spread spectrum clock receive clock of the received image data, modify the clock of the received image data with a range, and output the modified clock. The dual port memories modify the clock of the image data received at the receiver using the modified clock and modifies/output the clock of the image data.

Description

A driving device of a display device, a display device including the same, and a driving method of the display device {DRIVING APPARATUS FOR DISPLAY DEVICE, DISPLAY DEVICE INCLUDING THE SAME AND DRIVING METHOD OF DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a diagram illustrating in detail a signal controller according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a structure of a dual port memory according to an embodiment of the present invention.

5 is a timing diagram of a modified clock generator and a dual port memory according to an embodiment of the present invention.

6 is a graph illustrating EMI measurements of a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

191: pixel electrode 200: upper display panel

230: color filter 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: data driver 600: signal controller

610: receiver 620: ACC unit

630: data compression unit 640: memory control unit

650: DCC unit 660: output unit

670: control signal generator 680: abnormal signal generator

685: oscillator 690: Y pyrom control unit

700: driving voltage generator 800: gray voltage generator

900: frame memory 910: quartz clock generator

920: dual port memory 950: Ypyrom

The present invention relates to a driving device of a display device, a display device including the same, and a method of driving the display device.

Recently, organic light emitting diode display (OLED), plasma display panel (PDP), liquid crystal display (LCD), instead of heavy and large cathode ray tube (CRT) A flat panel display such as) is being actively developed.

The PDP is a device for displaying characters or images using plasma generated by gas discharge, and the organic light emitting diode display displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display device applies an electric field to a liquid crystal layer interposed between two display panels, and adjusts the intensity of the electric field to adjust a transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among such flat panel display devices, for example, a liquid crystal display device has a signal control unit for processing a signal to display an image, and a signal controlled by the signal control unit is applied to the wiring of the liquid crystal display panel to display an image. The signal applied to the liquid crystal display panel generally has a frequency of 60 Hz or 120 Hz and electromagnetic waves are generated due to this signal.

Recently, electromagnetic magnetic interference (EMI) is an important factor among the characteristics of liquid crystal displays, and there are various methods of reducing EMI. In some cases, the circuit is shielded to reduce EMI, but in this case, a separate component is added to increase manufacturing cost and processing time of the display device.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a driving device, a display device including the same, and a driving method of the display device, the device of which the EMI is reduced by simply changing the signal characteristics.

In order to solve this problem, the present invention changes a clock of a signal input to a signal controller to process a signal according to a changed clock in the entire signal controller, and controls a display device according to a signal whose clock is changed.

Specifically, the driving apparatus of the display apparatus according to the exemplary embodiment of the present invention is a driving apparatus of a display apparatus including a plurality of pixels each including a switching element, the receiving unit receiving image data input from the outside, and the received image. A correction clock generator which receives a clock of data clk and changes it within a predetermined range and outputs a changed clock clk_ss, and changes the clock of the image data received to the receiver by using the changed clock clk_ss. It includes dual port memory output.

The correction clock generator generates a modified clock (clk_ss) while changing a clock larger or smaller than the input clock (clk) within a predetermined range around a clock (clk) of the received image data according to a predetermined period. The clock can be changed in a spread spectrum manner.

The apparatus may further include an ACC unit for processing a signal output from the dual port memory, and a DCC unit for comparing and processing the ACC processed signal of the existing frame with the ACC processed signal of the current frame.

The ACC unit and the DCC unit may process a signal according to the changed clock clk_ss.

The data compression unit, a memory controller, and a frame memory may be further included to store the ACC processed signal of the existing frame.

The display device according to the exemplary embodiment of the present invention includes the driving device.

A method of driving a display device according to an exemplary embodiment of the present invention includes receiving image data received from the outside to a receiver of a signal controller; A correction clock generation unit receiving a clock (clk) of the received image data from the receiving unit and changing a predetermined range within a predetermined range and outputting the changed clock (clk_ss) to the dual port memory; The dual port memory receiving and storing the received image data from the receiving unit and correcting and outputting the image data to have a changed clock (clk_ss) received from the correction clock generator; And displaying the image by processing the corrected image data with the changed clock (clk_ss).

The correcting clock generator may receive the clock clk of the received image data from the receiver, change it within a predetermined range, and output the changed clock clk_ss to the dual port memory. The clock may be changed by a spread spectrum method that generates the changed clock clk_ss while changing a clock larger or smaller than a clock clk inputted within a predetermined range with a predetermined period.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2, and a liquid crystal display device will be described as an example.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of signal lines G1 -Gn and D1 -Dm and a plurality of pixels PX connected to the plurality of signal lines G1 -Gn and D1 -Dm and arranged in a substantially matrix form. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G1 -Gn and D1 -Dm include a plurality of gate lines G1 -Gn for transmitting a gate signal (also called a "scan signal") and a plurality of data lines D1 -Dm for transmitting a data signal. do. The gate lines G1 -Gn extend substantially in the row direction and are substantially parallel to each other, and the data lines D1 -Dm extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, a pixel PX connected to an i-th (i = 1, 2, n) gate line Gi and a j-th (j = 1, 2, m) data line Dj. The switching element Q includes a switching element Q connected to a signal line Gi Dj, a liquid crystal capacitor CLC, and a storage capacitor CST connected thereto. The holding capacitor CST can be omitted as necessary.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100. The control terminal is connected to the gate line Gi, and the input terminal is connected to the data line Dj. The output terminal is connected to the liquid crystal capacitor CLC and the storage capacitor CST.

The liquid crystal capacitor CLC has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor CST, which serves as an auxiliary part of the liquid crystal capacitor CLC, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor CST may be formed by the pixel electrode 191 overlapping the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the driving voltage generator 700 generates the driving voltage AVDD and provides the driving voltage AVDD to the gate signal generator 750, but also the gray voltage generator 800.

The gray voltage generator 800 receives the driving voltage AVDD to generate two sets of gray voltages (or a reference gray voltage set) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The gate driver 400 is integrated in the liquid crystal panel assembly 300, and is connected to the gate lines G1 -Gn of the liquid crystal panel assembly 300 to be connected to the gate-on voltage Von from the gate signal generator 750. A gate signal composed of a combination of the gate off voltages Voff is applied to the gate lines G1 -Gn.

The data driver 500 is connected to the data lines D1 -Dm of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data lines D1 -Dm as data signals. To apply. However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like. The structure and operation of the signal controller 600 will be described later.

Each of the driving circuits 500, 600, and 800 except the gate driver 400 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film ( It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, the driving circuits 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G1 -Gn, D1-Dm, and the thin film transistor switching element Q. In addition, the driving circuits 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 includes a horizontal synchronizing start signal STH indicating the start of image data transmission for one row of pixels PX and a load signal LOAD for applying a data signal to the data lines D1 -Dm. The data clock signal HCLK is included. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixel PX in one row and corresponds to each digital image signal DAT. By selecting the gray scale voltage, the digital image signal DAT is converted into an analog data signal and then applied to the corresponding data lines D1 -Dm.

The gate driver 400 applies a gate-on voltage Von to the gate lines G1 -Gn according to the gate control signal CONT1 from the signal controller 600, and is connected to the gate lines G1 -Gn. Turn on (Q). Then, the data signal applied to the data lines D1 -Dm is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor CLC, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE) to all the gate lines G1 -Gn. In response to the gate-on voltage Von, a data signal is applied to all the pixels PX to display an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarities of the data signals flowing through one data line are changed (eg, row inversion and point inversion) according to the characteristics of the inversion signal RVS within one frame, or the polarities of data signals applied to one pixel row are also different from each other. Can be different (eg invert columns, invert points).

Hereinafter, the signal controller 600 will be described in detail.

3 is a diagram illustrating in detail a signal controller according to an exemplary embodiment of the present invention.

The signal controller 600 according to an exemplary embodiment of the present invention includes a receiver LVDS Rx 610, a modified clock generator S910 [910], a dual port memory 920, an ACC unit 620, and data. A compression unit 630, a memory controller 640, a DCC unit 650, an output unit 660, a control signal generator 670, an error signal generator 680, an oscillator 685, An ipyrom control unit i2c_con 690 includes a frame memory DDR 900 and an EEPROM 950.

Each part is as follows.

The receiver LVDS Rx 610 is a part that receives the LVDS signal. Rx stands for receiving, and LVDS stands for Low Volatge Differential signaling, which means an interface standard for high-speed data transmission using low voltage differential signaling. The LVDS method can send digital information to the display device at high speed and uses low voltage, so it consumes less power and has excellent noise characteristics. Unlike the present embodiment, it is also possible to use a standard other than the LVDS method.

The modified clock generator (SSC [spread spectrum clock]: 910) outputs the changed clock (clk_ss) by changing the input clock (clk). The method for generating the changed clock (clk_ss) is generated by changing a clock larger or smaller than the input clock (clk) according to a predetermined period with respect to the input clock (clk). The range and period of changing the clock vary depending on the embodiment.

The dual port memory 920 stores data according to the clock clk received in the embodiment of the present invention and then outputs data changed according to the clock clk_ss changed by the correction clock generator 910. Operations of the crystal clock generator 910 and the dual port memory 920 will be described later with reference to FIGS. 4 and 5.

In the present embodiment, the receiver 610, the crystal clock generator 910, and the dual port memory 920 are configured in pairs (odd [odd] and even [even] sides). It may be separated into three or more pairs.

The ACC unit 620 performs adaptive color correction (ACC) and corrects colors by independently modifying gamma curves of R, G, and B. As a result, the number of bits of the data to be input is converted to the number of bits (generally larger bits) and output. The ACC unit 620 of the present embodiment reduces the number of bits increased through ACC processing through dithering to make the number of bits of the input data and the number of bits of the output data constant.

The data compression unit 630 and the memory control unit 640 may exchange digital image signals with the frame memory (DDR) 900. That is, the input data is compressed using the data compressor 630, and the memory controller 640 transmits or reads the compressed digital image data to the frame memory 900. In general, the memory controller 640 reads compressed digital image data of all frames stored in the frame memory 900, and stores the compressed digital image data of the current frame in the frame memory 900. Compressed digital image data is generally output after decompression for subsequent processing.

The data compression unit 630, the memory control unit 640, and the frame memory unit 900 store and read digital image data of an existing frame required by the DCC unit 650 in the frame memory 900. This is the part to come.

The DCC unit 650 performs dynamic capacitance compensation (DCC) processing. The DCC unit 650 compares the digital image data applied to the existing frame with the digital image data applied to the current frame and compares the voltage applied to the pixel to the current frame. It is a method to reduce charging time by correcting image data. The DCC converts one frame of digital image data (forwardly referred to as "current image data (gN)") for an arbitrary pixel PX into the digital image gator of the immediately preceding frame for that pixel PX [forward]. Current digital image data corrected on the basis of " previous image data (gN-1) " " first modified image data (gN ') " To make it. The first corrected image data gN 'is basically determined by the experimental result, and the difference between the first corrected image data gN' and the previous image data gN-1 is the current image data gN before the correction and the previous image. It is generally larger than the difference of the data gN-1.

In order to perform the correction of the image data, a memory space for storing the image data gN-1 of the previous frame is required, and the frame memory 900 plays such a role. In addition, a lookup table that stores the relationship between the current image data gN and the first corrected image data gN 'according to the previous image data gN-1 is required.

The image data processed as described above is output to the outside (such as the data driver 500) through the output unit 660. In FIG. 3, the output of the output unit 660 is divided into right data and left data. The display device according to the present embodiment is divided into two divisions, that is, left and right sides of the panel. This is because the data is input separately. The reason for using the two-division display device is that the size of the display device is large, which makes it difficult to process data integrally. However, the embodiment may be divided into four divisions or the like.

The above shows a procedure of processing and outputting image data input from the outside. Here, when the clocks of the image data signals processed by the respective parts of the signal controller 600 are examined, all except the receiver 610 have the changed clock clk_ss.

In addition to the image data, the control signal and the set default value are processed in the following places of the signal controller 600.

First, the control signal is processed through the control signal generator 670. The clock on which the control signal is processed also uses the changed clock (clk_ss).

On the other hand, the abnormal signal generator 680 transmits a signal to the control signal generator 670 and the output unit 660 so as to process when the image is difficult to display, such as when there is no input signal or there is an error in the input signal. do. The signal of the abnormal signal generator 680 is generated based on the signal generated by the oscillator 685.

Meanwhile, the default value of the display device is stored in the Y pyrom 950, and the Y pyrom control unit 690 may bring the default value stored in the Y pyrom 950 to be used in data processing. In the present embodiment, the ACC unit 620, the DCC unit 650, the output unit 660 and the control signal generator 670 is shown to use the default value provided by the YPIROM 950 control unit, Other embodiments are also possible.

As described above, the signal controller 600 according to the exemplary embodiment of the present invention has been described.

Hereinafter, a modified clock generator and a dual port memory will be described.

4 is a diagram illustrating a structure of a dual port memory according to an embodiment of the present invention, and FIG. 5 is a timing diagram of a modified clock generator and a dual port memory according to an embodiment of the present invention.

4 is a diagram illustrating a structure of the dual port memory 920. The dual port memory 920 has a structure in which data is written through two ports A and B, and output is performed together.

5 is a timing diagram of the modified clock generator 910 and the dual port memory 920 according to the present invention.

The top two timing diagrams of FIG. 5 show a data enable (DE) signal and line data. As shown in FIG. 5, a blank section in which line data is not applied is present in a section in which the DE signal is not applied.

The third and fourth timing diagrams of FIG. 5 show timing diagrams and clock clk signals of a write enable (WEN) signal for writing data to the dual port memory 920. The WEN signal has the same period as the DE signal but is set to be written when the signal is low. At this time, the clock has the same clock clk as the clock input to the signal controller 600 from the outside.

Meanwhile, the fifth to eighth timing diagrams of FIG. 5 show timing diagrams for reading and outputting data stored in the dual port memory 920. At this time, the clock used is a modified clock (clk_ss), the transformed clock is used to receive the input generated by the modified clock generator 910.

The RDEN (read enable) signal is applied to be shifted by the changed clock clk_ss. Accordingly, the line data line read and output from the dual port memory 920 is shown in the seventh timing diagram. Accordingly, the modified DE signal DE 'is shifted by ΔT according to the changed clock clk_ss as in the last timing diagram.

As described above, the clock clk_ss changed through the modified clock generator 910 and the dual port memory 920 is used as a standard clock in the following parts (each part in the signal controller, the gate driver and the data driver).

EMI generated when the changed clock clk_ss is used as shown in FIG. 6.

6 is a graph illustrating EMI measurements of a liquid crystal display according to an exemplary embodiment of the present invention.

Fig. 6 shows EMI peak values according to the cycle of the present embodiment using the changed clock. The horizontal axis in the diagram is frequency, and the vertical axis represents EMI values. On the other hand, the horizontal line shown in Figure 6 is the EMI value required by the display device according to the embodiment of the present invention it can be seen that there is no problem due to the EMI value is low EMI value.

Hereinafter, a driving method of the display device according to the present invention will be described.

Image data received from the outside is input to the receiver 610 of the signal controller 600. Meanwhile, the modified clock generator 910 generates a modified clock clk_ss by changing the clock clk transmitted from the received image data and outputs the changed clock clk_ss to the dual port memory 920. Meanwhile, the dual port memory 920 receives and stores the image data received by the receiver 610 and then outputs the modified image data having the changed clock clk_ss by the modified clock generator 910.

The corrected output image data is processed in each part of the signal controller 600 and output to the data driver 500 to display an image.

As described above, the EMI value of the display device may be reduced by transforming the input clock into a spread spectrum method and processing the signal input to the signal controller using the modified clock. In addition, since the EMI value can be reduced without adding a separate device, the manufacturing cost of the display device can be reduced, and the manufacturing time can be shortened.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (8)

A driving device of a display device including a plurality of pixels each including a switching element, Receiving unit for receiving the image data input from the outside, A correction clock generator which receives the clock (clk) of the received image data, changes it within a predetermined range, and outputs the changed clock (clk_ss); And a dual port memory configured to change and output a clock of the image data received to a receiver by using the changed clock (clk_ss). In claim 1, The correction clock generator generates a modified clock (clk_ss) while changing a clock larger or smaller than the input clock (clk) within a predetermined range around a clock (clk) of the received image data according to a predetermined period. A driving device of a display device that changes a clock in a spectrum manner. In claim 1, An ACC unit for processing a signal output from the dual port memory; And a DCC unit configured to compare and process the ACC processed signal of the existing frame with the ACC processed signal of the current frame. In claim 3, And the ACC unit and the DCC unit process signals according to the changed clock (clk_ss). In claim 3, To store the ACC processed signal of the existing frame, And a data compressor, a memory controller, and a frame memory. A display device comprising the driving device of any one of claims 1 to 5. Receiving image data received from the outside to the receiving unit of the signal controller; A correction clock generation unit receiving a clock (clk) of the received image data from the receiving unit and changing a predetermined range within a predetermined range and outputting the changed clock (clk_ss) to the dual port memory; The dual port memory receiving and storing the received image data from the receiving unit and correcting and outputting the image data to have a changed clock (clk_ss) received from the correction clock generator; And And displaying the image by processing the corrected image data with the changed clock (clk_ss). In claim 7, The correcting clock generator may receive the clock clk of the received image data from the receiver, change the signal within a predetermined range, and output the changed clock clk_ss to the dual port memory. Spread Spectrum which generates the modified clock clk_ss while changing a clock larger or smaller than the input clock clk within a predetermined range around the clock clk of the received image data according to a predetermined period. A method of driving a display device that changes a clock in a manner.

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