KR20080051637A - Shift register - Google Patents

Abstract

A shift register is provided to enhance aperture rates without adding sensing lines by implementing a sensing circuit for detecting coordinates of touch position in the shift register. A shift register includes plural stages for outputting sequentially gate on/off signals. Each of the stage includes an input unit(100), an output unit(200), pull-up and pull-down drivers(300,400), a sensing unit(600), and a gate off unit. The input unit receives a first carry signal and outputs a control signal. The output unit, which is connected to the input unit, outputs the gate on/off signal and a second carry signal according to the first clock and control signals. The pull-up driver is driven by the first clock signal. The pull-down driver, which is connected to the input unit, the output unit, and the pull-up driver, is driven by the first and second clock signals and a gate on/off signal of an (n+1)-th stage. The sensing unit outputs a sensing signal corresponding to a touch position according to the gate on/off signal. The gate off unit outputs an off signal according to the gate on/off signal of the (n+1)-th stage.

Description

Shift register

1 is an example of a block diagram showing a shift register according to a first embodiment of the present invention.

2 is an internal circuit diagram of the j-th stage according to the first embodiment of the present invention.

3 is an internal circuit diagram of the j-th stage according to the second embodiment of the present invention.

4 is an internal circuit diagram of the j-th stage according to the third embodiment of the present invention.

5 is an internal circuit diagram of the j th stage according to the fourth embodiment of the present invention.

6 is an internal circuit diagram of the j th stage according to the fifth embodiment of the present invention.

7 is an internal circuit diagram of the j-th stage according to the sixth embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10: shift register 100: input

200: output unit 300: pull-up driving unit

400: pull-down drive part 500: gate off part

600: sensing unit

The present invention relates to a shift register, and more particularly, to a shift register capable of improving the aperture ratio and accurately detecting the coordinates of a touch point.

There are various types of displays that display images, such as cathode ray tubes, liquid crystal displays, plasma display panels, and the like. In order to easily input the input information on the screen, such displays are used as an input device by installing a touch panel for inputting information corresponding to the position when the user presses the surface with a pen or finger.

In order to cope with thickness and size problems of the touch panel, a liquid crystal display device having a touch panel is being developed. In a liquid crystal display including a touch panel, when a pressure is applied from the outside, a sensing transistor that senses coordinates of a touch point is formed for each unit pixel, thereby reducing the aperture ratio.

In addition, when the sensing transistor is formed for each unit pixel, the common voltage is distorted due to the coupling between the pixel electrode formed on the thin film transistor array panel and the common electrode formed on the common electrode display panel. Every time the applied data voltage changes, the common voltage is severely distorted. As a result, a distorted common voltage is provided to the comparator through the sensor line, and the sensor misjudges the relative polarity of the two signals, so that the external pressure is applied or the external pressure is applied when no pressure is applied from the outside. In this case, the coordinate signal of the touch point is unknown.

An object of the present invention is to provide a shift register that can improve the aperture ratio and accurately detect the coordinates of a touch point.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

The shift register according to an embodiment of the present invention for achieving the technical problem is a shift register including n stages for sequentially outputting a gate on / off signal, each stage receives a first carry signal An input unit for outputting a control signal, an output unit connected to the input unit and outputting the gate on / off signal and the second carry signal according to a first clock signal and the control signal, and a pull-up driving unit operating on the first clock signal A pull-down driving unit connected to the input unit, the pull-up driving unit, and the output unit and operating according to the first clock signal, the second clock signal, and a gate on / off signal of the (n + 1) th stage; The sensing unit outputs a sensing signal corresponding to a touch point according to the off signal and the gate on / off signal of the (n + 1) th stage. And a gate off part for outputting a pre-signal.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an example of a block diagram illustrating a shift register according to an embodiment of the present invention.

Referring to FIG. 1, the shift registers 10 are dependently connected to each other, and a plurality of stages ST ₁ ,... Which sequentially output gate on / off signals Gout ₁ ,..., Gout _{(n + 1)} . , ST _{n +1} ), and a gate-off voltage Voff, a first clock signal CKV, a second clock signal CKVB, and an initialization signal INT are input. All stages except the last stage ST _{n +1} are connected one-to-one with a gate line (not shown) of the liquid crystal panel (not shown).

Each stage ST ₁ , ..., ST _{n +1} includes a first clock terminal CK1, a second clock terminal CK2, a set terminal S, a reset terminal R, a power supply voltage terminal GV, and a frame. It has a reset terminal FR, a gate output terminal OUT1 and a carry output terminal OUT2 and a sensing output terminal OUT3.

The carry signal Cout _(j-1) of the front stage ST _j-1 is provided to the set terminal S of each stage ST1, ..., STn + 1, for example, the j-th stage ST _j . The gate on / off signal Gout _{(j + 1} ) of the rear stage ST _{j +1} is input to the reset terminal R, and the first clock terminal CK1 and the second clock terminal CK2 are input to the reset terminal R. The first clock signal CKV and the second clock signal CKVB are input, an initialization signal INT is input to the power supply voltage terminal GV, and a gate off voltage Voff is input to the frame reset terminal FR. . The gate output terminal OUT1 outputs the gate on / off signal Gout _(j) , the carry output terminal OUT2 outputs the carry signal Cout _(j-1) , and the sensing output terminal OUT3 is output. The sensing signal Sout _(j ) is output. A final stage carry signal _{(Cout (n + 1))} of the _{(n +1} ST) is provided for each stage (ST1, ..., STn + 1 ) as an initialization signal.

However, the scan start signal STV is input to the first stage ST ₁ instead of the front carry signal, and the scan start signal STV is input to the last stage ST _{n +1} instead of the rear gate on / off signal.

In this case, the first clock signal CKV and the second clock signal CKVB may be gate-on in a high level so as to drive a transistor (not shown) constituting a pixel (not shown) of the liquid crystal panel (not shown). The voltage Von may be equal to the gate-off voltage Voff in the case of the low level, and the duty ratio of the first clock signal CKV and the second clock signal CKVB is 50%, and the phase difference thereof is 180 °. Can be.

2 is an internal circuit diagram of the j-th stage according to the first embodiment of the present invention.

Referring to FIG. 2, the j th stage ST _j includes the input unit 100, the output unit 200, the pull-up driver 300, the pull-down driver 400, the gate off unit 500, and the sensing unit 600. Include.

The input unit 100 includes a fourth transistor T4 having a source and a gate connected in common and receiving a carry signal Cout _(j-1) of a previous stage, and the front carry signal Cout _(j-1) . It receives the input and outputs the control signal CONT through the drain. The gate and the source of the fourth transistor T4 are commonly connected to the set terminal S, and the drain thereof is connected to the first node N1.

The output unit 200 is connected to the input unit 100 and outputs a gate on / off signal Gout _(j ) and a carry signal Cout _(j) according to the first clock signal CKV and the control signal CONT. Output

The output unit 200 has a gate connected to the control signal CONT, a drain connected to the first clock terminal CK1, and a source connected to the second node N2. And a fifteenth transistor T15 and a source connected to a first clock terminal CK1, a drain connected to a carry output terminal OUT2, and a gate connected to a first node, and a first transistor T1. The first capacitor C1 is connected between the gate and the drain of the transistor), and the second capacitor C2 is connected between the gate and the drain of the fifteenth transistor T15.

The pull-up driver 300 operates according to the first clock signal CKV, and prevents the pull-down driver 400 from pulling down the output unit 200.

The pull-up driving unit 300 is disposed between the twelfth transistor T12, the first clock terminal CK1, and the fourth node N4, which are connected between the first clock terminal CK1 and the third node N3. And a seventh transistor T7 connected thereto. A gate and a source of the twelfth transistor T12 are commonly connected to the first clock terminal CK1, and a drain thereof is connected to the third node N3. The gate of the seventh transistor T7 is connected to the third node N3 and to the first clock terminal CK1 through the third capacitor C3, and the source is drained to the first clock terminal CK1. Is connected to the fourth node N4, and the fourth capacitor C4 is connected between the third node N3 and the fourth node N4.

The pull-down driving unit 400 is connected to the input unit 100, the pull-up driving unit 300, and the output unit 200, and includes the first clock signal CKV, the second clock signal CKVB, and the (j + 1) th stage. The output unit 200 is pulled down by operating according to the gate on / off signal Gout _{(j + 1)} .

The pull-down driving unit 400 includes three transistors T5, T10, and T11 connected in series between the set terminal S and the frame reset terminal FR, the first node N1, and the frame reset terminal FR. Are connected between the pair of transistors T6 and T9 connected in parallel, the third node N3 of the pull-up driver 300, and the fourth node N4 and the frame reset terminal FR, respectively. A pair of transistors T13 and T8 and a pair of transistors T2 and T3 connected in parallel between the second node N2 and the frame reset terminal FR are included.

The gate off part 500 has a gate connected to the reset terminal R, a drain connected to the second node N2, and a source connected to the frame reset terminal FR. The gate includes the gate on / off signal Gout _{(j + 1)} of the (j + 1) th stage (ST _{j +1} ) to turn on the fourteenth transistor T14 and to gate through the drain. The off voltage Voff is output to the gate output terminal OUT1.

The sensing unit 600 has a gate connected to the second node N2, a drain connected to the sensing line SL1, and a source connected to the fifth node N5. The second sensing transistor ST2 and the inverting input terminal are connected to the reset terminal R, the drain is connected to the fifth node N5, and the source is connected to the frame reset terminal FR. (-) Is connected to the fifth node, the non-inverting input terminal (+) is connected to the reference voltage (Vref), by comparing the sensing signal input through the sensing line (SL1) and the reference voltage (Vref), The comparator AMP outputs the comparison result to the output terminal OUT3.

Here, the sensing line SL1 is connected to a sensing electrode (not shown) formed on the thin film transistor array panel (not shown), and is formed on the common electrode display panel (not shown) when a pressure is applied from the outside. The sensor spacer (not shown) and the sensing electrode (not shown) of the thin film transistor array panel are energized to transmit a sensing signal to the sensing line SL1. At this time, a gate on / off signal Gout _(j) is output to the gate output terminal OUT1, and the signal is input to the gate of the first sensing transistor ST1 to turn on the first sensing transistor ST1. The sensing signal of the sensing line SL1 is input to the inverting input terminal (−) of the comparator AMP.

The gate on / off signal Gout _{(j + 1} ) of the (j + 1) th stage is input to the reset terminal R, and this signal is input to the gate of the fourteenth transistor T14 to provide the fourteenth transistor. The T14 is turned on, and the gate output terminal OUT1 outputs the gate off signal Voff. At this time, the first sensing transistor ST1 is turned off.

In addition, the gate on / off signal Gout _{(j + 1)} of the (j + 1) th stage is input to the gate of the second sensing transistor ST2 to turn on the second sensing transistor ST2, and through the drain. The gate-off signal Voff is output to the fifth node N5 to prevent any signal from being input to the inverting input terminal (-) of the comparator AMP due to noise.

3 is an internal circuit diagram of the j-th stage according to the second embodiment of the present invention.

The internal circuit diagram of a j-th stage according to the second embodiment of the present invention, the second to the gate of the sensing transistor (ST2) (j + 2) gate on the second stage _{(ST (j + 2))} / off signal (Gout _{( j + 2)} is identical to the internal circuit diagram (see FIG. 2) of the j-th stage according to the first embodiment of the present invention except that the gate off unit 500 and the sensing unit 600 are excluded. The remaining parts will be omitted for convenience of description.

Referring to FIG. 3, the sensing unit 600 has a gate connected to the second node N2, a drain connected to the sensing line SL1, and a source connected to the fifth node N5. The second sensing transistor ST1, the gate is connected to the first dummy terminal D1, the drain is connected to the fifth node N5, and the source is connected to the frame reset terminal FR. The transistor ST2 and the inverting input terminal (-) are connected to the fifth node, the non-inverting input terminal (+) is connected to the reference voltage Vref, and the sensing signal input through the sensing line SL1 And a comparator AMP for comparing the reference voltage Vref and outputting the comparison result to the output terminal OUT3.

When pressure is applied from the outside, a sensing signal is transmitted to the sensing line SL1. At this time, the gate output terminal OUT1 outputs the gate on / off signal Gout _(j) , which is input to the gate of the first sensing transistor ST1 to turn on the first sensing transistor ST1, The sensing signal of the sensing line SL1 is input to the inverting input terminal (−) of the comparator AMP.

The gate on / off signal Gout _{(j + 1} ) of the (j + 1) th stage is input to the reset terminal R, and this signal is input to the gate of the fourteenth transistor T14 to provide the fourteenth transistor. The T14 is turned on, and the gate output terminal OUT1 outputs the gate off signal Voff. At this time, the first sensing transistor ST1 is turned off.

In addition, the gate on / off signal Gout _{(j + 2)} of the (j + 2) th stage ST _{(j + 2} ) is input to the gate of the second sensing transistor ST2, so that the second sensing transistor ST2 is input. ) Is turned on and the gate-off signal Voff is output to the fifth node N5 through the drain to prevent any signal from being input to the inverting input terminal (-) of the comparator AMP due to noise.

4 is an internal circuit diagram of the j-th stage according to the third embodiment of the present invention.

The internal circuit diagram of the j-th stage according to the third embodiment of the present invention is the j-th stage according to the second embodiment of the present invention except that the third sensing transistor ST3 and the fifth capacitor C5 are further included. Since it is the same as the internal circuit diagram (see FIG. 3), other portions except for the gate off unit 500 and the sensing unit 600 will be omitted for convenience of description.

Referring to FIG. 4, the sensing unit 600 has a gate connected to the second node N2, a drain connected to the sensing line SL1, and a source connected to the fifth node N5. The second sensing transistor ST1, the gate is connected to the first dummy terminal D1, the drain is connected to the fifth node N5, and the source is connected to the frame reset terminal FR. The third sensing transistor ST3 has a transistor ST2, a gate connected to a fifth node N5, a drain connected to a fifth capacitor C5, and a source connected to a reset terminal S. And the fifth capacitor C5 and the inverting input terminal (-) connected between the gate and the drain of the third sensing transistor ST3 are connected to the drain terminal of the third sensing transistor ST3 and have a non-inverting input. Terminal (+) is connected to the reference voltage (Vref), the sensing scene is input through the sensing line (SL1) And a comparator AMP for comparing the call with the reference voltage Vref and outputting the comparison result to the output terminal OUT3.

When pressure is applied from the outside, a sensing signal is transmitted to the sensing line SL1. At this time, a gate on / off signal Gout _(j) is output to the gate output terminal OUT1, and the signal is input to the gate of the first sensing transistor ST1 to turn on the first sensing transistor ST1. The sensing signal output through the drain is input to the gate of the third sensing transistor ST3. Then, the third sensing transistor ST3 is turned on and outputs a gate-off signal Voff to the drain.

Thereafter, the gate on / off signal Gout _{(j + 1} ) of the (j + 1) th stage is input to the reset terminal R, and the signal is input to the gate of the fourteenth transistor T14 to provide the fourteenth transistor. The T14 is turned on, and the gate output terminal OUT1 outputs the gate off signal Voff. At this time, the first sensing transistor ST1 is turned off. In addition, the fifth node N5 between the first sensing transistor ST1 and the third sensing transistor ST3 is in a floating state. At this time, the fifth node C5 is moved by the fifth capacitor C5. Is boosted up to turn on the third sensing transistor ST3, and the gate on / off signal Gout _{(j + 1} ) is output through the drain. At this time, the gate on / off signal Gout _{(j + 1)} is input to the inverting input terminal (-) of the comparator AMP, and the comparator AMP is connected with the reference voltage Vref and the gate on / off signal Gout _{( j + 1)} ) is compared and the comparison result is output to the output terminal OUT3.

In addition, the gate on / off signal Gout _{(j + 2)} of the (j + 2) th stage ST _{(j + 2} ) is input to the gate of the second sensing transistor ST2, so that the second sensing transistor ST2 is input. ) Is turned on and the gate-off signal Voff is output to the fifth node N5 through the drain to prevent any signal from being input to the inverting input terminal (-) of the comparator AMP due to noise.

5 is an internal circuit diagram of the j th stage according to the fourth embodiment of the present invention.

The internal circuit diagram of the j-th stage according to the fourth embodiment of the present invention is a gate on / off signal Gout of the (j + 3) th stage ST _{(j + 3)} to the gate of the second sensing transistor ST2. _{(j + 3)} ) is input _, and the gate on / off signal Gout _{(j + 2)} of the (j + 2) th stage ST _{(j + 2)} to the source of the third sensing transistor ST3. Except is input, since it is the same as the internal circuit diagram (see FIG. 4) of the j-th stage according to the third embodiment of the present invention, the remaining parts except for the gate off unit 500 and the sensing unit 600 will be described. It will be omitted for convenience.

Referring to FIG. 5, the sensing unit 600 has a gate connected to the second node N2, a drain connected to the sensing line SL1, and a source connected to the fifth node N5. The second sensing transistor ST1, the gate is connected to the second dummy terminal D2, the drain is connected to the fifth node N5, and the source is connected to the frame reset terminal FR. The third sensing transistor having a transistor ST2, a gate connected to a fifth node N5, a drain connected to a fifth capacitor C5, and a source connected to a first dummy terminal D1. The third capacitor C5 and the inverting input terminal (−) connected between the ST3, the gate and the drain of the third sensing transistor ST3 are connected to the drain terminal of the third sensing transistor ST3, and Inverting input terminal (+) is connected to the reference voltage (Vref), the sense input through the sensing line (SL1) By comparing the signal with a reference voltage (Vref), a comparator (AMP) for outputting a comparison result to the output terminal (OUT3).

When pressure is applied from the outside, a sensing signal is transmitted to the sensing line SL1. At this time, a gate on / off signal Gout _(j) is output to the gate output terminal OUT1, and the signal is input to the gate of the first sensing transistor ST1 to turn on the first sensing transistor ST1. The sensing signal output through the drain is input to the gate of the third sensing transistor ST3. Then, the third sensing transistor ST3 is turned on and outputs the gate off signal Voff to the drain.

Thereafter, the gate on / off signal Gout _{(j + 1} ) of the (j + 1) th stage is input to the reset terminal R, and the signal is input to the gate of the fourteenth transistor T14 to provide the fourteenth transistor. The T14 is turned on, and the gate output terminal OUT1 outputs the gate off signal Voff. At this time, the first sensing transistor ST1 is turned off. In addition, the fifth node N5 between the first sensing transistor ST1 and the third sensing transistor ST3 is in a floating state. At this time, the fifth node C5 is moved by the fifth capacitor C5. Is boosted up to turn on the third sensing transistor ST3, and the gate on / off signal Gout _{(j + 2} ) of the (j + 2) th stage ST _{(j + 2)} is applied to the source. ₎ ) Is input to output the gate on / off signal Gout _{(j + 2)} through the drain. At this time, the gate on / off signal Gout _{(j + 2)} is input to the inverting input terminal (-) of the comparator AMP, and the comparator AMP is connected to the reference voltage Vref and the gate on / off signal Gout _{( j + 2)} ) is compared and the comparison result is output to the output terminal OUT3.

In addition, the gate on / off signal Gout _{(j + 2)} of the (j + 3) th stage ST _{(j + 2} ) is input to the gate of the second sensing transistor ST2 so that the second sensing transistor ST2 is input. ) Is turned on and the gate-off signal Voff is output to the fifth node N5 through the drain to prevent any signal from being input to the inverting input terminal (-) of the comparator AMP due to noise.

6 is an internal circuit diagram of the j th stage according to the fifth embodiment of the present invention.

The internal circuit diagram of a j-th stage according to the fifth embodiment of the present invention, the second to the gate of the sensing transistor (ST2) (j + 2) gate on the second stage _{(ST (j + 2))} / off signal (Gout _{( j + 2)} ) and the internal circuit diagram of the j-th stage according to the fourth embodiment of the present invention except that the gate and the source of the third sensing transistor ST3 are connected in common (see FIG. 5). Since it is the same as), other portions except for the gate off unit 500 and the sensing unit 600 will be omitted for convenience of description.

Referring to FIG. 6, the sensing unit 600 has a gate connected to the second node N2, a drain connected to the sensing line SL1, and a source connected to the fifth node N5. The second sensing transistor ST1, the gate is connected to the first dummy terminal D1, the drain is connected to the fifth node N5, and the source is connected to the frame reset terminal FR. The transistor ST2, the gate and the source are commonly connected to the fifth node N5, and the drain thereof is the third sensing transistor ST3 and the inverting input connected to the inverting input terminal (-) of the comparator AMP. The terminal (-) is connected to the drain terminal of the third sensing transistor ST3, the non-inverting input terminal (+) is connected to the reference voltage Vref, and the sensing signal and the reference input through the sensing line SL1. Comparator AMP for comparing the voltage (Vref), and outputs the comparison result to the output terminal (OUT3) The.

When pressure is applied from the outside, a sensing signal is transmitted to the sensing line SL1. At this time, the gate output terminal OUT1 outputs the gate on / off signal Gout _(j) , which is input to the gate of the first sensing transistor ST1 to turn on the first sensing transistor ST1, The sensing signal output through the drain is input to the gate of the third sensing transistor ST3. Then, the third sensing transistor ST3 is turned on and outputs a sensing signal input to the gate as a drain, which is input to the inverting input terminal (-) of the comparator AMP, and the comparator AMP is sensed. The signal is compared with the reference voltage Vref, and the comparison result is output to the output terminal OUT3. Here, the third sensing transistor ST3 serves as a diode for outputting a sensing signal input to the gate as a drain.

The gate on / off signal Gout _{(j + 1} ) of the (j + 1) th stage is input to the reset terminal R, and this signal is input to the gate of the fourteenth transistor T14 to provide the fourteenth transistor. The T14 is turned on and the drain outputs the gate off signal Voff. At this time, the first sensing transistor ST1 is turned off.

In addition, the gate on / off signal Gout _{(j + 2)} of the (j + 2) th stage ST _{(j + 2} ) is input to the gate of the second sensing transistor ST2, so that the second sensing transistor ST2 is input. ) Is turned on and the gate-off signal Voff is output to the fifth node N5 through the drain to prevent any signal from being input to the inverting input terminal (-) of the comparator AMP due to noise.

7 is an internal circuit diagram of the j-th stage according to the sixth embodiment of the present invention.

The internal circuit diagram of the j-th stage according to the sixth embodiment of the present invention is a gate on / off signal (j + 1) of the (j + 1) th stage ST _{(j + 1)} to the gate of the second sensing transistor ST2. Internal circuit diagram of the j-th stage according to the third embodiment of the present invention except that Gout _{(j + 1)} is input and the input voltage Vin is externally input to the source of the third sensing transistor ST3. Since it is the same as (see FIG. 4), the rest of portions except for the gate off unit 500 and the sensing unit 600 will be omitted for convenience of description.

Referring to FIG. 7, the sensing unit 600 has a gate connected to the second node N2, a drain connected to the sensing line SL1, and a source connected to the fifth node N5. The second sensing transistor ST1, the gate is connected to the reset terminal R, the drain is connected to the fifth node N5, and the source is connected to the frame reset terminal FR. ST2), the gate is connected to the fifth node N5, the drain is connected to the fifth capacitor C5, and the source is connected to the first dummy terminal D1 to which a separate external voltage is input. The third capacitor ST3, the fifth capacitor C5 and the inverting input terminal (−) connected between the gate and the drain of the third sensing transistor ST3 are connected to the drain terminal of the third sensing transistor ST3. Non-inverting input terminal (+) is connected to a reference voltage (Vref), and A (SL1) by comparing the sensing signal with a reference voltage (Vref) is input through, a comparator (AMP) for outputting a comparison result to the output terminal (OUT3).

When pressure is applied from the outside, a sensing signal is transmitted to the sensing line SL1. At this time, the gate output terminal OUT1 outputs the gate on / off signal Gout _(j) , and this signal is input to the gate of the first sensing transistor ST1 to turn on the first sensing transistor ST1. The sensing signal output through the drain is input to the gate of the third sensing transistor ST3. Then, the third sensing transistor ST3 is turned on and an input voltage Vin provided from the outside to the drain is output. In this case, the input voltage Vin may have the same voltage level as the gate off signal Voff.

Thereafter, the gate on / off signal Gout _{(j + 1} ) of the (j + 1) th stage is input to the reset terminal R, and the signal is input to the gate of the fourteenth transistor T14 to provide the fourteenth transistor. The T14 is turned on, and the gate output terminal OUT1 outputs the gate off signal Voff. At this time, the first sensing transistor ST1 is turned off. In addition, the fifth node N5 between the first sensing transistor ST1 and the third sensing transistor ST3 is in a floating state. At this time, the fifth node C5 is moved by the fifth capacitor C5. The voltage of boosts up to turn on the third sensing transistor ST3 and outputs an input voltage Vin externally provided as a drain. In this case, the input voltage Vin may have the same voltage level as the gate on / off signal Gout _(j ), where the input voltage Vin is input to the inverting input terminal (-) of the comparator AMP, The comparator AMP compares the reference voltage Vref with the gate-on signal and outputs a comparison result to the output terminal OUT3.

In the present invention, the shift register is provided with a sensing circuit for sensing the X coordinate of the touch point inside the shift register, and the sensing signal is transmitted to the comparator through the sensing line. However, the shift register detects the Y coordinate. A sensing circuit may be provided to transmit a sensing signal to a comparator through a sensing line to output a comparison result.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, the shift register according to the present invention includes a sensing circuit that senses coordinates of a touch point when a pressure is applied from the inside of the shift register to correspond to the X and Y axes in the pixel area of the liquid crystal display. Since it is not necessary to add a sensing line, the aperture ratio can be improved, and the sensing line increases the fan out resistance, thereby preventing the sensing signal from being distorted, thereby accurately detecting the coordinates of the touch point.

Claims (10)

A shift register including n stages for sequentially outputting a gate on / off signal, Each stage An input unit configured to receive a first carry signal and output a control signal; An output unit connected to the input unit and outputting the gate on / off signal and the second carry signal according to a first clock signal and the control signal; A pull-up driver configured to operate on the first clock signal; A pull-down driving unit connected to the input unit, the pull-up driving unit, and the output unit and operating according to the first clock signal, the second clock signal, and a gate on / off signal of an (n + 1) th stage; A sensing unit configured to output a sensing signal corresponding to a touch point according to the gate on / off signal; And And a gate off part configured to output an off signal according to the gate on / off signal of the (n + 1) th stage. The method of claim 1, The sensing unit, A first sensing transistor configured to output the sensing signal according to the gate on / off signal; A second sensing transistor configured to output an off signal according to the gate on / off signal of the (n + 1) th stage; And And a comparator configured to compare the sensing signal with a reference voltage and output a comparison result. The method of claim 1, The sensing unit, A first sensing transistor configured to output a sensing signal according to the gate on / off signal; A second sensing transistor configured to output an off signal according to the gate on / off signal of the (n + 2) th stage; And And a comparator configured to compare the sensing signal with a reference voltage and output a comparison result. The method of claim 1, The sensing unit, A first sensing transistor configured to output a sensing signal according to the gate on / off signal; A second sensing transistor configured to output an off signal according to the gate on / off signal of the (n + 2) th stage; A third sensing transistor configured to output a gate on / off signal of the (n + 2) th stage; A capacitor connected to the gate and the drain of the third sensing transistor; And And a comparator configured to compare the gate on / off signal of the (n + 2) th stage with a reference voltage and output a comparison result. The method of claim 4, wherein And the third sensing transistor is turned on by a voltage stored in the capacitor when the first sensing transistor is turned on. The method of claim 1, The sensing unit, A first sensing transistor configured to output a sensing signal according to the gate on / off signal; A second sensing transistor configured to output an off signal according to the gate on / off signal of the (n + 3) th stage; A third sensing transistor configured to output a gate on / off signal of the (n + 2) th stage; A capacitor connected to the gate and the drain of the third sensing transistor; And And a comparator configured to compare the gate on / off signal of the (n + 2) th stage with a reference voltage and output a comparison result. The method of claim 6, And the third sensing transistor is turned on by a voltage stored in the capacitor when the first sensing transistor is turned on. The method of claim 1, The sensing unit, A first sensing transistor configured to output a sensing signal according to the gate on / off signal; A second sensing transistor configured to output an off signal according to the gate on / off signal of the (n + 2) th stage; A third sensing transistor connected to a source and a gate and outputting a signal input to the gate; And And a comparator configured to compare the sensing signal with a reference voltage and output a comparison result. The method of claim 1, The sensing unit, A first sensing transistor configured to output a sensing signal according to the gate on / off signal; A second sensing transistor configured to output an off signal according to the gate on / off signal of the (n + 1) th stage; A third sensing transistor configured to output an input voltage provided from the outside; A capacitor connected to the gate and the drain of the third sensing transistor; And And a comparator configured to compare the input voltage with a reference voltage and output a comparison result. The method of claim 9, And the third sensing transistor is turned on by a voltage stored in the capacitor when the first sensing transistor is turned on.

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