KR20080050770A - Flash memory device and manufacturing method thereof - Google Patents

Abstract

A method for manufacturing a flash memory device is provided to prevent bridge phenomenon among plural cells by forming a dielectric contact hole only on a cell region. A semiconductor substrate(200) on which a cell region and a dummy region are defined, is provided. A gate dielectric pattern(202a), a first conductive layer pattern(204a), and an isolation layer(210) are formed on the semiconductor substrate. A dielectric(212) is formed on upper portions of the isolation layer and the first conductive layer. A part of the dielectric on the cell region, where a selective transistor is formed, is removed to form a dielectric contact hole. A second conductive layer is formed on an upper portion of the entire structure including the dielectric contact hole. A length of the dummy region is 2 to 10 mum. Two or three dummy patterns are formed on the dummy regions. The dielectric contact hole is formed in a cell region direction from an upper portion of an active region that is adjacent the dummy region among the active region of the cell region.

Description

Flash memory device and manufacturing method

1 is a layout for explaining a flash memory device according to the present invention.

2A to 2F are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

200 semiconductor substrate 202 gate insulating film

204: First conductive film 206: Nitride film

208: first mask film pattern 210: device isolation film

212: dielectric film 214: second mask film pattern

216: second conductive film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to flash memory devices and manufacturing methods, and more particularly, to dielectric film contact holes in flash memory devices.

In general, a flash memory device includes a cell area that substantially performs an operation and a dummy area that is formed in a process step. The cell region includes a plurality of memory cells in which data is stored, a source select transistor, and a drain select transistor. The dummy region is a region formed in the manufacturing process. Therefore, a plurality of gates are formed in the dummy area irrespective of the operation of the flash memory device.

In particular, a step occurs in a subsequent process due to a difference in density of a layer formed between a cell region and a dummy region in a manufacturing process, and a process for forming an effective field oxide (EFH) is performed. At this time, since a film having a low density is formed in the dummy region, a step is generated. This step occurs mainly on the device isolation film. Due to the step, the polysilicon film may remain during the manufacturing process. A bridge may occur between the device and the device due to the residue, thereby deteriorating the characteristics of the device. For this reason, one of the important factors in NAND flash devices is the control of effective field oxide (EFH). This directly affects the coupling ratio, which is a very important factor in the operation of the device, affecting the operation speed of the device.

Therefore, after the dielectric film is formed in the manufacturing process of the flash memory device, the contact hole of the source and drain selection lines formed in the dummy region and the cell region is formed only in the cell region, thereby bridging the plurality of cells in the dummy region. To prevent it.

The flash memory device according to the present invention includes a semiconductor substrate in which a cell region and a dummy region are defined. Active spaced apart from the device isolation layer. Memory cells arranged vertically with the active. It is composed of source and drain select transistors arranged horizontally with the memory cells and having dielectric contact holes formed only in the cell region.

The dielectric film contact hole is formed in the cell region direction based on the activity between the cell region and the dummy region.

The dielectric film contact hole is formed in the cell region direction based on 1/2 of the active.

In the method for manufacturing a flash memory device according to the present invention, a semiconductor substrate in which a cell region and a dummy region are defined is provided. A gate insulating film pattern, a first conductive film pattern, and an element isolation film are formed on a semiconductor substrate. A dielectric film is formed over the device isolation film and the first conductive film. A portion of the dielectric film in the cell region where the selection transistor is formed is removed to form a dielectric film contact hole. Forming a second conductive film over the entire structure including the dielectric film contact hole.

The dummy region is formed to have a length of 2 to 10 mu m, and two or three dummy patterns are formed in the dummy region.

The dielectric film contact hole is formed in the cell region direction from an upper portion of the active region immediately adjacent to the dummy region among the active regions of the cell region, and is based on 1/2 of the active length.

The dielectric film contact hole is formed in the cell region direction from an upper portion of the active region immediately adjacent to the cell region among the active regions of the dummy region, and is based on 1/2 of the active length.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 is a layout for explaining a flash memory device according to the present invention. This layout diagram shows a cell region and a dummy region as part of a flash memory device. The structure of a cell array in a flash memory device is as follows.

The cell array includes an isolation region 102 and an active region 104, and the isolation layer 102 and the active region 102 are alternately defined in parallel. An isolation layer is formed in the isolation region 102. The plurality of gates includes source select lines SSL1 and SSL2 and a plurality of word lines WL0 to WLn (n is an integer).

Transistors are formed below the source select lines SSL1 and SSL2, and memory cells are formed below the word lines WL0 to WLn. Both transistors and memory cells are formed in a structure in which a gate insulating film, a first conductive film for floating gates, a dielectric film and a second conductive film for control gates are stacked on a semiconductor substrate. However, in the case of the transistor, the voltage is transferred to the floating gate, not to store data, so that a portion of the dielectric film is removed so that the first conductive film and the second conductive film are in contact with each other. The contact hole formed at this time is a dielectric film contact hole.

Meanwhile, in the process of forming the device isolation layer, many studies have been conducted to improve the effective field oxide height (EFH), which is the height from the active top to the top of the device isolation layer. In the vicinity of the boundary between the cell region and the dummy region, there is a severe level difference in the structure of the device. Specifically, the variation of the EFH in the manufacturing process of the flash memory device is mainly generated during the etching process of the phase change layer (PCL). The phase change layer PCL is used to remove the step between the cell region and the peripheral region. However, when the mask layer pattern in which the top of the region where the step is generated is closed is used, height difference occurs between the device isolation layers, which may make subsequent processing difficult.

That is, after forming the gate insulating film and the floating gate conductive film on the semiconductor substrate in which the cell region and the dummy region are defined, the device isolation film is formed in the device isolation region by the SA-STI process. A step difference occurs in the device separator between the cell region and the dummy region due to the device separator etching process for controlling the EFH. After forming a dielectric film, a capping polysilicon film, and a control gate conductive film on the floating gate conductive film, an etching process for gate patterning is performed. At this time, after the dielectric film is formed, a portion of the dielectric film in the source and drain select transistor regions is removed so that the floating gate conductive film and the control gate conductive film are in contact with each other.

When the gate patterning process is performed, the loading of the equipment is not easy due to the step between the cell region and the dummy region, so that the etching process may leave the conductive film for the floating gate as a residue. . Since the residue of the conductive film remains in the dummy region, and a dielectric film is further formed on the residue, it does not affect the cell region unless a bias is directly applied to the conductive film for the floating gate.

However, since the drain and source select transistors are general transistors for operating a memory cell rather than data storage, a portion of the dielectric film is removed to allow current to flow.

In the flash memory fabrication process, a portion of the dielectric film is removed using a dielectric film contact mask pattern. The dielectric film contact mask pattern has a pattern in which a portion of the source select line and drain select line regions are open. As a result, the bias applied to the drain or source select transistor can be transferred to the adjacent memory cells of the same string through the remaining conductive film. This may be transferred to another memory cell and eventually cause a short circuit of cells in the block, which may cause device malfunction.

Therefore, in the present invention, the dielectric film contact hole 108 is formed only in the drain of the cell region and the source transistor regions SSL1 and SSL2. As a result, the gate and the gate to be formed in the drain and source transistor regions (SSL1 and SSL2) of the dummy region are formed without the transistor to form the same structure as the memory cell.

As a result, the floating state is maintained even when a bias is applied to the drain or the source gate, thereby suppressing a phenomenon of transferring to the memory cell through the conductive layer. Next, the manufacturing method will be described in detail through the cross-sectional view of the E-E 'direction.

2A to 2F are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.

Referring to FIG. 2A, a gate insulating film 202, a first conductive film 204 for floating gates, a nitride film 206, and a first mask film for gate patterning are formed on a semiconductor substrate 200 on which cell and dummy regions are defined. Pattern 208 is formed. The dummy region is mainly defined as a length of 2 to 10 mu m.

Referring to FIG. 2B, an etching process is performed to form the nitride film pattern 206, the first conductive film pattern 204a, the gate insulating film pattern 202a, and the trench according to the first mask film pattern, and the first mask film pattern. Remove it. The nitride film pattern 206a prevents loss and damage of the first conductive film pattern 204a during the etching process. Two or three dummy patterns are formed in the dummy region.

Referring to FIG. 2C, a material for an isolation layer is filled on the semiconductor substrate 200 including the nitride layer pattern and the trench. A chemical mechanical polishing process is performed to expose the first conductive layer pattern 204a to form the isolation layer 210 spaced apart from each other. In this case, the device isolation layer 210 in the cell region may have a height difference of EFH in order to increase the efficiency of device operation. At this time, a step occurs between the device isolation layer 210 in the dummy region and the device isolation layer 210 in the cell region in the manufacturing process.

Referring to FIG. 2D, a dielectric film 212 is formed along the surfaces of the first conductive film pattern 204a and the device isolation film 210. The second mask layer pattern 214 is formed on the dielectric layer 212. The second hard mask layer pattern 214 has a pattern in which the cell region is open, and the boundary of the open pattern has an active boundary immediately adjacent to the cell region in the dummy region. Alternatively, the active area adjacent to the dummy area in the cell area may be the boundary. That is, on the basis of 1/2 of the active width B between the cell region and the dummy region, the dummy region is closed and the cell region forms the second mask layer pattern 214 that is open.

Referring to FIG. 2E, an etching process of removing a portion of the dielectric film is performed according to the second mask layer pattern 214 to form a dielectric film contact hole. At this time, all of the dielectric film pattern 212a in the dummy region remains, and part of the dielectric film pattern 212a in the cell region is removed. That is, it should be noted that the dielectric film of the cell region is removed in the illustrated cross-sectional view, but the dielectric film remains in regions other than this cross section.

Referring to FIG. 2F, the second mask layer pattern is removed. The second conductive layer 216 for the control gate is formed to cover the dielectric layer pattern 212a, the first conductive layer pattern 204a, and the isolation layer 210.

As a result, a dielectric film contact hole may be formed only in the cell region of the source and drain select transistor regions to prevent a bridge phenomenon between a plurality of cells.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to the method of manufacturing the flash memory device of the present invention described above, after the dielectric film is formed, a dielectric film contact hole may be formed only in the cell region of the source and drain select transistor regions to prevent the bridge phenomenon between the plurality of cells.

Claims (10)

A semiconductor substrate including a cell region and a dummy region; Active spaced apart from the device isolation layer; Memory cells arranged vertically with the active; And And a source and drain select transistor arranged horizontally with the memory cells and having a dielectric layer contact hole formed only in a cell region. The method of claim 1, And the dielectric layer contact hole is formed in a direction of the cell region based on the activity between the cell region and the dummy region. The method of claim 2, And the dielectric layer contact hole is formed in the cell region direction based on one half of the active. Providing a semiconductor substrate in which a cell region and a dummy region are defined; Forming a gate insulating layer pattern, a first conductive layer pattern, and an isolation layer on the semiconductor substrate; Forming a dielectric layer on the device isolation layer and the first conductive layer; Removing a portion of the dielectric film in the cell region in which the select transistor is formed to form a dielectric film contact hole; And And forming a second conductive film on the entire structure including the dielectric film contact hole. The method of claim 4, wherein The dummy region is formed of a flash memory device having a length of 2 to 10㎛. The method of claim 4, wherein 2 or 3 dummy patterns are formed in the dummy region. The method of claim 4, wherein And the dielectric layer contact hole is formed in the cell region direction from an upper portion of an active region immediately adjacent to the dummy region among the active regions of the cell region. The method of claim 7, wherein And the dielectric layer contact hole is based on one half of the active length. The method of claim 4, wherein And the dielectric film contact hole is formed in the cell region direction from an upper portion of an active region immediately adjacent to the cell region among the active regions of the dummy region. The method of claim 9, And the dielectric layer contact hole is based on one half of the active length.

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