KR20080049442A - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

An LCD device and a manufacturing method thereof are provided to improve an aperture ratio by forming no common line in the middle of a sub pixel and improve a contrast ratio of the device by preventing a stepped portion caused by the common line in an opening area. A gate line(112) and a data line(115) are vertically crossed on a substrate to define a sub pixel divided into an opening area and a non-opening area. A TFT(Thin Film Transistor) is disposed in an intersection between the gate line and the data line. A counter electrode(124) is formed in the sub pixel. A common line(125) is parallel to the gate line, and is formed in an upper surface of the counter electrode of the non-opening area. A pixel electrode(117) is insulated from the counter electrode and forms an electric field together with the counter electrode. An LC layer is interposed between an opposite substrate facing the substrate and two substrates.

Description

Liquid Crystal Display Device and Method for Manufacturing the Same {Liquid Crystal Display Device And Method For Fabricating The Same}

1 is a plan view of a conventional FFS mode liquid crystal display device.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1. FIG.

3 is a plan view of the FFS mode liquid crystal display device according to the present invention.

4 is a cross-sectional view taken along line II-II ′ of FIG. 3.

5A through 5D are cross-sectional views of a FFS mode liquid crystal display device according to the present invention.

* Explanation of symbols on the main parts of the drawings

112: gate wiring 112a: gate electrode

114: semiconductor layer 115: data wiring

115a: source electrode 115b: drain electrode

117: pixel electrode 119: slit

124: counter electrode 125: common wiring

150 photoresist pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly to a FFS mode (Fringe Field Switching Mode) liquid crystal display device for improving contrast characteristics and a method of manufacturing the same.

In recent years, active matrix liquid crystal display devices have been widely used in flat panel TVs, portable computers, monitors, and the like, as their performance is rapidly developed.

Among the active matrix liquid crystal display devices, twisted nematic (TN) type liquid crystal display devices are mainly used. In the twisted nematic method, electrodes are installed on two substrates and the liquid crystal directors are arranged to be twisted by 90 °. It is a technique of driving a liquid crystal director by applying a voltage to an electrode.

Twisted nematic liquid crystal display devices are spotlighted for providing excellent contrast and color reproducibility, but suffer from the chronic problem of narrow viewing angles.

In order to solve the viewing angle problem of the TN method, an IPS mode in which two electrodes are formed on a single substrate and a transverse electric field generated between the two electrodes is controlled.

Subsequently, in order to improve the low aperture ratio and transmittance of the IPS mode, a fringe formed between the counter electrode and the pixel electrode by forming a narrow gap between the counter electrode and the pixel electrode while forming the counter electrode and the pixel electrode as a transparent conductor. FFS mode for operating liquid crystal molecules has emerged by the field.

Hereinafter, the liquid crystal display device according to the prior art will be described with reference to the FFS mode liquid crystal display device as an embodiment.

1 is a plan view of a conventional FFS mode liquid crystal display device, and FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

In the FFS mode liquid crystal display device, a color filter layer array substrate including a color filter layer and a TFT array substrate including a thin film transistor, a counter electrode, and a pixel electrode are opposed to each other with a liquid crystal layer interposed therebetween. 1 and 2, the gate wiring 12 and the data wiring 15 formed of an opaque metal and vertically intersecting with each other to define a sub-pixel; A thin film transistor for switching voltage on / off at an intersection point and a plate-shaped counter electrode 24 and a pixel electrode 17 formed of a transparent metal, insulated by an insulating film, and overlapping each other in the pixel are formed.

The thin film transistor is stacked with a gate electrode 12a, a gate insulating layer 13, a semiconductor layer 14, and source / drain electrodes 15a and 15b, and the drain electrode is formed through the first contact hole 18. It is electrically connected to the electrode 17.

In addition, the pixel electrode 17 includes a plurality of slits 19 having a regular shape and insulated from the counter electrode by the second insulating film 20 and formed of a transparent metal. Usually, the width of the slit 19 has a value between approximately 2-6 μm.

The counter electrode 24 is insulated from the data line 15 forming layer by the first insulating layer 16, is formed on the entire surface of the sub-pixel in a plate shape, and is formed of a transparent metal in the same manner as the pixel electrode. The counter electrode penetrates through the gate insulating layer 13 and the first insulating layer 16 and contacts the common wiring 25 to receive a Vcom signal from the common wiring.

A fringe field is formed between the counter electrode 24 and the pixel electrode 17. The liquid crystal layer is driven by the fringe field. That is, the liquid crystals that were initially oriented by rubbing when no voltage is applied are rotated by the fringe field so that light is transmitted. At this time, the Vcom signal is transmitted to the counter electrode 24, and the pixel voltage passing through the thin film transistor is transferred to the pixel electrode 17.

On the other hand, the color filter layer array substrate is arranged in a predetermined order to implement the color (Red), green (Green), blue (Blue) color filter layer, and serves to distinguish between the R, G, B cells and light blocking A black matrix is formed, and the color filter layers of each color are formed to correspond to the sub-pixels so that each sub-pixel has one pigment, and typically, pixels having dyes of R, G, and B are arranged. Each is driven independently and the color of one pixel is displayed by the combination thereof.

The liquid crystal display device according to the prior art as described above had the following problems.

First, the common wiring 25 is provided on the same layer as the gate wiring 12. In order to contact the counter electrode 24 provided thereon, an insulating film provided between the common wiring and the counter electrode is removed to form a contact hole. There is a fear that the process will be cumbersome.

Second, in the case of a general FFS mode liquid crystal display device, as shown in FIG. 1, the common wiring 25 is disposed in the middle of the sub-pixel, but the common wiring is formed of an opaque metal material, thereby reducing the aperture ratio. It is becoming.

Third, a step is generated in the middle of the opening area of the sub-pixel due to the common wiring. Due to this step, the rubbing cloth is not touched in the alignment film rubbing process so that the rubbing does not occur. Direction is not controlled and arranged in a disordered state. In addition, the surface having a step is thinly coated with an alignment layer compared with other regions, but when the thickness of the alignment layer is low, there is a problem in that the anchoring energy between the liquid crystal molecules and the alignment layer becomes small.

Such rubbing defects and lowering of the thickness of the alignment film result in light leakage problems. Such light leakage is not a problem in the white state, but in the black state, the luminance is increased and the contrast ratio is lowered. Therefore, the image quality of the device is degraded.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and does not form a common wiring in the opening area of the sub-pixel. It is an object of the present invention to provide a liquid crystal display device and a manufacturing method of the FFS mode to prevent the.

The liquid crystal display device of the present invention for achieving the above object is a gate wiring and data wiring defining a sub-pixel divided into an opening region and a non-opening region by vertical crossing on a substrate, and the intersection of the gate wiring and data wiring A thin film transistor disposed at a point, a counter electrode formed on the sub-pixel, a common wiring parallel to the gate line and formed on an upper surface of the counter electrode of the non-opening region, and insulated from the counter electrode; And a pixel electrode forming an electric field, an opposing substrate facing the substrate, and a liquid crystal layer interposed between the two substrates.

In addition, the manufacturing method of the liquid crystal display device of the present invention for achieving the object of the present invention comprises the steps of forming a gate wiring on a substrate, forming a gate insulating film on the entire surface including the gate wiring, and on the gate insulating film Forming a data line at the intersection of the gate line and the sub-pixel divided into an opening region and a non-opening region, forming a thin film transistor at an intersection of the gate line and the data line; Forming a counter electrode on a sub-pixel, forming a common wiring on an upper surface of the counter electrode of the non-opening region, and forming a pixel electrode insulated from the counter electrode and generating an electric field together with the counter electrode. Characterized in that made.

Hereinafter, a liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view of an FFS mode liquid crystal display device according to the present invention, FIG. 4 is a cross-sectional view taken along the line II-II 'of FIG. 3, and FIGS. 5A to 5D are steps of the FFS mode liquid crystal display device according to the present invention. It is a cross section.

First, as shown in FIGS. 3 and 4, the thin film transistor array substrate of the liquid crystal display device according to the present invention defines a sub-pixel by vertical crossing and is insulated from each other by a gate insulating film (not shown). (112) and the data wiring 115, the thin film transistor formed at the intersection of the gate wiring and the data wiring, and a counter electrode disposed to be insulated from each other in the sub-pixel to generate a fringe field to drive the liquid crystal layer ( 124 and the pixel electrode 117 and a common wiring 125 in contact with the upper surface of the counter electrode and parallel to the gate wiring 112 are formed.

The thin film transistor serves to control on / off of a voltage. The thin film transistor TFT has a front surface including a gate electrode 112a which is a predetermined region of the gate line 112 and the gate electrode 112a. A gate insulating layer 113 formed on the gate insulating layer 113, a semiconductor layer 114 formed on the gate insulating layer above the gate electrode 112a, and a source electrode 115a branched from the data line 115 to be formed on the semiconductor layer. And a drain electrode 115b, and a first insulating layer 116 is provided on the entire surface including the thin film transistor.

The sub-pixel is divided into an opening area for transmitting light to display an image and a non-opening area at the edge of the sub-pixel where light is not transmitted, and the common wiring is disposed in the non-opening area to prevent a decrease in aperture ratio.

In addition, the sub-pixel contacts the common wiring 125 to apply the Vcom voltage, and has a plate-shaped counter electrode 124 formed in a passage through the sub-pixel, and the drain electrode 115b of the thin film transistor. A pixel electrode 117 is formed to be in contact with the pixel voltage, to be insulated from the counter electrode 124 by the second insulating layer 120, and to have a plurality of slits 119. In this case, a fringe field is formed between the counter electrode and the pixel electrode through the slit to drive the liquid crystal layer. However, the pixel electrode may be formed in a plate shape and the counter electrode may be formed to have a plurality of slits.

In this case, the counter electrode 124 and the pixel electrode 117 are formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the counter electrode is formed on the same layer as the gate wiring layer. 4, or may be disposed so as not to short with the data line layer on the first insulating layer 116 above the data line layer.

In the case of the former forming the counter electrode on the same layer as the gate wiring layer, the common wiring and the gate wiring layer formed on the upper surface of the counter electrode may be simultaneously formed. In other words, the transparent conductive material and the metal are deposited on the substrate, and the patterns are collectively patterned to form the gate wiring layer, the common wiring, and the counter electrode, and then the metal of the counter electrode may be removed.

On the other hand, in the latter case where the counter electrode is provided above the data line, the counter electrode and the common line are formed on the first insulating film formed on the front surface including the data line, and the second electrode is formed on the counter electrode to form the pixel electrode. Insulate from In other words, the transparent conductive material and the metal are deposited on the first insulating film, and the patterns are collectively patterned to form the common wiring and the counter electrode, and then the metal of the counter electrode may be removed.

In the above, the arrangement of the counter electrode and the common wiring has been described. In any case, the counter electrode is formed in the sub-pixel including the opening area and the non-opening area, and the common wiring is formed directly on the counter electrode of the non-opening area. do.

Therefore, since the common wiring is not arranged in the opening region, the opening ratio of the device can be prevented from being lowered, and a contact hole for contacting the common wiring and the counter electrode is unnecessary. Further, since the common wiring is formed in the non-opening region, even if a step is generated due to the common wiring and light leakage occurs, the contrast ratio is not lowered because it is a non-opening region irrelevant to the image display anyway.

In this case, the counter electrode is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and common wiring is copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), and molybdenum. It is formed of a metal material such as (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum-tungsten (MoW).

As described above, in order to form a common wiring with a counter electrode having a different material, a counter electrode may be formed of a transparent conductive material, and then a common wiring may be formed of a metal material thereon, but may be stacked using a diffraction exposure mask to simplify the process. The transparent conductive material and the metal material may be formed by patterning the batch.

Hereinafter, an embodiment in which the common electrode and the common wiring are formed by applying the diffraction exposure method will be described in detail.

First, as shown in FIG. 5A, copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), and molybdenum-tungsten (MoW) having low resistivity on the entire surface of the substrate 111. The gate wiring 112 and the gate electrode 112a are formed by depositing and patterning a metal, for example.

Next, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is generally deposited on the entire surface including the gate wiring 112 by a plasma enhanced chemical vapor deposition (PECVD) method. The gate insulating layer 113 is formed, amorphous silicon is deposited on the entire surface including the gate insulating layer, and patterned by a photolithography process to form a semiconductor layer 114 on the gate electrode 112a.

Subsequently, low resistance metals such as copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), and molybdenum-tungsten (MoW) are deposited on the entire surface including the semiconductor layer 114. After patterning, the data line 115 and the source / drain electrodes 115a and 115b are formed.

The data line 115 is formed to cross the gate line 112 to define a sub-pixel, and the source / drain electrodes 115a and 115b are formed to overlap both ends of the semiconductor layer 114 to form a thin film transistor. To complete.

Subsequently, an inorganic material such as silicon nitride or silicon oxide is deposited on the entire surface including the data line 115 or an organic material such as BCB or acrylic resin is coated to form the first insulating film 116 thereon. The transparent conductive material layer 124a and the metal layer 125a are sequentially deposited.

The transparent conductive material layer is formed of indium tin oxide (ITO) or indium zinc oxide (IZO), and the metal layer is copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo) , Chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum-tungsten (MoW) and the like.

Thereafter, a photoresist, which is a UV curable resin, is coated on the metal layer 125a by a spin method or a roll coating method, and then diffracted on the photoresist. An exposure mask (not shown) is covered and exposed to UV or x-ray wavelengths to be exposed, and then the diffractive photoresist is developed to form a double-thick photoresist pattern 150.

Here, the diffraction exposure mask is formed of a metal light shielding layer and a semi-transmissive layer on a transparent substrate, divided into three regions, a transmission region, a semi-transmissive region, a light shielding region, the light transmittance is 100%, The light blocking area has a light transmittance of 0%, and the transflective area has a light transmittance of 0% to less than 100%.

Therefore, the remaining thickness of the photoresist pattern 150 subjected to diffraction exposure is also divided into three regions, which are aligned with the transmission region of the diffraction exposure mask and completely removed in the development process, and the light blocking region of the diffraction exposure mask. And a part which is not removed at all in the development process afterwards, and a part having an intermediate thickness aligned with the transflective area of the diffraction exposure mask. However, the photoresist from which the exposed portion is removed is limited to the positive photoresist, and the negative photoresist removes the unexposed portion.

The photoresist pattern thus formed remains unremoved in the region where the common wiring is to be formed and has an intermediate thickness in the region where the counter electrode is to be formed.

Thereafter, the transparent conductive material layer 124a and the metal layer 125a are etched using the double-thick photoresist pattern 150 as a mask to define the size of the plate-shaped counter electrode as shown in FIG. 5B. .

Subsequently, the photoresist pattern 150 is ashed until the intermediate thickness photoresist pattern 150 is completely removed, and the exposed metal layer 125a is etched between the ashed photoresist patterns, as shown in FIG. 5C. Similarly, the common wiring 125 is formed.

In this case, the portion where the metal layer is etched is exposed to the transparent conductive material layer to form a counter electrode, and the portion where the metal layer remains is common wiring. The common wiring is formed in a non-opening region where an image is not displayed, and is formed parallel to the gate wiring 112. By this method, the common wiring can be formed directly on the upper surface of the counter electrode of the non-opening region.

Subsequently, as illustrated in FIG. 5D, an inorganic material such as silicon nitride or silicon oxide is deposited on the entire surface including the counter electrode and the common wiring, or an organic material such as BCB or acrylic resin is coated to form a second insulating film ( The contact hole 118 is formed by selectively removing the first and second insulating layers 116 and 120 so as to expose the drain electrode 115b of the thin film transistor 120.

A transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited thereon and patterned by photolithography to form a pixel electrode 117 having a plurality of slits 119. The direction of the slit is formed in the direction of the gate wiring or data wiring, and as shown in FIG. 3, the slits may be formed in an oblique direction to be inclined at a predetermined angle from the gate wiring and the data wiring direction to secure a wide viewing angle.

Thus, a TFT array substrate having a counter electrode and a pixel electrode is completed, an alignment film is formed on the entire surface of the TFT array substrate, an alignment film is also formed on the color filter layer array substrate facing the TFT array substrate, and then the two substrates are placed. After the adhesion, the liquid crystal layer is formed therebetween, thereby completing the transverse electric field type liquid crystal display device. Here, the color filter layer array substrate further includes a black matrix formed in the non-opening region to prevent light leakage and a color filter layer for colorfully expressing the image.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The liquid crystal display device and its manufacturing method according to the present invention as described above has the following effects.

By not forming a common wiring in the middle of the sub-pixels, the aperture ratio is improved and the contrast ratio of the device is also improved since no step difference due to the common wiring occurs in the opening region.

That is, since the common wiring of the opaque metal material is not formed in the opening region, the opening ratio of the device can be secured by the size of the common wiring.

In addition, since the step is not generated due to the common wiring in the opening area, the liquid crystal array disorder due to the step can be prevented and the thickness of the alignment layer can be prevented from being applied thinner than other areas, thereby preventing light leakage in the corresponding area. have.

As such, since light leakage does not occur in the opening region, the luminance in the black state can be lowered, thereby improving the contrast ratio of the device.

Claims (15)

Gate wiring and data wiring defining a sub-pixel that is vertically crossed on the substrate and divided into an opening region and a non-opening region; A thin film transistor disposed at an intersection point of the gate line and the data line; A counter electrode formed on the sub-pixel; A common wiring parallel to the gate wiring and formed on an upper surface of the counter electrode of the non-opening region; A pixel electrode insulated from the counter electrode and forming an electric field together with the counter electrode; And a liquid crystal layer interposed between the opposite substrate facing the substrate and the two substrates. The method of claim 1, Wherein one of the counter electrode and the pixel electrode has a plurality of slits, and the other has a plate shape. The method of claim 1, And the pixel electrode and the counter electrode are transparent conductive material layers. The method of claim 1, The common wiring is a liquid crystal display device, characterized in that the metal material. The method of claim 1, The counter electrode and the common wiring are on the same layer as the gate wiring. The method of claim 1, And the counter electrode and the common wiring are provided on an insulating film formed on the entire surface including the data wiring. Forming a gate wiring on the substrate; Forming a gate insulating film on the entire surface including the gate wiring; Forming data wirings on the gate insulating film to define sub-pixels intersecting the gate wirings and divided into an opening region and a non-opening region; Forming a thin film transistor at an intersection of the gate wiring and the data wiring; Forming a counter electrode on the sub-pixel, and forming a common wiring on an upper surface of the counter electrode of the non-opening region; And forming a pixel electrode which is insulated from the counter electrode and generates an electric field together with the counter electrode. The method of claim 7, wherein The counter electrode and the common wiring are simultaneously patterned by applying a photolithography process using a diffraction exposure mask. The method of claim 8, Forming the counter electrode and the common wiring, Sequentially forming a transparent conductive material layer and a metal layer on the substrate; Forming a double-thick photoresist pattern on the metal layer; Etching the transparent conductive material layer and the metal layer using the photoresist pattern as a mask; Exposing the metal layer by ashing the photoresist pattern; And etching the metal layer exposed between the ashed photoresist patterns to form a common wiring of the counter electrode of the transparent conductive material layer and the metal layer. The method of claim 9, The transparent conductive material layer is formed of indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 9, The metal layer is formed of copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) or molybdenum-tungsten (MoW) Method for manufacturing a liquid crystal display device, characterized in that. The method of claim 7, wherein And the common wiring is parallel to the gate wiring. The method of claim 7, wherein Any one of the counter electrode and the pixel electrode is patterned to have a plurality of slits, and the other is formed in a plate shape. The method of claim 7, wherein The forming of the counter electrode and the common wiring may be performed at the same time as the forming of the gate wiring. The method of claim 7, wherein Forming the counter electrode and the common wiring, And forming an insulating film on the entire surface including the data line.

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