KR20080041572A - Method for manufacturing electronic substrate - Google Patents

Method for manufacturing electronic substrate Download PDF

Info

Publication number
KR20080041572A
KR20080041572A KR1020070111894A KR20070111894A KR20080041572A KR 20080041572 A KR20080041572 A KR 20080041572A KR 1020070111894 A KR1020070111894 A KR 1020070111894A KR 20070111894 A KR20070111894 A KR 20070111894A KR 20080041572 A KR20080041572 A KR 20080041572A
Authority
KR
South Korea
Prior art keywords
electronic component
adhesive material
adhesive
manufacturing
electronic
Prior art date
Application number
KR1020070111894A
Other languages
Korean (ko)
Inventor
츠요시 신타테
Original Assignee
세이코 엡슨 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세이코 엡슨 가부시키가이샤 filed Critical 세이코 엡슨 가부시키가이샤
Publication of KR20080041572A publication Critical patent/KR20080041572A/en

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/12—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by using adhesives
    • B32B37/1284—Application of adhesive
    • B32B37/1292—Application of adhesive selectively, e.g. in stripes, in patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/02—Temperature
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/04—Time
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2310/00—Treatment by energy or chemical effects
    • B32B2310/08—Treatment by energy or chemical effects by wave energy or particle radiation
    • B32B2310/0806—Treatment by energy or chemical effects by wave energy or particle radiation using electromagnetic radiation
    • B32B2310/0831—Treatment by energy or chemical effects by wave energy or particle radiation using electromagnetic radiation using UV radiation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/24011—Deposited, e.g. MCM-D type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/27848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/76—Apparatus for connecting with build-up interconnects
    • H01L2224/7615—Means for depositing
    • H01L2224/76151—Means for direct writing
    • H01L2224/76155—Jetting means, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874—Ultraviolet [UV] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/013—Inkjet printing, e.g. for printing insulating material or resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1241—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing
    • H05K3/125—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing by ink-jet printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Die Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

A method for manufacturing an electronic substrate is provided to improve adhesiveness even with an electronic component having a joining surface of poor flatness and stably mount and fix the electronic component. A method for manufacturing an electronic substrate including an electronic component(P) bonded with an adhesive(C) to a base(B) includes the steps of: (a) applying a droplet containing the adhesive to an area on the base, which faces the electronic component within a range substantially equal to a size of the electronic component by using a droplet ejection head moving relatively to the base; (b) bringing the adhesive into a half-cured state; (c) mounting the electronic component on the adhesive applied to the base; and (d) applying hat energy to the adhesive.

Description

전자 기판의 제조 방법{METHOD FOR MANUFACTURING ELECTRONIC SUBSTRATE}Manufacturing method of an electronic substrate {METHOD FOR MANUFACTURING ELECTRONIC SUBSTRATE}

본 발명은 전자 기판의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing an electronic substrate.

최근, 전자 기기의 고성능화·소형화가 진행함에 따라, IC칩 등의 전자 부품을 탑재한 전자 기판에서도 고밀도·고기능화가 한층더 요구되고 있다.In recent years, as the performance and miniaturization of electronic devices have progressed, high-density and high-functionalization is required even in electronic boards equipped with electronic components such as IC chips.

이러한 기술로서는, 예를 들어 특허문헌 1에는, 기판재(材)에 형성된 구리 배선 상(上)에 전자 부품을 탑재하고, 그 위로부터 수지로 일괄적으로 피복하여 전자 부품 매립층을 형성하고, 이와 같이 하여 얻어진 전자 부품 매립층을 접착제에 의해 적층함으로써 전자 기판을 제조하고 있다.As such a technique, for example, Patent Literature 1 mounts an electronic component on a copper wiring formed on a substrate material, coats it with resin from above, and forms an electronic component embedding layer. An electronic board | substrate is manufactured by laminating | stacking the obtained electronic component embedding layer with an adhesive agent.

[특허문헌 1] 일본국 공개특허 평3-69191호 공보[Patent Document 1] Japanese Unexamined Patent Publication No. 3-69191

그러나, 상술한 바와 같은 종래 기술에는, 이하와 같은 문제가 존재한다.However, the following problems exist in the prior art as described above.

통상, 상기한 전자 부품은 실장되는 베이스부에 대하여 접착재(材)에 의해 고정된다. 이 접착재는 예를 들어 디스펜서(dispensor)에 의해 전자 부품 탑재 영역 내의 복수 개소(箇所)에서 점 형상으로 도포된다. 그런데, 이와 같이 도포된 접착재 위에 전자 부품을 실장한 경우, 접착재는 젖어 퍼지지만, 전자 부품과 베이스부 사이를 전부 충전할 수 없어 간극(間隙)이 형성되는 경우가 많다.Usually, the said electronic component is fixed by the adhesive material with respect to the base part to be mounted. This adhesive material is apply | coated to a point shape in several places in the electronic component mounting area | region by a dispenser, for example. By the way, when an electronic component is mounted on the apply | coated adhesive material in this way, although an adhesive material gets wet, it is not possible to fill all between an electronic component and a base part, and a gap is formed in many cases.

이 경우, 접착재를 경화시키기 위해 가열했을 때에, 간극에 남은 에어가 팽창함으로써, 경화된 접착재에 크랙(crack)이 생겨 접착 강도가 저하될 우려가 있었다.In this case, when heated to cure the adhesive, the air remaining in the gap expands, causing cracks in the cured adhesive, resulting in a drop in adhesive strength.

본 발명은 이상과 같은 점을 고려하여 이루어진 것으로서, 전자 부품을 안정적으로 실장·고정할 수 있는 전자 기판의 제조 방법을 제공하는 것을 목적으로 한다.This invention is made | formed in view of the above points, and an object of this invention is to provide the manufacturing method of the electronic board | substrate which can mount and fix an electronic component stably.

상기한 목적을 달성하기 위해 본 발명은 이하의 구성을 채용하고 있다.In order to achieve the above object, the present invention employs the following configurations.

본 발명의 전자 기판의 제조 방법은, 전자 부품이 접착재(材)를 통하여 베이스부에 접착되어 이루어지는 전자 기판의 제조 방법으로서, 상기 베이스부와 상대 이동하는 액적(液滴) 토출 헤드를 사용하여, 상기 접착재를 포함하는 액적을 상기 베이스부의 상기 전자 부품과 대향하는 영역에 상기 전자 부품과 거의 동일한 크기 로 도포하는 도포 공정과, 상기 베이스부에 도포된 상기 접착재 위에 상기 전자 부품을 탑재하는 탑재 공정을 갖는 것을 특징으로 하는 것이다.The manufacturing method of the electronic board | substrate of this invention is a manufacturing method of the electronic board | substrate with which an electronic component is adhere | attached to a base part through an adhesive material, Using the droplet discharge head which moves relatively with the said base part, An application step of applying the droplet including the adhesive material to a region facing the electronic part of the base part in substantially the same size as the electronic part, and a mounting step of mounting the electronic part on the adhesive material applied to the base part; It is characterized by having.

따라서, 본 발명의 전자 기판의 제조 방법에서는, 접착재를 포함하는 액적이 상기 베이스부에 상기 전자 부품과 거의 동일한 크기로 도포되기 때문에, 탑재한 전자 부품과 베이스부 사이에 공기가 혼입되는 것을 회피할 수 있다. 따라서, 접착재를 경화하기 위해 열 등을 부여한 경우에도, 공기의 팽창 등에 기인하여 크랙(crack)이 생기는 것을 방지할 수 있고, 전자 부품의 접착 강도를 안정된 상태로 유지하는 것이 가능해진다.Therefore, in the method for manufacturing an electronic substrate of the present invention, since droplets containing an adhesive material are applied to the base portion at almost the same size as the electronic component, it is possible to avoid mixing air between the mounted electronic component and the base portion. Can be. Therefore, even when heat or the like is applied to cure the adhesive, cracks can be prevented due to expansion of air or the like, and the adhesive strength of the electronic component can be maintained in a stable state.

또한, 본 발명에서는, 액적 토출 방식에 의해 상기 접착재를 포함하는 액적을 도포하기 때문에, 인쇄법이나 포토리소그래피법 등과 같이, 마스크나 레지스트 등을 사용하지 않고, 용이하게 접착재를 패터닝할 수 있으며, 또한 소비되는 접착재에 낭비가 생기지 않기 때문에, 비용 저감에도 기여할 수 있다.Further, in the present invention, since the droplet containing the adhesive is coated by the droplet ejecting method, the adhesive can be easily patterned without using a mask, a resist or the like, such as a printing method or a photolithography method. Since waste does not arise in the adhesive used, it can contribute to cost reduction.

또한, 본 발명에서는, 도포한 상기 접착재를, 상기 탑재 배치 공정 전에 반(半)경화 상태로 하는 반경화 공정을 갖는 순서도 적절하게 채용할 수 있다.Moreover, in this invention, the procedure which has the semi-hardening process of making the apply | coated adhesive material into the semihardening state before the mounting arrangement process can also be employ | adopted suitably.

이에 따라, 본 발명에서는, 반경화 상태의 접착재에 대하여 전자 부품을 탑재하는 것으로 되기 때문에, 전자 부품이 접착재에 밀착되기 쉬워져, 접착성을 향상시키는 것이 가능해진다. 또한, 도포한 접착재의 점도나, 전자 부품 탑재 시의 압력에 따라서는, 전자 부품이 접착재에 묻히게 되어, 전자 부품의 측면(側面)에도 접착재가 밀착되기 때문에, 접착 강도를 더 높일 수 있는 동시에, 접착재가 열수축 한 경우에는, 그 수축력이 전자 부품의 유지력으로 되기 때문에, 한층더 접착 강도 를 높일 수 있다.As a result, in the present invention, since the electronic component is mounted on the adhesive material in the semi-cured state, the electronic component easily adheres to the adhesive material, thereby making it possible to improve the adhesiveness. In addition, depending on the viscosity of the coated adhesive material and the pressure at the time of mounting the electronic component, the electronic component is buried in the adhesive material, and the adhesive material adheres to the side surfaces of the electronic component, so that the adhesive strength can be further increased. In the case where the adhesive material is thermally contracted, the shrinkage force becomes the holding force of the electronic component, so that the adhesive strength can be further increased.

상기 반경화 공정에서는, 상기 접착재를 포함하는 액적이 경화되는 에너지량보다도 작은 에너지량을 부여하고, 상기 탑재 공정 후에 상기 접착재를 포함하는 액적이 경화되는 에너지량을 부여하는 순서도 적절하게 채용할 수 있다.In the said semi-hardening process, the order which gives an energy amount smaller than the energy amount hardened | cured by the droplet containing the said adhesive material and gives the energy amount hardened by the droplet containing the said adhesive material after the said mounting process can also be employ | adopted suitably. .

이 경우, 상기 접착재를 포함하는 액적에 광에너지와 열에너지 중 적어도 한쪽을 부여하는 구성을 채용할 수 있다.In this case, the structure which provides at least one of light energy and heat energy to the droplet containing the said adhesive material can be employ | adopted.

따라서, 본 발명의 전자 기판의 제조 방법에서는, 상기 접착재를 포함하는 액적이 경화되는 에너지량보다도 작은 에너지량을 부여함으로써, 도포한 접착재를 반경화 상태로 할 수 있고, 또한 전자 부품 탑재 후에, 추가의 에너지량을 부여함으로써, 접착재를 경화시켜 전자 부품을 베이스부에 고정할 수 있다.Therefore, in the manufacturing method of the electronic board | substrate of this invention, by applying the energy amount smaller than the energy amount hardened | cured by the droplet containing the said adhesive material, the apply | coated adhesive material can be made into the semi-hardened state, and also after electronic component mounting, By providing an energy amount of, the adhesive material can be cured to fix the electronic component to the base part.

또한, 본 발명에서는, 상기 베이스부는 절연재(材)로 형성되고, 상기 접착재는 상기 절연재인 구성을 적절하게 채용할 수 있다.Moreover, in this invention, the said base part is formed with the insulating material, and the said adhesive material can employ | adopt the structure which is the said insulating material suitably.

따라서, 본 발명의 전자 기판의 제조 방법에서는, 베이스부와 접착재를 동일한 재료로 형성할 수 있기 때문에, 사용하는 재료의 종류를 줄일 수 있고, 제조 효율의 향상에 기여할 수 있다.Therefore, in the manufacturing method of the electronic board | substrate of this invention, since a base part and an adhesive material can be formed from the same material, the kind of material to be used can be reduced and it can contribute to the improvement of manufacturing efficiency.

또한, 본 발명에서는, 상기 전자 부품에 전기적으로 접속되는 도전 배선을 갖고, 상기 접착재는 상기 도전 배선을 형성하는 재료를 포함하는 구성을 적절하게 채용할 수 있다.Moreover, in this invention, the structure which has electrically conductive wiring electrically connected to the said electronic component, and the said adhesive material containing the material which forms the said electrically conductive wiring can be employ | adopted suitably.

따라서, 본 발명의 전자 기판의 제조 방법에서는, 도전 배선과 접착재를 동일한 재료로 형성할 수 있기 때문에, 사용하는 재료의 종류를 줄일 수 있고, 제조 효율의 향상에 기여할 수 있다. 상기한 구성에서는, 상기 도전 배선이 절연층을 통하여 복수 적층하여 설치되는 구성도 적절하게 채용할 수 있다.Therefore, in the manufacturing method of the electronic board | substrate of this invention, since an electrically conductive wiring and an adhesive material can be formed from the same material, the kind of material used can be reduced and it can contribute to the improvement of manufacturing efficiency. In the above-described configuration, a configuration in which a plurality of conductive wires are laminated through an insulating layer can also be appropriately employed.

이에 따라, 본 발명에서는, 소위 다층 배선 기판을 제조할 때에도, 제조 효율의 향상에 기여할 수 있다.Therefore, in this invention, even when manufacturing what is called a multilayer wiring board, it can contribute to the improvement of manufacturing efficiency.

또한, 본 발명에서는, 상기 도전 배선 및 상기 절연층을, 상기 액적 토출 헤드를 사용하여 성막(成膜)하는 순서도 적절하게 채용할 수 있다.Moreover, in this invention, the order which forms the said conductive wiring and the said insulating layer using the said droplet discharge head can also be employ | adopted suitably.

이에 따라, 본 발명에서는, 다층 배선 기판을 액적 토출 방식만에 의해 성막, 형성하는 것이 가능해지고, 제조 효율의 향상에 기여할 수 있다.Accordingly, in the present invention, it is possible to form and form a multilayer wiring substrate only by the droplet discharging method, thereby contributing to the improvement of manufacturing efficiency.

이하, 본 발명의 전자 기판의 제조 방법의 실시예를, 도 1 내지 도 5를 참조하여 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, the Example of the manufacturing method of the electronic substrate of this invention is described with reference to FIGS.

또한, 이하의 설명에 사용하는 각 도면에서는, 각 부재를 인식 가능한 크기로 하기 위해, 각 부재의 축척을 적절하게 변경하고 있다.In addition, in each figure used for the following description, in order to make each member the magnitude | size which can be recognized, the scale of each member is changed suitably.

(액적 토출 장치)(Droplet ejection device)

우선, 본 발명에 따른 전자 기판의 제조 방법에서 사용되는 액적(液滴) 토출 장치에 대해서 도 1 및 도 2를 참조하여 설명한다.First, the droplet ejection apparatus used in the manufacturing method of the electronic substrate which concerns on this invention is demonstrated with reference to FIG.

도 1에 나타낸 액적 토출 장치(1)는 기본적으로는 잉크젯 장치이다. 더 구체적으로는, 액적 토출 장치(1)는 액상 재료(111)를 유지하는 탱크(101)와, 튜브(110)와, 그라운드 스테이지(GS)와, 토출 헤드부(액적 토출 헤드)(103)와, 스테이지(106)와, 제 1 위치 제어 장치(104)와, 제 2 위치 제어 장치(108)와, 제어 부(112)와, 광 조사 장치(140)와, 지지부(104a)를 구비하고 있다.The droplet ejection apparatus 1 shown in FIG. 1 is basically an inkjet apparatus. More specifically, the droplet ejection apparatus 1 includes a tank 101 holding the liquid material 111, a tube 110, a ground stage GS, and an ejection head portion (droplet ejection head) 103. And a stage 106, a first position control device 104, a second position control device 108, a control unit 112, a light irradiation device 140, and a support unit 104a. have.

토출 헤드부(103)는 헤드(114)(도 2 참조)를 유지하고 있다. 이 헤드(114)는 제어부(112)로부터의 신호에 따라, 액상 재료(111)의 액적을 토출한다. 또한, 토출 헤드부(103)에서의 헤드(114)는 튜브(110)에 의해 탱크(101)에 연결되어 있고, 따라서 탱크(101)로부터 헤드(114)에 액상 재료(111)가 공급된다.The discharge head part 103 holds the head 114 (refer FIG. 2). The head 114 discharges the droplets of the liquid material 111 in response to a signal from the control unit 112. In addition, the head 114 in the discharge head portion 103 is connected to the tank 101 by the tube 110, so that the liquid material 111 is supplied from the tank 101 to the head 114.

스테이지(106)는 기판(후술)을 고정하기 위한 평면을 제공하고 있다. 또한, 스테이지(106)는 흡인력을 이용하여 기판의 위치를 고정하는 기능도 갖는다.The stage 106 provides a plane for fixing the substrate (to be described later). In addition, the stage 106 also has a function of fixing the position of the substrate by using a suction force.

제 1 위치 제어 장치(104)는 지지부(104a)에 의해, 그라운드 스테이지(GS)로부터 소정 높이의 위치에 고정되어 있다. 이 제 1 위치 제어 장치(104)는 제어부(112)로부터의 신호에 따라, 토출 헤드부(103)를 X축 방향과, X축 방향에 직교하는 Z축 방향을 따라 이동시키는 기능을 갖는다. 또한, 제 1 위치 제어 장치(104)는 Z축에 평행한 축의 둘레에서 토출 헤드부(103)를 회전시키는 기능도 갖는다. 여기서, 본 실시예에서는, Z축 방향은 연직(鉛直) 방향(즉, 중력가속도의 방향)에 평행한 방향이다.The 1st position control apparatus 104 is being fixed to the position of predetermined height from the ground stage GS by the support part 104a. This 1st position control apparatus 104 has a function which moves the discharge head part 103 along an X-axis direction and the Z-axis direction orthogonal to an X-axis direction according to the signal from the control part 112. FIG. The first position control device 104 also has a function of rotating the discharge head portion 103 around an axis parallel to the Z axis. Here, in this embodiment, the Z-axis direction is a direction parallel to the vertical direction (that is, the direction of gravity acceleration).

제 2 위치 제어 장치(108)는 제어부(112)로부터의 신호에 따라, 스테이지(106)를 그라운드 스테이지(GS) 상에서 Y축 방향으로 이동시킨다. 여기서, Y축 방향은 X축 방향 및 Z축 방향의 쌍방과 직교하는 방향이다.The second position control device 108 moves the stage 106 in the Y-axis direction on the ground stage GS in response to a signal from the control unit 112. Here, the Y-axis direction is a direction orthogonal to both the X-axis direction and the Z-axis direction.

상술한 바와 같이, 제 1 위치 제어 장치(104)에 의해, 토출 헤드부(103)는 X축 방향으로 이동한다. 그리고, 제 2 위치 제어 장치(108)에 의해, 기판은 스테이지(106)와 함께 Y축 방향으로 이동한다. 이러한 결과, 기판에 대한 헤드(114)의 상대 위치가 바뀐다. 더 구체적으로는, 이러한 동작에 의해, 토출 헤드부(103), 헤드(114), 또는 노즐(118)(도 2 참조)은 기판에 대하여, Z축 방향에 소정의 거리를 유지하면서, X축 방향 및 Y축 방향으로 상대적으로 이동, 즉 상대적으로 주사(走査)한다. 「상대 이동」 또는 「상대 주사」는 액상 재료(111)를 토출하는 측과, 그곳으로부터의 토출물이 착탄하는 측(피토출부) 중 적어도 한쪽을 다른 쪽에 대하여 상대 이동하는 것을 의미한다.As described above, the discharge head portion 103 moves in the X-axis direction by the first position control device 104. The substrate moves in the Y-axis direction together with the stage 106 by the second position control device 108. As a result, the relative position of the head 114 relative to the substrate is changed. More specifically, by this operation, the discharge head 103, the head 114, or the nozzle 118 (see FIG. 2) maintains the X axis while maintaining a predetermined distance in the Z axis direction with respect to the substrate. And move relatively in the direction and Y-axis direction, that is, scan relatively. "Relative movement" or "relative scanning" means relatively moving at least one of the side which discharges the liquid material 111, and the side (discharge part) to which the discharge object from there arrives.

제어부(112)는 액상 재료(111)의 액적을 토출해야할 상대 위치를 나타내는 토출 데이터를 외부 정보 처리 장치로부터 수취(受取)하도록 구성되어 있다. 제어부(112)는 수취한 토출 데이터를 내부의 기억 장치에 저장하는 동시에, 저장된 토출 데이터에 따라, 제 1 위치 제어 장치(104)와, 제 2 위치 제어 장치(108)와, 헤드(114)를 제어한다. 또한, 토출 데이터는 기판 상에 액상 재료(111)를 소정 패턴으로 부여하기 위한 데이터이다. 본 실시예에서는, 토출 데이터는 비트맵 데이터의 형태를 갖고 있다.The control part 112 is comprised so that discharge data which shows the relative position which should discharge the droplet of the liquid material 111 is received from an external information processing apparatus. The control unit 112 stores the received discharge data in an internal storage device and simultaneously stores the first position control device 104, the second position control device 108, and the head 114 in accordance with the stored discharge data. To control. The discharge data is data for applying the liquid material 111 in a predetermined pattern on the substrate. In this embodiment, the ejection data has the form of bitmap data.

상기 구성을 갖는 액적 토출 장치(1)는 토출 데이터에 따라, 헤드(114)의 노즐(118)(도 2 참조)을 기판에 대하여 상대 이동시키는 동시에, 피(被)토출부를 향하여 노즐(118)로부터 액상 재료(111)를 토출한다. 또한, 액적 토출 장치(1)에 의한 헤드(114)의 상대 이동과, 헤드(114)로부터의 액상 재료(111)의 토출을 통틀어 「도포 주사」 또는 「토출 주사」라고 표기하는 경우도 있다.The droplet ejection apparatus 1 having the above structure relatively moves the nozzle 118 (see FIG. 2) of the head 114 with respect to the substrate in accordance with the ejection data, and simultaneously moves the nozzle 118 toward the discharged portion. The liquid material 111 is discharged from the. In addition, the relative movement of the head 114 by the droplet ejection apparatus 1 and the ejection of the liquid material 111 from the head 114 may be described as "coating scan" or "discharge scanning."

광 조사 장치(140)는 기판에 부여된 액상 재료(111)에 자외광을 조사하는 장치이다. 광 조사 장치(140)의 자외광의 조사의 온(on)·오프(off)는 제어부(112) 에 의해 제어된다.The light irradiation apparatus 140 is an apparatus which irradiates an ultraviolet light to the liquid material 111 provided to the board | substrate. The on / off of the irradiation of the ultraviolet light of the light irradiation apparatus 140 is controlled by the control part 112. FIG.

도 2의 (a) 및 (b)에 나타낸 바와 같이, 액적 토출 장치(1)에서의 헤드(114)는 복수의 노즐(118)을 갖는 잉크젯 헤드이다. 구체적으로는, 헤드(114)는 진동판(126)과, 복수의 노즐(118)과, 복수의 노즐(118)의 각각의 개구를 규정하는 노즐 플레이트(128)와, 액체 저장소(129)와, 복수의 격벽(122)과, 복수의 캐비티(120)와, 복수의 진동자(振動子)(124)를 구비하고 있다.As shown in FIGS. 2A and 2B, the head 114 in the droplet ejection apparatus 1 is an inkjet head having a plurality of nozzles 118. Specifically, the head 114 includes a diaphragm 126, a plurality of nozzles 118, nozzle plates 128 defining respective openings of the plurality of nozzles 118, a liquid reservoir 129, A plurality of partitions 122, a plurality of cavities 120, and a plurality of vibrators 124 are provided.

액체 저장소(129)는 진동판(126)과 노즐 플레이트(128) 사이에 위치하고 있고, 이 액체 저장소(129)에는, 외부 탱크(도시 생략)로부터 구멍(131)을 통하여 공급되는 액상 재료(111)가 항상 충전된다. 또한, 복수의 격벽(122)은 진동판(126)과 노즐 플레이트(128) 사이에 위치하고 있다.The liquid reservoir 129 is located between the diaphragm 126 and the nozzle plate 128, in which the liquid material 111 is supplied from the outer tank (not shown) through the hole 131. It is always charged. In addition, the plurality of partitions 122 are positioned between the diaphragm 126 and the nozzle plate 128.

캐비티(120)는 진동판(126)과, 노즐 플레이트(128)와, 한 쌍의 격벽(122)에 의해 둘러싸인 부분이다. 캐비티(120)는 노즐(118)에 대응하여 설치되어 있기 때문에, 캐비티(120)의 수와 노즐(118)의 수는 동일하다. 캐비티(120)에는, 한 쌍의 격벽(122) 사이에 위치하는 공급구(130)를 통하여, 액체 저장소(129)로부터 액상 재료(111)가 공급된다. 또한, 본 실시예에서는, 노즐(118)의 직경은 예를 들어 약 27㎛이다.The cavity 120 is a part surrounded by the diaphragm 126, the nozzle plate 128, and the pair of partition walls 122. Since the cavity 120 is provided corresponding to the nozzle 118, the number of the cavity 120 and the number of the nozzles 118 are the same. The liquid material 111 is supplied to the cavity 120 from the liquid reservoir 129 through a supply port 130 positioned between the pair of partition walls 122. In addition, in this embodiment, the diameter of the nozzle 118 is about 27 micrometers, for example.

또한, 복수의 진동자(124)의 각각은 각각의 캐비티(120)에 대응하도록 진동판(126) 상에 위치한다. 복수의 진동자(124)의 각각은 피에조 소자(124C)와, 피에조 소자(124C)를 사이에 끼운 한 쌍의 전극(124A, 124B)을 포함한다. 제어부(112)가 이 한 쌍의 전극(124A, 124B)의 사이에 구동 전압을 부여함으로써, 대응하는 노 즐(118)로부터 액상 재료(111)의 액적(D)이 토출된다. 여기서, 노즐(118)로부터 토출되는 재료의 부피는 0pl 이상 42pl(피코리터) 이하의 사이에서 가변(可變)한다. 또한, 노즐(118)로부터 Z축 방향으로 액상 재료(111)의 액적이 토출되도록, 노즐(118)의 형상이 조정되어 있다.In addition, each of the plurality of vibrators 124 is located on the diaphragm 126 to correspond to each cavity 120. Each of the plurality of vibrators 124 includes a piezo element 124C and a pair of electrodes 124A and 124B sandwiched between the piezo element 124C. The control unit 112 applies a driving voltage between the pair of electrodes 124A and 124B, so that the droplet D of the liquid material 111 is discharged from the corresponding nozzle 118. Here, the volume of the material discharged from the nozzle 118 varies between 0 pl and 42 pl (picoliter) or less. Moreover, the shape of the nozzle 118 is adjusted so that the droplet of the liquid material 111 may be discharged from the nozzle 118 in the Z-axis direction.

또한, 토출부(127)는 피에조 소자의 대신에 전기열 변환 소자를 가질 수도 있다. 즉, 토출부(127)는 전기열 변환 소자에 의한 재료의 열팽창을 이용하여 재료를 토출하는 구성을 갖고 있을 수도 있다.In addition, the discharge part 127 may have an electrothermal conversion element instead of the piezo element. That is, the discharge part 127 may have the structure which discharges material using the thermal expansion of the material by an electrothermal conversion element.

(전자 기판의 제조 방법)(Method for Manufacturing Electronic Substrate)

다음으로, 상기한 액적 토출 장치(1)를 사용하여 전자 기판을 제조하는 순서 중, 우선 전자 부품을 베이스부에 고정하는 순서에 대해서 설명한다.Next, of the procedure of manufacturing an electronic board | substrate using the said droplet discharge apparatus 1, the procedure which fixes an electronic component to a base part first is demonstrated.

도 3은 전자 기판의 제조 방법을 나타내는 공정도이다.3 is a process chart showing a manufacturing method of an electronic substrate.

도 3의 (a)에 나타낸 바와 같이, 우선 상기 액적 토출 장치(1)의 헤드(114)로부터 베이스부(B) 상에 접착재(材)를 포함하는 액적(C)(이후, 간단히 접착재(C)라고 함)을 도포한다(도포 공정).As shown in Fig. 3A, first, a droplet C containing an adhesive on the base portion B from the head 114 of the droplet ejection apparatus 1 (hereinafter, simply an adhesive C ) Is applied (coating step).

여기서, 접착재(C)는 나중에 베이스부(B) 상에 탑재하는 전자 부품(P)(도 3의 (c) 참조)과 대향하는 영역에 당해(當該) 전자 부품(P)과 거의 동일한 크기로 도포된다.Here, the adhesive material C is almost the same size as the electronic component P in the region facing the electronic component P (see FIG. 3C) to be mounted later on the base portion B. FIG. Is applied.

이 경우의 베이스부(B)로서는, 유리 기판이나 반도체 기판 등의 기판이나, 기판 상에 성막된 절연막일 수도 있다. 접착재(C)로서는, 여기서는 광에너지를 부여했을 때에 경화되는 광경화성, 및 열에너지를 부여했을 때에 경화되는 열경화성 을 갖는 재료로서, 아크릴계의 감광성 수지를 포함하고 있다.In this case, the base portion B may be a substrate such as a glass substrate or a semiconductor substrate, or an insulating film formed on the substrate. As the adhesive material (C), an acrylic photosensitive resin is included here as a material having photocurability which is cured when light energy is applied and thermosetting which is cured when heat energy is applied.

이 광경화성 재료는 용제(溶劑)와, 용제에 용해한 수지를 함유할 수도 있다. 여기서, 이 경우의 광경화성 재료는 그 자체가 감광하여 중합도(重合度)를 올리는 수지를 함유할 수도 있고, 또는 수지와, 그 수지의 경화를 개시(開始)시키는 광중합 개시제를 함유하고 있을 수도 있다. 또한, 광경화성 재료로서, 광중합하여 불용의 절연 수지를 생성하는 모노머와, 그 모노머의 광중합을 개시시키는 광중합 개시제를 함유할 수도 있다. 다만, 이 경우의 광경화성 재료는 모노머 자체가 광관능기를 갖고 있으면, 광중합 개시제를 함유하지 않아도 된다.This photocurable material may contain a solvent and resin melt | dissolved in the solvent. Here, the photocurable material in this case may contain resin which photosensitizes itself, and raises a polymerization degree, or may contain resin and the photoinitiator which initiates hardening of the resin. . Moreover, as a photocurable material, you may contain the monomer which photopolymerizes and produces insoluble insulating resin, and the photoinitiator which starts photopolymerization of this monomer. However, the photocurable material in this case does not need to contain a photoinitiator as long as the monomer itself has a photofunctional group.

이어서, 도 3의 (b)에 나타낸 바와 같이, 자외역(紫外域)의 파장을 갖는 광(L)을 소정 시간 조사하여 소정 에너지량을 부여함으로써, 도포한 접착재(C)를 반경화 상태로 한다(반경화 공정). 이 때, 접착재(C)에 대하여 부여하는 에너지량은 접착재(C)가 경화되는 에너지량보다도 작은 값으로 설정된다.Subsequently, as shown in FIG. 3 (b), the applied adhesive C is semi-cured by irradiating light L having a wavelength in the ultraviolet region for a predetermined time to give a predetermined amount of energy. (Semi-curing step). At this time, the amount of energy applied to the adhesive material C is set to a value smaller than the amount of energy that the adhesive material C is cured.

본 실시예에서는, 접착재(C)에 조사하는 광의 파장은 예를 들어 365㎚이다.In the present Example, the wavelength of the light irradiated to the adhesive material C is 365 nm, for example.

여기서, 접착재(C)의 반경화는 접착재(C)에 포함되는 광경화성 재료의 상태가 토출 시의 상태와 완전한 경화 상태 사이의 상태가 되는 것을 의미한다. 본 실시예에서는, 이러한 중간의 상태가 상술한 반경화 상태이다. 또한, 토출 시의 상태는 광경화성 재료가 노즐(118)로부터 토출될 수 있는 점성을 갖고 있는 상태이다.Here, the semi-curing of the adhesive material C means that the state of the photocurable material included in the adhesive material C becomes a state between the state at the time of discharge and the complete curing state. In this embodiment, this intermediate state is the above-mentioned semi-cured state. In addition, the state at the time of discharge is a state which has the viscosity which can be discharged from the nozzle 118 by the photocurable material.

다음으로, 도 3의 (c)에 나타낸 바와 같이, 반경화 상태의 접착재(C) 상에 전자 부품(P)을 탑재 배치·탑재한다(탑재 공정). 이 전자 부품(P)의 탑재는 마운 터(mounter) 등을 사용하여 실시된다. 또한, 전자 부품(P)은 접착재(C) 상에 탑재 배치하는 것만일 수도 있고, 가압하여 탑재할 수도 있다. 전자 부품(P)을 가압하여 탑재한 경우에는, 전자 부품(P)이 접착재(C)에 매립되고, 전자 부품(P)과 접착재(C)의 접촉 면적이 커지기 때문에, 전자 부품(P)을 고정시키기 더 쉬워진다.Next, as shown in FIG.3 (c), the electronic component P is mounted and arrange | positioned and mounted on the adhesive material C of a semi-hardened state (mounting process). The electronic component P is mounted using a mounter or the like. In addition, the electronic component P may be mounted only on the adhesive material C, or may be mounted under pressure. When the electronic component P is mounted under pressure, the electronic component P is embedded in the adhesive material C, and the contact area between the electronic component P and the adhesive material C becomes large, so that the electronic component P is mounted. It is easier to fix.

어떤 탑재 방법이어도, 접착재(C)가 반경화 상태에서 연성(軟性)이기 때문에, 전자 부품(P)의 저면(底面)(접착재(C)와의 접착면)의 평탄성이 나쁘고 요철이 있던 경우에도, 접착재(C)가 당해 접착면을 따르기 때문에 접촉 면적이 늘어나 밀착성을 올릴 수 있다.In any mounting method, since the adhesive material C is ductile in a semi-cured state, even when the bottom surface of the electronic component P (adhesive surface with the adhesive material C) is bad and irregularities are present, Since the adhesive material (C) follows the said adhesive surface, a contact area can increase and adhesiveness can be improved.

이어서, 도 3의 (d)에 나타낸 바와 같이, 베이스부(B) 측으로부터 가열함으로써, 접착재(C)에 열에너지를 부여한다. 이 에너지량은 반경화 상태였던 접착재(C)가 경화되는 양으로 설정된다. 이 가열 처리로서는, 예를 들어 클린 오븐을 사용하여, 150℃의 온도에서 60분간 가열한다. 이 가열에 의해, 접착재(C)에서의 수지의 중합 반응이 더 진행되기 때문에, 수지가 경화된다. 이 결과, 접착재(C)가 절연재로 형성된 전자 부품(P)과 베이스부(B)의 접합층으로 된다.Next, as shown in FIG.3 (d), heat energy is given to the adhesive material C by heating from the base part B side. This amount of energy is set to the amount by which the adhesive material C, which was in the semi-cured state, is cured. As this heat processing, it heats for 60 minutes at the temperature of 150 degreeC, for example using a clean oven. By this heating, since the polymerization reaction of the resin in the adhesive (C) further proceeds, the resin is cured. As a result, the adhesive material C becomes a bonding layer of the electronic component P and the base part B formed of the insulating material.

(다층 배선 기판의 제조 방법)(Manufacturing method of a multilayer wiring board)

다음으로, 상기한 전자 기판의 제조 방법을 이용하여 다층 배선 기판을 제조하는 방법에 대해서, 도 4 및 도 5를 참조하여 설명한다.Next, the method of manufacturing a multilayer wiring board using the manufacturing method of an electronic board | substrate mentioned above is demonstrated with reference to FIG. 4 and FIG.

여기서는, 베이스부로서의 절연층 상에, 전자 부품으로서의 IC칩을 탑재하는 예를 사용하여 설명한다.Here, description will be given using an example in which an IC chip as an electronic component is mounted on an insulating layer as a base portion.

우선, 도 4의 (a)에 나타낸 바와 같이, 실리콘으로 이루어지는 기재(基 材)(10) 상에 칩 부품(20, 21)을 배치한다. 이 때, 상기 칩 부품(20, 21)의 이면(裏面)에는, 예를 들어 접착 테이프 등이 설치되고, 이에 따라 기재(10) 상에 고정된다. 또한, 상기 칩 부품(20, 21)을 배치하는 기재로서는, 그 외에도 유리, 석영유리, 금속판 등 각종의 것을 들 수 있다. 또한, 이들 각종의 소재 기판의 표면에 반도체막, 금속막, 절연막, 유기막 등이 하지층(下地層)으로서 형성된 것도 포함한다.First, as shown in Fig. 4A, the chip components 20 and 21 are disposed on a base 10 made of silicon. At this time, the adhesive tape etc. are provided in the back surface of the said chip components 20 and 21, for example, and are fixed on the base material 10. As shown in FIG. Moreover, as a base material which arrange | positions the said chip component 20, 21, various things, such as glass, quartz glass, a metal plate, are mentioned besides. Moreover, the thing in which a semiconductor film, a metal film, an insulating film, an organic film, etc. were formed as a base layer on the surface of these various raw material substrates is also included.

상기 칩 부품(20, 21)으로서는, 저항, 콘덴서, IC칩 등을 들 수 있고, 본 실시예에서는, 칩 부품(20)으로서 저항을 사용하고, 칩 부품(21)으로서 콘덴서를 사용했다. 또한, 칩 부품(20, 21)은 그 전극부(도전부)(20a, 21a)를 상방으로 향한 상태로 기재(10) 상에 배치되어 있다.Examples of the chip components 20 and 21 include a resistor, a capacitor, an IC chip, and the like. In this embodiment, a resistor is used as the chip component 20 and a capacitor is used as the chip component 21. Moreover, the chip components 20 and 21 are arrange | positioned on the base material 10 with the electrode part (conductive part) 20a, 21a facing upwards.

또한, 실제로는 전극부(20a, 21a)는 칩 부품(20, 21)의 상면(上面)과 거의 동일 면을 이루지만, 여기서는 돌기 형상으로 도시하고 있다. 또한, 액적 토출 방식 등을 이용하여 도전성 잉크를 토출함으로써 실제로 돌기를 형성할 수도 있다.In addition, although the electrode part 20a, 21a actually forms substantially the same surface as the upper surface of the chip component 20, 21, it is shown in the protrusion shape here. In addition, the projections may be actually formed by ejecting the conductive ink using a droplet ejection method or the like.

다음으로, 액적 토출 장치(1)에 의한 액적 토출 방식을 이용하여 상기 칩 부품(20, 21)의 주위에, 상기 칩 부품(20, 21)과 거의 동일한 높이로 되도록 절연성 잉크(절연 재료)를 도포하고, 상기 절연성 잉크를 경화시킴으로써 절연막을 형성한다.Next, insulating ink (insulating material) is applied around the chip parts 20 and 21 so as to be almost the same height as the chip parts 20 and 21 by using the droplet discharge method by the droplet discharge device 1. The insulating film is formed by applying and curing the insulating ink.

이 절연성 잉크로서는, 건조 후에 SiO2, SiN, Si3N4로 되는 액상 재료, 폴리이미드 수지계, 에폭시 수지계, 폴리에스테르 수지계, 페놀 수지계, 불소 수지계, 자외선 경화 수지 등을 사용할 수 있다. 본 실시예에서는, 절연성 잉크로서, 예를 들어 폴리이미드를 용제(N-메틸-2-피롤리돈)에 희석하고, 점도가 20[m㎩·s]으로 되도록 조정한 것을 사용했다.As this insulating ink, a liquid material made of SiO 2 , SiN, Si 3 N 4 after drying, a polyimide resin, an epoxy resin, a polyester resin, a phenol resin, a fluororesin, an ultraviolet curable resin, or the like can be used. In the present Example, as an insulating ink, the polyimide was diluted in the solvent (N-methyl- 2-pyrrolidone), for example, and what adjusted so that it might become 20 [mPa * s] was used.

그리고, 절연성 잉크를 경화함으로써, 형성된 절연막(13)은, 도 4의 (b)에 나타낸 바와 같이, 칩 부품(20, 21)을 매립하는 동시에, 전극부(20a, 21a)를 돌출시킨다.The insulating film 13 formed by curing the insulating ink fills the chip parts 20 and 21 and protrudes the electrode portions 20a and 21a as shown in Fig. 4B.

다음으로, 상기 절연막(13) 상에 전극부(20a, 21a)에 접속하는 배선을 형성한다. 본 실시예에서는, 상기 접착재(C) 및 절연막(13)과 마찬가지로, 액적 토출 장치(1)에 의한 액적 토출 방식을 이용하여 도전성 잉크를 토출함으로써 배선을 형성한다.Next, wirings are formed on the insulating film 13 to connect the electrode portions 20a and 21a. In this embodiment, similarly to the adhesive material C and the insulating film 13, the wiring is formed by discharging the conductive ink using the droplet discharging method by the droplet discharging device 1.

본 실시예에서는, 직경 10㎚ 정도의 은(銀) 미립자가 유기용제에 분산된 은 미립자 분산액의 분산매를 테트라데칸으로 치환하여 이것을 희석하고, 농도가 60wt%、점도가 8m㎩·s, 표면장력이 0.022N/m으로 되도록 조정한 것을 도전성 잉크로서 사용했다.In this embodiment, silver fine particles having a diameter of about 10 nm are substituted with tetradecane to disperse the dispersion medium of the silver fine particle dispersion dispersed in the organic solvent, and the concentration is 60 wt%, viscosity is 8 mPa · s, surface tension What was adjusted so that it might be 0.022 N / m was used as electroconductive ink.

구체적으로는, 상기 칩 부품(20, 21)의 전극부(20a, 21a) 상에 도전성 잉크를 토출하고, 소성함으로써, 도 4의 (c)에 나타낸 바와 같이, 상기 칩 부품(20, 21)과 전기적으로 접속되는 Ag 배선(도전 배선)(15)을 형성할 수 있다.Specifically, by discharging and firing conductive ink on the electrode portions 20a and 21a of the chip components 20 and 21, the chip components 20 and 21 are as shown in Fig. 4C. Ag wirings (conductive wirings) 15 electrically connected to each other can be formed.

또한, 상기 분산매로서는, 은 미립자를 분산할 수 있는 것으로, 응집을 일으키지 않는 것이면 특별히 한정되지 않는다. 예를 들어 물 이외에, 메탄올, 에탄올, 프로판올, 부탄올 등의 알코올류, n-헵탄, n-옥탄, 데칸, 도데칸, 테트라데칸, 톨루엔, 크실렌, 시멘, 듀렌, 인덴, 디펜텐, 테트라히드로나프탈렌, 데카히드로나프탈렌, 시클로헥실벤젠 등의 탄화수소계 화합물, 또한 에틸렌글리콜디메틸에테르, 에틸렌글리콜디에틸에테르, 에틸렌글리콜메틸에틸에테르, 디에틸렌글리콜디메틸에테르, 디에틸렌글리콜디에틸에테르, 디에틸렌글리콜메틸에틸에테르, 1,2-디메톡시에탄, 비스(2-메톡시에틸)에테르, p-디옥산 등의 에테르계 화합물, 또한 프로필렌카보네이트, γ-부티로락톤, N-메틸-2-피롤리돈, 디메틸포름아미드, 디메틸술폭시드, 시클로헥사논 등의 극성 화합물을 예시할 수 있다. 이들 중, 미립자의 분산성과 분산액의 안정성, 또한 액적 토출법(잉크젯법)으로의 적용의 용이성의 점에서, 물, 알코올류, 탄화수소계 화합물, 에테르계 화합물이 바람직하고, 더 바람직한 분산매로서는, 물, 탄화수소계 화합물을 들 수 있다. 또한, 분산액의 점도는 예를 들어 1m㎩·s 이상 50m㎩·s 이하인 것이 바람직하다. 잉크젯법을 이용하여 액체 재료를 액적으로서 토출할 때, 점도가 1m㎩·s보다 작은 경우에는 노즐 주위가 잉크의 유출에 의해 오염되기 쉽고, 또한 점도가 50m㎩·s보다 큰 경우에는 노즐 구멍에서의 막힘 빈도가 높아져 원활한 액적의 토출이 곤란해지기 때문이다.Moreover, as said dispersion medium, silver microparticles | fine-particles can be disperse | distributed and it will not specifically limit, if it does not cause aggregation. For example, in addition to water, alcohols such as methanol, ethanol, propanol, butanol, n-heptane, n-octane, decane, dodecane, tetradecane, toluene, xylene, cymene, durene, indene, dipentene, tetrahydronaphthalene Hydrocarbon compounds such as decahydronaphthalene, cyclohexylbenzene, ethylene glycol dimethyl ether, ethylene glycol diethyl ether, ethylene glycol methyl ethyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol methylethyl Ether compounds such as ether, 1,2-dimethoxyethane, bis (2-methoxyethyl) ether, p-dioxane, propylene carbonate, γ-butyrolactone, N-methyl-2-pyrrolidone, Polar compounds, such as dimethylformamide, dimethyl sulfoxide, and cyclohexanone, can be illustrated. Among them, water, alcohols, hydrocarbon-based compounds and ether-based compounds are preferred from the viewpoint of dispersibility of the fine particles, stability of the dispersion liquid, and ease of application to the droplet ejection method (ink jet method). And hydrocarbon compounds. In addition, it is preferable that the viscosity of a dispersion liquid is 1 mPa * s or more and 50 mPa * s or less, for example. When the liquid material is discharged as droplets using the inkjet method, when the viscosity is less than 1 mPa · s, the area around the nozzle is likely to be contaminated by the outflow of ink, and when the viscosity is larger than 50 mPa · s, This is because the clogging frequency increases, making it difficult to discharge the droplets smoothly.

또한, 표면장력을 조정하기 위해, 상기 분산액에는, 기판과의 접촉각을 크게 저하시키지 않는 범위에서, 불소계, 실리콘계, 노니온계 등의 표면장력 조절제를 미량 첨가하면 된다. 노니온계 표면장력 조절제는 액체의 기판으로의 젖음성을 향상시키고, 막의 레벨링성을 개량하여, 막의 미세한 요철의 발생 등의 방지에 도움이 되는 것이다. 상기 표면장력 조절제는 필요에 따라, 알코올, 에테르, 에스테르, 케톤 등의 유기 화합물을 포함할 수도 있다.In addition, in order to adjust surface tension, a small amount of surface tension regulators, such as a fluorine type, a silicone type, and a nonionic type, may be added to the said dispersion liquid in the range which does not reduce the contact angle with a board | substrate significantly. The nonionic surface tension modifier improves the wettability of the liquid to the substrate, improves the leveling property of the film, and helps to prevent the occurrence of minute unevenness of the film. The surface tension modifier may include organic compounds such as alcohols, ethers, esters, ketones and the like as necessary.

이상의 공정에 의해 전자 부품(20, 21)이 절연막(13)에 매설된 배선 기판(100)이 제조된다.By the above process, the wiring board 100 in which the electronic components 20 and 21 were embedded in the insulating film 13 is manufactured.

다음으로, 도 4의 (d)에 나타낸 바와 같이, 상기 배선 기판(100) 상에 제 1 층간 절연막(60)을 형성한다. 그리고, 상기 제 1 층간 절연막(60) 상에 스루홀(through-hole)(H1)을 통하여 배선(15) 및 칩 부품(20)에 접속되는 제 1 상층 배선(61)을 형성하는 동시에, 상술한 접착재(C)를 후술하는 IC칩(70)과 거의 동일한 크기로 도포한다. 본 실시예에서는, 접착재(C)로서는, 절연막(60)(및 후술하는 절연막(62, 64))과 동일한 재료가 도포된다.Next, as shown in FIG. 4D, a first interlayer insulating film 60 is formed on the wiring board 100. The first upper layer wiring 61 connected to the wiring 15 and the chip component 20 through the through-hole H1 is formed on the first interlayer insulating film 60, and is described above. One adhesive material (C) is applied to substantially the same size as the IC chip 70 described later. In this embodiment, as the adhesive material C, the same material as the insulating film 60 (and insulating films 62 and 64 to be described later) is coated.

이들 제 1 층간 절연막(60), 스루홀(H1), 제 1 상층 배선(61) 및 접착재(C)는 모두 액적 토출 방식을 이용하여 형성된다.These first interlayer insulating films 60, through holes H1, the first upper layer wirings 61, and the adhesive material C are all formed by using a droplet discharging method.

그리고, 접착재(C)에 대해서는, 제 1 층간 절연막(60) 상에 도포한 후에, 자외광을 조사하여 반경화 상태로 한다.And about the adhesive material C, after apply | coating on the 1st interlayer insulation film 60, ultraviolet light is irradiated and it is set as a semi-hardened state.

이 후, 도 5의 (a)에 나타낸 바와 같이, 외부 접속용의 단자(72)를 갖는 IC칩(전자 부품)(70)을 접착재(C) 상에 탑재하고, 가열함으로써, 접착재(C)를 경화시켜 IC칩(70)을 고정한다.Subsequently, as shown in Fig. 5A, the IC chip (electronic component) 70 having the terminal 72 for external connection is mounted on the adhesive material C and heated, thereby adhering the adhesive material C to it. The IC chip 70 is fixed by hardening.

이어서, 도 5의 (b)에 나타낸 바와 같이, 상기 제 1 층간 절연막(60) 상에 IC칩(70) 및 배선(61)을 덮도록, 절연성 잉크를 액적 토출 방식으로 도포하고, 경화시킴으로써 제 2 층간 절연막(절연막)(62)을 형성한다. 또한, 이 절연성 잉크의 도포는 배선(15)에 접속되는 스루홀(H2) 및 배선(61)에 접속되는 스루홀(H3)을 둘러싸도록 형성된다.Subsequently, as shown in FIG. 5B, the insulating ink is applied by a droplet ejection method and cured so as to cover the IC chip 70 and the wiring 61 on the first interlayer insulating film 60. A two interlayer insulating film (insulating film) 62 is formed. The application of the insulating ink is formed so as to surround the through hole H2 connected to the wiring 15 and the through hole H3 connected to the wiring 61.

이에 따라, 제 2 층간 절연막(62) 내에 IC칩(70)을 매립할 수 있다.As a result, the IC chip 70 can be embedded in the second interlayer insulating film 62.

그리고, 상기 스루홀(H2, H3)을 액적 토출 방식에 의해 배선(15, 61)과 동일한 재료를 도포하여 형성하는 동시에, 상기 제 2 층간 절연막(62) 상에 상기 단자(72)에 접속하는 제 2 상층 배선(63)을 액적 토출 방식에 의해 형성한다. 이 때, 배선(63)은 IC칩(70)의 단자(72)와 스루홀(H2, H3)에 각각 접속된다.The through holes H2 and H3 are formed by applying the same material as that of the wirings 15 and 61 by the droplet ejection method, and are connected to the terminal 72 on the second interlayer insulating film 62. The second upper layer wiring 63 is formed by the droplet discharging method. At this time, the wiring 63 is connected to the terminal 72 and the through holes H2 and H3 of the IC chip 70, respectively.

또한, 이 제 2 상층 배선(63)은 스루홀(H3)을 통하여 제 1 상층 배선(61), 또는 스루홀(H2)을 통하여 Ag 배선(15)에 도통된다. 따라서, IC칩(70)과 제 2 상층 배선(63)은 단자(72)를 통하여 양호하게 도통된 것으로 되어 있다.In addition, the second upper wiring 63 is electrically connected to the Ag wiring 15 through the first upper wiring 61 or the through hole H2 through the through hole H3. Therefore, the IC chip 70 and the second upper layer wiring 63 are well conducted through the terminal 72.

그리고, 도 5의 (c)에 나타낸 바와 같이, 상기 제 2 층간 절연막(62) 상에 제 3 층간 절연막(64)을 형성하고, 상기 제 3 층간 절연막(64) 상에 다른 칩 부품(24, 25)을 스루홀(H4, H5)을 통하여 실장한다. 이들 스루홀(H4, H5)은 상술한 스루홀(H2, H3)과 동일한 재료·순서에 의해 형성된다. 또한, 이들 제 3 층간 절연막(64), 스루홀(H4, H5)도 액적 토출 방식을 이용하여 형성된다.As shown in FIG. 5C, a third interlayer insulating film 64 is formed on the second interlayer insulating film 62, and another chip component 24 is formed on the third interlayer insulating film 64. 25) is mounted through the through holes H4 and H5. These through holes H4 and H5 are formed by the same material and procedure as the through holes H2 and H3 described above. In addition, these third interlayer insulating films 64 and through holes H4 and H5 are also formed using a droplet discharging method.

또한, 칩 부품(24, 25)으로서는, 여기서는 안테나 소자 및 수정(水晶) 진동자를 각각 실장했다.In addition, as the chip components 24 and 25, the antenna element and the crystal oscillator were mounted here, respectively.

이상의 공정에 의해, 다층 배선 기판(500)을 형성할 수 있다.Through the above steps, the multilayer wiring board 500 can be formed.

이와 같이, 본 실시예에서는, 전자 부품(P)이나 IC칩(70)과 거의 동일한 크기로 접착재(C)를 도포한 후에, 이들 전자 부품(P)이나 IC칩(70)을 탑재하기 때문에, 이들 전자 부품과 베이스부(B)(다층 배선 기판(500)에서는 절연막(60)) 사이에 에어가 혼입되는 것을 방지할 수 있다. 따라서, 본 실시예에서는, 가열 시에 에어 가 팽창하여, 경화된 접착재(C)에 크랙이 생기고, 접착 강도가 저하되는 것을 회피하는 것이 가능해진다.Thus, in this embodiment, since the electronic component P and the IC chip 70 are mounted after the adhesive material C is applied to substantially the same size as the electronic component P and the IC chip 70, It is possible to prevent air from mixing between these electronic components and the base portion B (the insulating film 60 in the multilayer wiring board 500). Therefore, in the present Example, it becomes possible to avoid that air expands at the time of heating, a crack occurs in the hardened adhesive material C, and the adhesive strength falls.

또한, 본 실시예에서는, 접착재(C)를 반경화 상태로 한 후에 전자 부품을 탑재하기 때문에, 전자 부품의 접착면의 평탄성이 낮은 경우에도, 밀착성을 향상시킬 수 있고, 안정적으로 전자 부품을 탑재·고정하는 것이 가능해진다.In addition, in this embodiment, since the electronic component is mounted after the adhesive material C is semi-cured, the adhesiveness can be improved even when the flatness of the adhesive surface of the electronic component is low, and the electronic component can be stably mounted. · It becomes possible to fix it.

특히, 본 실시예에서는, 광에너지의 부여에 의해 접착재(C)를 반경화 상태로 하고 있기 때문에, 반경화 처리가 용이함과 동시에, 예를 들어 마스크 등을 사용함으로써, 용이하게 자외광의 조사 범위를 규정하는 것이 가능해진다.In particular, in the present embodiment, since the adhesive material (C) is in a semi-cured state by applying light energy, the semi-curing treatment is easy and, for example, by using a mask or the like, the irradiation range of ultraviolet light can be easily It becomes possible to define.

또한, 본 실시예에서는, 접착재(C)로서 절연막(60, 62, 64)과 동일한 재료를 사용하고 있기 때문에, 별도 접착재(C)용의 재료를 준비할 필요가 없어지고, 생산성의 향상에 기여할 수 있다. 또한, 본 실시예에서는, 배선 기판(100) 및 다층 배선 기판(500)의 제조 공정을 모두 액적 토출 방식으로 행하는 것이 가능하고, 생산성의 대폭적인 향상을 도모할 수 있다.In addition, in this embodiment, since the same material as the insulating films 60, 62, and 64 is used as the adhesive material C, there is no need to prepare a material for the adhesive material C separately, which contributes to the improvement in productivity. Can be. In addition, in this embodiment, it is possible to perform both the manufacturing process of the wiring board 100 and the multilayer wiring board 500 by the droplet discharge system, and the productivity can be improved significantly.

또한, 본 실시예에서는, 액적 토출 방식에 의해 상기 접착재를 포함하는 액적을 도포하기 때문에, 인쇄법이나 포토리소그래피법 등과 같이, 마스크나 레지스트 등을 사용하지 않고, 용이하게 접착재를 패터닝할 수 있으며, 또한 소비되는 접착재에 낭비가 생기지 않기 때문에, 비용 저감에도 기여할 수 있다.Further, in the present embodiment, since the droplet containing the adhesive is coated by the droplet ejecting method, the adhesive can be easily patterned without using a mask, a resist, or the like, such as a printing method or a photolithography method. Moreover, since waste does not generate | occur | produce in the adhesive material consumed, it can contribute to cost reduction.

이상, 첨부 도면을 참조하면서 본 발명에 따른 적절한 실시예에 대해서 설명했지만, 본 발명은 이러한 예에 한정되지 않는다. 상술한 예에서 나타낸 각 구성 부재의 다양한 형상이나 조합 등은 일례로서, 본 발명의 주지(主旨)로부터 일탈하 지 않는 범위에서 설계 요구 등에 의거하여 다양하게 변경 가능하다.As mentioned above, although the preferred embodiment which concerns on this invention was described referring an accompanying drawing, this invention is not limited to this example. The various shapes, combinations, etc. of each structural member shown by the above-mentioned example are an example, and can be variously changed according to a design request etc. in the range which does not deviate from the main point of this invention.

예를 들어 반경화 상태의 접착재(C)에 열에너지를 부여하여 경화시키는 순서로 했지만, 이것에 한정되지 않고, 베이스부(B)나 전자 부품(P)이 자외광을 투과할 경우에는, 광에너지를 부여하여 경화시키는 순서로 할 수도 있다.For example, although the heat energy was applied to the adhesive material C in the semi-cured state and hardened, the present invention is not limited thereto. When the base part B or the electronic component P transmits ultraviolet light, the light energy is used. It can also be set in order to provide and harden | cure.

또한, 상기 실시예에서는, 반경화 상태의 접착재(C)에 전자 부품을 탑재한 후에, 즉시 경화 처리를 실시하는 순서로 했지만, 예를 들어 다층 배선 기판(500)을 형성할 경우에는, 반경화 상태에서 접착재나 절연막, 도전 배선을 형성하고, 그 후, 가열 처리를 실시하여, 일괄적으로 경화시키는 순서로 할 수도 있다.In addition, in the said Example, although the order of hardening process was performed immediately after mounting an electronic component in the adhesive material C of a semi-hardened state, when forming the multilayer wiring board 500, for example, it semi-hardens. It is also possible to form an adhesive material, an insulating film, and conductive wirings in a state, and then heat treatment and cure them collectively.

또한, 상기 실시예에서는, 접착재(C)로서, 절연막(60, 62, 64)과 동일한 재료를 사용하는 순서로 했지만, 예를 들어 전자 부품의 접착면에 전극이나 단자 등의 도전 접속부가 배치되지 않을 경우에는, 절연막 이외에도, 배선(15, 61, 63)과 동일한 도전성 재료를 사용하는 순서로 할 수도 있다.In the above embodiment, the same materials as the insulating films 60, 62, and 64 are used as the adhesive material C. However, for example, conductive connections such as electrodes and terminals are not disposed on the adhesive surface of the electronic component. If not, the same conductive material as that of the wirings 15, 61, and 63 may be used in addition to the insulating film.

또한, 상기 실시예에서는, IC칩(72)을 탑재할 때에 본 발명을 적용하는 순서로 했지만, 이것에 한정되지 않고, 칩 부품(20, 21)이나 칩 부품(24, 25)을 실장하기 전에 접착재를 도포·반경화시키고, 그 후에 이들 칩 부품을 실장하는 순서로 할 수도 있다.In the above embodiment, the present invention is applied in the order of mounting the IC chip 72. However, the present invention is not limited thereto, but before the chip parts 20 and 21 and the chip parts 24 and 25 are mounted. It can also be set as the order which apply | coats and semi-cures an adhesive material, and mounts these chip components after that.

도 1은 전자 기판의 제조에 사용하는 액적 토출 장치의 모식도.BRIEF DESCRIPTION OF THE DRAWINGS The schematic diagram of the droplet ejection apparatus used for manufacture of an electronic board | substrate.

도 2의 (a) 및 (b)는 액적 토출 장치에서의 헤드의 모식도.2 (a) and 2 (b) are schematic diagrams of a head in the droplet ejection apparatus.

도 3은 본 발명에 따른 전자 기판의 제조 방법을 나타내는 공정도.3 is a process chart showing the manufacturing method of the electronic substrate according to the present invention;

도 4는 다층 배선 기판을 제조하는 순서를 나타내는 도면.4 is a diagram illustrating a procedure of manufacturing a multilayer wiring board.

도 5는 다층 배선 기판을 제조하는 순서를 나타내는 도면.5 is a diagram illustrating a procedure of manufacturing a multilayer wiring board.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

1: 액적 토출 장치 15: Ag 배선(도전 배선)1: droplet ejection apparatus 15: Ag wiring (conductive wiring)

70: IC칩(전자 부품) 103: 토출 헤드부(액적 토출 헤드)70: IC chip (electronic component) 103: discharge head portion (droplet discharge head)

B: 베이스부 C: 접착재B: Base C: Adhesive

P: 전자 부품P: electronic components

Claims (8)

전자 부품이 접착재(材)를 통하여 베이스부에 접착되어 이루어지는 전자 기판의 제조 방법으로서,As a manufacturing method of an electronic substrate in which an electronic component is adhere | attached to a base part through an adhesive material, 상기 베이스부와 상대 이동하는 액적(液滴) 토출 헤드를 사용하여, 상기 접착재를 포함하는 액적을 상기 베이스부의 상기 전자 부품과 대향하는 영역에 상기 전자 부품과 거의 동일한 크기로 도포하는 도포 공정과,An application step of applying a droplet including the adhesive material to a region facing the electronic component of the base portion in substantially the same size as the electronic component, using a liquid droplet discharge head relatively moving with the base portion; 상기 베이스부에 도포된 상기 접착재 위에 상기 전자 부품을 탑재하는 탑재 공정을 갖는 것을 특징으로 하는 전자 기판의 제조 방법.And a mounting step of mounting the electronic component on the adhesive material applied to the base portion. 제 1 항에 있어서,The method of claim 1, 도포한 상기 접착재를, 상기 탑재 공정의 전에 반(半)경화 상태로 하는 반경화 공정을 갖는 것을 특징으로 하는 전자 기판의 제조 방법.It has a semi-hardening process which makes the apply | coated adhesive material apply | coat a semi-hardened state before the mounting process, The manufacturing method of the electronic substrate characterized by the above-mentioned. 제 2 항에 있어서,The method of claim 2, 상기 반경화 공정에서는, 상기 접착재를 포함하는 액적이 경화되는 에너지량보다도 작은 에너지량을 부여하고,In the said semi-hardening process, the energy amount smaller than the energy amount hardened | cured by the droplet containing the said adhesive material is given, 상기 탑재 공정 후에 상기 접착재를 포함하는 액적이 경화되는 에너지량을 부여하는 것을 특징으로 하는 전자 기판의 제조 방법.A method of manufacturing an electronic substrate, wherein the amount of energy that the droplet containing the adhesive is cured after the mounting step is imparted. 제 3 항에 있어서,The method of claim 3, wherein 상기 접착재를 포함하는 액적에 광에너지와 열에너지 중 적어도 한쪽을 부여하는 것을 특징으로 하는 전자 기판의 제조 방법.And at least one of light energy and thermal energy is applied to the droplet containing the adhesive. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 베이스부는 절연재로 형성되고,The base portion is formed of an insulating material, 상기 접착재는 상기 절연재인 것을 특징으로 하는 전자 기판의 제조 방법.And said adhesive material is said insulating material. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 전자 부품에 전기적으로 접속되는 도전 배선을 갖고,It has a conductive wiring electrically connected to the said electronic component, 상기 접착재는 상기 도전 배선을 형성하는 재료를 포함하는 것을 특징으로 하는 전자 기판의 제조 방법.The adhesive material includes a material for forming the conductive wiring. 제 6 항에 있어서,The method of claim 6, 상기 도전 배선은 절연층을 통하여 복수 적층하여 설치되는 것을 특징으로 하는 전자 기판의 제조 방법.And a plurality of the conductive wires are laminated through an insulating layer. 제 7 항에 있어서,The method of claim 7, wherein 상기 도전 배선 및 상기 절연층을, 상기 액적 토출 헤드를 사용하여 성막(成膜)하는 것을 특징으로 하는 전자 기판의 제조 방법.A method of manufacturing an electronic substrate, wherein the conductive wiring and the insulating layer are formed by using the droplet discharge head.
KR1020070111894A 2006-11-07 2007-11-05 Method for manufacturing electronic substrate KR20080041572A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006301234A JP2008117997A (en) 2006-11-07 2006-11-07 Method of manufacturing electronic substrate
JPJP-P-2006-00301234 2006-11-07

Publications (1)

Publication Number Publication Date
KR20080041572A true KR20080041572A (en) 2008-05-13

Family

ID=39358445

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070111894A KR20080041572A (en) 2006-11-07 2007-11-05 Method for manufacturing electronic substrate

Country Status (3)

Country Link
US (1) US7793411B2 (en)
JP (1) JP2008117997A (en)
KR (1) KR20080041572A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160012974A (en) * 2013-11-19 2016-02-03 세키스이가가쿠 고교가부시키가이샤 Method for manufacturing electronic component, and electronic component

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2421339A1 (en) * 2010-08-18 2012-02-22 Dyconex AG Method for embedding electrical components
JP5433628B2 (en) * 2011-05-12 2014-03-05 東芝テック株式会社 Circuit board and inkjet head manufacturing method
KR102000302B1 (en) * 2011-05-27 2019-07-15 엠씨10, 인크 Electronic, optical and/or mechanical apparatus and systems and methods for fabricating same
JP2014220372A (en) * 2013-05-08 2014-11-20 積水化学工業株式会社 Method of manufacturing semiconductor device
US9801277B1 (en) * 2013-08-27 2017-10-24 Flextronics Ap, Llc Bellows interconnect
CN106103633B (en) * 2014-11-17 2023-11-17 积水化学工业株式会社 Photo-and thermosetting adhesive for ink jet, method for manufacturing semiconductor device, and electronic component
US10449729B1 (en) 2015-12-03 2019-10-22 Multek Technologies Ltd. 3D printed fiber optics
EP3471135A4 (en) * 2016-06-08 2019-05-01 Fuji Corporation Method for forming circuit
DE102019202245A1 (en) * 2019-02-19 2020-08-20 Ekra Automatisierungssysteme Gmbh Printing facility and procedure

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0369191A (en) 1989-08-08 1991-03-25 Nec Corp Multi-layer printed-circuit board with built-in electronic parts
US5136365A (en) * 1990-09-27 1992-08-04 Motorola, Inc. Anisotropic conductive adhesive and encapsulant material
US6171468B1 (en) * 1993-05-17 2001-01-09 Electrochemicals Inc. Direct metallization process
US5637920A (en) * 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips
CA2306384A1 (en) * 1997-10-14 1999-04-22 Patterning Technologies Limited Method of forming an electronic device
US20030108664A1 (en) * 2001-10-05 2003-06-12 Kodas Toivo T. Methods and compositions for the formation of recessed electrical features on a substrate
JP2006259657A (en) * 2004-06-11 2006-09-28 Seiko Epson Corp Electro-optical device, method of manufacturing the same, and electronic apparatus using electro-optical device
US7687326B2 (en) * 2004-12-17 2010-03-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP2006332094A (en) * 2005-05-23 2006-12-07 Seiko Epson Corp Process for producing electronic substrate, process for manufacturing semiconductor device and process for manufacturing electronic apparatus
KR100643934B1 (en) * 2005-09-02 2006-11-10 삼성전기주식회사 Method of forming circuit pattern of pcb

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160012974A (en) * 2013-11-19 2016-02-03 세키스이가가쿠 고교가부시키가이샤 Method for manufacturing electronic component, and electronic component

Also Published As

Publication number Publication date
US7793411B2 (en) 2010-09-14
US20080104832A1 (en) 2008-05-08
JP2008117997A (en) 2008-05-22

Similar Documents

Publication Publication Date Title
KR20080041572A (en) Method for manufacturing electronic substrate
KR100788445B1 (en) Electronic substrate manufacturing method, semiconductor device manufacturing method, and electronic equipment manufacturing method
KR100723998B1 (en) Forming method of multi-layer structure, manufacturing method of wiring substrate and manufacturing method of electronic apparatus
US7972651B2 (en) Method for forming multi-layered structure, method for manufacturing wiring substrate, and method for manufacturing electronic apparatus
KR100668273B1 (en) Method of forming multi-layer structure, and method of manufacturing wiring substrate and electronic equipment
KR100714820B1 (en) Method of forming wiring pattern, wiring pattern and electronic equipment
JP4207917B2 (en) Manufacturing method of multilayer substrate
KR100769636B1 (en) Multilayered structure forming method
KR100770286B1 (en) Method of manufacturing a wiring substrate
JP4506809B2 (en) MULTILAYER STRUCTURE FORMING METHOD, WIRING BOARD AND ELECTRONIC DEVICE MANUFACTURING METHOD
JP4211842B2 (en) Method for manufacturing electronic substrate and method for manufacturing multilayer wiring substrate
JP4888073B2 (en) Manufacturing method of electronic substrate
JP2006073561A (en) Circuit board
JP2008124106A (en) Manufacturing method of multilayer wiring board
JP2008258376A (en) Method and device for manufacturing circuit element mounting module, and circuit element mounting module
JP2008124294A (en) Electronic substrate, and manufacturing method thereof
JP4888072B2 (en) Manufacturing method of electronic substrate
JP2005327985A (en) Inter-electrode connecting structure and method, and electronic apparatus

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application