KR20080039004A - Liquid crystal display panel of horizontal electronic fileld applying type and method of fabricating the same - Google Patents

Abstract

An in-field application type liquid crystal display panel, and its fabrication method are provided to prevent degradation of picture quality caused by non-uniformity of a cell gap. A TFT(Thin Film Transistor) array substrate is attached with a color filter array substrate with liquid crystal interposed therebetween. A gate line(102) and a data line(104) are formed to cross each other on the TFT array substrate. A TFT(106) is formed at a crossing of the gate line and the data line. A pixel electrode(114) is connected with the TFT. A common electrode(118) are formed to be parallel with the pixel electrode and form an in-plane field together with the pixel electrode. A common line(116) is formed to be parallel to the gate line on the same plane as that of the gate line and supplies a reference voltage to the common electrode. A dummy pattern(210) is positioned between the common line and the gate line.

Description

Liquid Crystal Display Panel Of Horizontal Electronic Fileld Applying Type and Method of Fabricating the same}

1 is a plan view illustrating a thin film transistor array substrate of a conventional horizontal field application liquid crystal display panel.

FIG. 2A is a cross-sectional view illustrating a portion of a liquid crystal display panel including a thin film transistor array substrate and a color filter array substrate taken along line II ′ in FIG. 1.

FIG. 2B is a cross-sectional view illustrating a portion of a liquid crystal display panel including a thin film transistor array substrate and a color filter array substrate taken along line II-II ′ in FIG. 1.

3 shows cell gap non-uniformity as the ball spacers are positioned abnormally.

4 is a plan view illustrating a thin film transistor array substrate of a horizontal field applied liquid crystal display panel according to the present invention;

FIG. 5A is a cross-sectional view illustrating a portion of a liquid crystal display panel including a thin film transistor array substrate and a color filter array substrate taken along line III-III ′ in FIG. 1.

FIG. 5B is a cross-sectional view illustrating a portion of a liquid crystal display panel including a thin film transistor array substrate and a color filter array substrate taken along line VI-VI ′ in FIG. 1.

6A to 6E illustrate a method of manufacturing the thin film transistor array substrate illustrated in FIGS. 5A and 5B.

7A and 7B specifically illustrate the second mask process of FIG. 6B.

         <Explanation of symbols for the main parts of the drawings>

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10 source electrode 12, 112 drain electrode

14, 114: pixel electrodes 16, 116: common line

18, 118: common electrode 51, 151: protective film

46,146: gate insulating film 70,170: thin film transistor array substrate

80,180 color filter array substrate

220: photoresist pattern 210: dummy pattern

17,117: first contact hole 27, 127: second contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly, to a horizontal field application type liquid crystal display panel capable of preventing image quality deterioration and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal displays are classified into vertical electric field types and horizontal electric field types according to the direction of the electric field for driving the liquid crystal.

In the vertical field application type liquid crystal display, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate are disposed to face each other to drive the liquid crystal of TN (Twisted Nemastic) mode by a vertical electric field formed therebetween. . Such a vertical field type liquid crystal display device has a large aperture ratio, but has a narrow viewing angle of about 90 degrees.

In a horizontal field application liquid crystal display, an in-plane switch (hereinafter referred to as IPS) mode liquid crystal is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. The horizontal field application liquid crystal display device has an advantage that a viewing angle is wide as about 160 degrees. Hereinafter, a horizontal field application liquid crystal display device will be described in detail.

The horizontal field application type liquid crystal display device includes a thin film transistor array substrate (lower substrate) and a color filter array substrate (upper substrate) bonded to each other, a spacer for maintaining a constant cell gap between the two substrates, and a spacer provided by the spacer. A liquid crystal filled in the liquid crystal space is provided.

The thin film transistor array substrate is composed of a plurality of signal lines and thin film transistors for forming a horizontal electric field in pixels, and an alignment film coated thereon for liquid crystal alignment. The color filter array substrate is composed of a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated thereon for liquid crystal alignment.

1 is a plan view showing only a thin film transistor array substrate of a conventional horizontal field applied liquid crystal display panel, and FIG. 2A is a liquid crystal including a thin film transistor array substrate and a color filter array substrate taken along line I-I 'of FIG. 1. FIG. 2B is a cross-sectional view showing a part of a display panel, and FIG. 2B is a cross-sectional view showing a part of a liquid crystal display panel including a thin film transistor array substrate and a color filter array substrate taken along line II-II 'in FIG. 1.

The liquid crystal display panel 90 illustrated in FIGS. 1, 2A, and 2B includes a thin film transistor array substrate 70 and a color filter array substrate 80 facing each other with the liquid crystal 72 therebetween.

The thin film transistor array substrate 70 includes a thin film transistor formed at each intersection of the gate line 2 and the data line 4 and the gate line 2 and the data line 4 formed on the lower substrate 45. 6, the pixel electrode 14 and the common electrode 18 formed to form a horizontal electric field in the pixel region 5 defined by the gate line 2 and the data line 4, and the common electrodes 18 are connected to each other. Common line 16 is provided.

The gate line 2 supplies a gate signal to the gate electrode 8 of the thin film transistor 6. The data line 4 supplies the pixel signal to the pixel electrode 14 through the drain electrode 12 of the thin film transistor 6. The gate line 2 and the data line 4 are formed in an intersecting structure to define the pixel region 5.

The common line 16 is formed in parallel with the gate line 2 with the pixel region 5 therebetween, and supplies a reference voltage for driving the liquid crystal to the common electrode 18.

The thin film transistor 6 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 14 in response to the gate signal of the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode connected to the pixel electrode 14. 12). In addition, the thin film transistor 6 includes a semiconductor layer including an active layer 48 overlapping with the gate electrode 8 and the gate insulating layer 46 therebetween to form a channel between the source electrode 10 and the drain electrode 12. The pattern 49 is further provided. The semiconductor pattern 49 further includes an ohmic contact layer 50 positioned on the active layer 48 to make ohmic contact with the data line 4, the source electrode 10, and the drain electrode 12.

The pixel electrode 14 is connected to the drain electrode 12 of the thin film transistor 6 through the first contact hole 17 and is formed in the pixel region 5. Here, the pixel electrode 14 is connected to the drain electrode 12 and formed in parallel with the adjacent gate line 2 (14a) (hereinafter, the horizontal portion of the pixel electrode is referred to as the "first horizontal portion"), A finger portion 14b connected to the first horizontal portion 14a of the pixel electrode 14 and parallel to the finger portion 18b of the common electrode 18 (hereinafter, the finger portion of the common electrode is referred to as a “second finger portion”). (Hereinafter, the finger portion of the pixel electrode is referred to as a "first finger portion").

The common electrode 18 is connected to the common line 16 to be formed of the same metal as the gate line 2 and the gate electrode 8 in the pixel region 5. In particular, the common electrode 18 contacts the common line 16 through the second contact hole 27 through the gate insulating layer 46 and the passivation layer 51 to expose the common line 16. ) And a horizontal portion 18a (hereinafter referred to as a horizontal portion of the common electrode is referred to as a "second horizontal portion") and a second finger portion of the pixel electrode 14 extending from the second horizontal portion 18a. A second finger portion 18b parallel to 14b is provided.

The color filter array substrate 80 includes a black matrix 56 partitioning each pixel region 5, a color filter 58 formed in the pixel region 5 partitioned by the black matrix 56, and a color filter ( An overcoat layer 59 formed to cover 58).

The black matrix 56 overlaps the thin film transistor 6, the gate line 2, the data line 4, and the common line 16 of the lower substrate 55 to prevent light leakage and absorb external light. To increase the contrast. The color filter 58 is formed for each of R, G, and B in the pixel area partitioned by the black matrix 56 to implement R, G, and B colors. The overcoat layer 59 is formed to cover the color filter 58 to planarize the upper substrate 55. The ball spacer 62 is positioned in an area overlapping the gate line 2 or the common line 16 to maintain a cell gap between the color filter array substrate 80 and the thin film transistor array substrate 70.

In addition, upper and lower alignment layers 61 and 53 for liquid crystal alignment are disposed on the color filter array substrate 80 and the thin film transistor array substrate 70, respectively. The upper and lower alignment layers 61 and 53 are formed as a rubbing process is performed after an alignment material such as polyimide is applied.

Meanwhile, the conventional ball spacer 62 is coated on the thin film transistor array substrate by an inkjet method. Here, the ball spacer 62 is positioned in an area overlapping the gate line 2 or the common line 16. However, the ball spacer 62 does not overlap with the gate line 2 or the common line 16 due to variations in the process applied by the fluidity and the inkjet method of the ball spacer 62 so that uniformity of the cell gap is achieved. The problem of deterioration occurs.

Referring to FIG. 3, the distance d1 between the gate line 2 and the common line 16 is about 12 μm, and the diameter d2 of the ball spacer 62 is about 2.5 μm to 4 μm. . As a result, the ball spacer 62 frequently slides into the recessed region between the gate line 2 and the common line 16 due to a small impact, process variation, or the like. When the ball spacer 62 is positioned in the recessed region between the gate line 2 and the common line 16, the cell gap around the ball spacer 62 becomes relatively small, resulting in uneven cell gap and color filter. The array substrate 80 is also partially curved. As a result, the transmittance becomes uneven and a luminance difference occurs, resulting in a problem of deterioration in image quality such as unevenness in an image.

Accordingly, it is an object of the present invention to provide a horizontal field application type liquid crystal display panel and a method of manufacturing the same that can prevent deterioration of image quality.

In order to achieve the above object, a horizontal field application type liquid crystal display panel according to an embodiment of the present invention includes a color filter array substrate; A thin film transistor array substrate bonded to the color filter array substrate with a liquid crystal interposed therebetween, the thin film transistor array substrate having a gate line and a data line formed to cross each other on a substrate; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the thin film transistor; A common electrode formed in parallel with the pixel electrode to form a horizontal electric field with the pixel electrode; A common line formed parallel to the gate line on the same plane as the gate line and supplying a reference voltage to the common electrode; And a dummy pattern positioned between the common line and the gate line.

And a ball spacer for maintaining a gap between the color filter array substrate and the thin film transistor array substrate, wherein the ball spacer overlaps at least one of the gate line, the common line, and the dummy pattern.

The thin film transistor may include a gate electrode connected to the gate line; A source electrode connected to the data line; A drain electrode facing the source electrode; An active layer is formed between the source electrode and the drain electrode.

The dummy pattern is characterized in that the same material as the active layer.

The dummy pattern may have the same thickness as the gate line and the common line.

The dummy pattern may be in the form of a line.

The thin film transistor array substrate may further include a gate insulating layer formed on the substrate to cover the gate line and the common line, and the dummy pattern may be formed on the gate insulating layer between the gate line and the common line.

According to another aspect of the present invention, there is provided a method of manufacturing a horizontal field applied liquid crystal display panel, including forming a color filter array substrate; Forming a thin film transistor array substrate; Bonding the color filter array substrate and the color filter array substrate to each other with a liquid crystal interposed therebetween, wherein the forming of the thin film transistor array substrate comprises forming the thin film transistor array substrate on the substrate; Forming a gate pattern including a gate line and a common line parallel to the gate line; Forming a gate insulating film to cover the gate pattern; A source / drain pattern including a data line crossing the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and a channel between the source electrode and the drain electrode on the gate insulating layer; Forming a dummy pattern positioned between the active layer and the gate line and the common line; Forming a passivation layer having a first contact hole exposing the drain electrode and a second contact hole exposing the common line; And a pixel electrode contacting the drain electrode through the first contact hole, and a common electrode contacting the common line through the second contact hole.

The method may further include forming a ball spacer on the thin film transistor array substrate, wherein the ball spacer overlaps at least one of the gate line, the common line, and the dummy pattern.

The forming of the source / drain pattern, the active layer, and the dummy pattern may include sequentially forming a first semiconductor layer, a second semiconductor layer, and a first metal layer on the substrate on which the gate insulating layer is formed; Forming a photoresist pattern in which a region in which the dummy pattern and the channel are to be formed has a relatively lower height than a region in which the source electrode and the drain pattern are to be formed by a photolithography process using a transflective mask; Removing the first semiconductor layer, the second semiconductor layer, and the first metal layer that are not overlapped with the photoresist pattern; Partially removing the photoresist pattern by an ashing process to expose the first metal layer only to the channel region and the region where the dummy pattern is to be formed; Removing the exposed first metal layer to form a source / drain pattern including a data line, a source electrode and a drain electrode and exposing a second semiconductor layer; Removing the remaining photoresist pattern; And removing the second semiconductor layer that is not overlapped with the source / drain pattern to expose the first semiconductor layer including the channel region and to form the dummy pattern.

The thickness of the first semiconductor layer is characterized by having the same height as the height of the gate pattern.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 7B.

4 is a plan view illustrating only a thin film transistor array substrate of a horizontal field applied liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 5A illustrates a thin film transistor array substrate and a color filter array taken along line III-III ′ of FIG. 4. FIG. 5B is a cross-sectional view illustrating a portion of a liquid crystal display panel including a substrate, and FIG. 5B is a cross-sectional view illustrating a portion of a liquid crystal display panel including a thin film transistor array substrate and a color filter array substrate taken along line VI-VI ′ in FIG. 4.

4, 5A, and 5B, the liquid crystal display panel 190 includes a thin film transistor array substrate 170 and a color filter array substrate 180 facing each other with the liquid crystal 172 therebetween.

The color filter array substrate 180 includes a black matrix 156 partitioning each pixel region 105, a color filter 158 formed in the pixel region 105 partitioned by the black matrix 156, and a color filter ( And an overcoat layer 159 formed to cover 158.

The black matrix 156 overlaps the thin film transistor 106, the gate line 102, the data line 104, and the common line 116 of the lower substrate 145 to prevent light leakage and absorb external light. To increase the contrast. The color filter 158 is formed for each of R, G, and B in the pixel area partitioned by the black matrix 156 to implement R, G, and B colors. The overcoat layer 159 is formed to cover the color filter 158 to planarize the upper substrate 155.

The thin film transistor array substrate 170 may include a thin film transistor formed at each intersection of the gate line 102 and the data line 104 and the gate line 102 and the data line 104 formed on the lower substrate 145. 106, the pixel electrode 114 and the common electrode 118 formed to form a horizontal electric field in the pixel region 105 defined by the gate line 102 and the data line 104, and the common electrodes 118 are connected to each other. And a dummy pattern 210 formed between the common line 116 and the gate line 102 and formed on the gate insulating layer 146.

The gate line 102 supplies a gate signal to the gate electrode 108 of the thin film transistor 106. The data line 104 supplies a pixel signal to the pixel electrode 114 through the drain electrode 112 of the thin film transistor 106. The gate line 102 and the data line 104 are formed in an intersecting structure to define the pixel region 105.

The common line 116 is formed in parallel with the gate line 102 with the pixel region 105 interposed therebetween, and supplies a reference voltage for driving the liquid crystal to the common electrode 118.

The thin film transistor 106 keeps the pixel signal of the data line 104 charged and held in the pixel electrode 114 in response to the gate signal of the gate line 102. To this end, the thin film transistor 106 may include a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a drain electrode connected to the pixel electrode 114. 112). In addition, the thin film transistor 106 includes a semiconductor including an active layer 148 overlapping with the gate electrode 108 and the gate insulating layer 146 therebetween to form a channel between the source electrode 110 and the drain electrode 112. The pattern 149 is further provided. The semiconductor pattern 149 further includes an ohmic contact layer 150 positioned on the active layer 148 and for ohmic contact with the data line 104, the source electrode 110, and the drain electrode 112.

The pixel electrode 114 is connected to the drain electrode 112 of the thin film transistor 106 through the first contact hole 117 and is formed in the pixel region 105. Here, the pixel electrode 114 is connected to the drain electrode 112 and is connected to the first horizontal portion 114a formed in parallel with the adjacent gate line 102 and the first horizontal portion 114a of the pixel electrode 114 is connected. It is divided into a first finger portion 114b parallel to the second finger portion 118b of the common electrode 118.

The common electrode 118 is connected to the common line 116 and is formed of the same metal as the gate line 102 and the gate electrode 108 in the pixel region 105. In particular, the common electrode 118 contacts the common line 116 through the second contact hole 127 through the gate insulating layer 146 and the passivation layer 151 to expose the common line 116, and the common line 116. ) Is divided into a second horizontal portion 118a partially overlapping the second horizontal portion 118a and a second finger portion 118b extending from the second horizontal portion 118a and parallel to the first finger portion 114b of the pixel electrode 114. .

The dummy pattern 210 is formed in a line shape on the gate insulating layer 146 positioned between the gate line 102 and the common line 116. The dummy pattern 210 is formed of the same material as the active layer 48 of the semiconductor pattern 49 and has the same height as the thickness of the gate line 102 and the common line 116.

Accordingly, the recessed region, that is, the step difference, formed between the gate line 2 and the common line 16 in FIG. 2B can be eliminated, so that the cell gap holding function by the ball spacer 162 can be normally performed.

That is, even if the position of the ball spacer 162 is changed slightly due to the deviation or external impact in the application process of the ball spacer 162, the stepped or recessed area is removed from the lower part of the ball spacer 162, thereby causing the ball spacer 162 to be removed. The cell gap of the liquid crystal display panel 190 can be maintained normally. Accordingly, it is possible to prevent the deterioration of image quality due to the conventional cell gap nonuniformity.

Upper and lower alignment layers 161 and 153 for liquid crystal alignment are disposed on the color filter array substrate 180 and the thin film transistor array substrate 170, respectively. The upper and lower alignment layers 161 and 153 may be formed as a rubbing process is performed after an alignment material such as polyimide is applied.

The horizontal field application type liquid crystal display panel 190 is disposed between the pixel electrode 114 supplied with the pixel signal through the thin film transistor 106 and the common electrode 118 supplied with the reference voltage through the common line 116. A horizontal electric field is formed. In particular, a horizontal electric field is formed between the first finger portion 114b of the pixel electrode 114 and the second finger portion 118b of the common electrode 118. The liquid crystal 172 molecules arranged in the horizontal direction by the horizontal electric field are rotated by the dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region 105 is changed, thereby realizing an image.

6A to 7B illustrate a method of manufacturing a thin film transistor array substrate according to the present invention.

Referring to FIG. 6A, a gate line 102 and a common line 116 parallel to each other and a gate electrode 108 connected to the gate line 102 are included on the lower substrate 145 as the first mask process is performed. A gate pattern is formed.

After the gate metal layer is deposited on the lower substrate 145 through a deposition method such as sputtering, the gate metal layer is patterned by a photolithography process and an etching process using a first mask, thereby forming the gate electrode 108 and the gate line 102. The gate pattern including the common line 116 is formed. Aluminum neodium (AlNd), aluminum (Al), or the like is used as the gate metal layer.

The gate insulating layer 146 is formed by depositing an inorganic insulating material on the lower substrate 145 on which the gate pattern and the like are deposited by a deposition method such as PECVD. As the material of the gate insulating film 146, silicon nitride (SiNx), silicon oxide (SiOx), or the like, which is an inorganic insulating material, is used.

Referring to FIG. 6B, as the second mask process is performed, the dummy pattern 210 and the semiconductor pattern 149 are formed on the lower substrate 145 on which the gate insulating layer 146 is formed, as well as the data line 104 and the source. A source / drain pattern including the electrode 110 and the drain electrode 112 is formed.

Hereinafter, the second mask process will be described in more detail with reference to FIGS. 7A to 7B.

After the amorphous silicon layer 148a, the n + amorphous silicon layer 150a, and the source / drain metal layer 104a are sequentially deposited on the lower substrate 145 on which the gate insulating layer 146 is formed, a photo using a transflective mask or the like The lithography process is performed to form a photoresist pattern 220 having a step as shown in FIG. 7A. In the photoresist pattern 220, the region where the dummy pattern 210 and the channel are to be formed has a relatively lower height than the region where the source electrode and the drain electrode 110 and 112 are to be formed.

Thereafter, the amorphous silicon layer 148a, the n + amorphous silicon layer 150a, and the source / drain metal layer 104a which are not overlapped with the photoresist pattern 220 are removed by an etching process. Accordingly, the semiconductor pattern 149 including the active layer 148 and the ohmic contact layer 150 is formed, and the source / source including the data line 104, the integrated source electrode 110, and the drain electrode 112 is formed. A drain pattern is formed.

Thereafter, the ashing process is performed to partially remove the photoresist pattern 220 so that the photoresist pattern 220 remains only in an area overlapping with the source and drain electrodes 110 and 112, as shown in FIG. 7B.

Thereafter, the exposed source / drain metal layer is removed using the remaining photoresist pattern 220 as a mask to separate the source electrode 10 and the drain electrode 12 and to expose the ohmic contact layer 150. Thereafter, the strip process is performed to remove the remaining photoresist pattern 220.

Thereafter, a dry etching 150 process using the source and drain electrodes 110 and 112 as a mask is performed to remove the ohmic contact layer 150, thereby exposing the active layer 148. As a result, as shown in FIG. 6B, a dummy pattern 210 positioned between the gate line 102 and the common line 116 is formed. Here, the dummy pattern 210 is made of amorphous silicon and has the same height as the gate pattern.

As the data metal material, chromium (Cr), molybdenum (Mo), titanium (Ti), or the like is used.

Referring to FIG. 6C, as the third mask process is performed, a passivation layer 151 having first and second contact holes 117 and 127 is formed on the lower substrate 145 on which the source / drain metal and the like are formed.

An inorganic insulating material is deposited on the lower substrate 145 on which the source / drain patterns and the like are formed by a deposition process such as PECVD. As the material of the protective film 151, silicon nitride (SiNx), silicon oxide (SiOx), or the like, which is an inorganic insulating material, is used. Afterwards, the passivation layer 151 is patterned by a photolithography process and an etching process to form a first contact hole 117 exposing the drain electrode 112 and a second contact hole 127 exposing the common line 116. A protective film 151 is formed.

Referring to FIG. 6D, as the fourth mask process is performed, the pixel electrode 114 and the common electrode 118 are formed on the lower substrate 145 on which the passivation layer 151 is formed.

The transparent electrode material is deposited on the lower substrate 145 on which the protective layer 151 is formed by a deposition method such as sputtering, and then patterned by a photolithography process and an etching process. Accordingly, the pixel electrode 114 contacting the drain electrode 112 through the first contact hole 117 and the common electrode 118 contacting the common line 116 through the second contact hole 127 are formed. Is formed.

The pixel electrode 114 is connected to the drain electrode 112 and is connected to the first horizontal portion 114a formed in parallel with the adjacent gate line 102 and the first horizontal portion 114a of the pixel electrode 114 and is common. And a first finger portion 114b parallel to the second finger portion 118b of the electrode 118.

The common electrode 118 extends from the second horizontal portion 118a partially overlapping the common line 116, and is parallel to the first finger portion 114b of the pixel electrode 114. The second finger portion 118b is provided.

Transparent electrode materials include indium tin oxide (hereinafter referred to as "ITO"), tin oxide (hereinafter referred to as "TO"), and indium zinc oxide (hereinafter referred to as "IZO"). Or indium tin zinc oxide (hereinafter referred to as "ITZO").

Thereafter, after forming an alignment material such as polyimide by a printing process, a rubbing process is performed to form a lower alignment layer 153 as illustrated in FIG. 6E.

A color filter array substrate 180 including a black matrix 156, a color filter 158, an overcoat layer 159, an upper alignment layer 161, etc., is formed separately from the manufacturing process of the thin film transistor array substrate 170 described above. do.

Thereafter, the ball spacer 162 is formed in a region overlapping at least one of the gate line 102, the common line 118, and the dummy pattern 210 of the thin film transistor array substrate 180, and then the liquid crystal 172. The liquid crystal display panel 190 is formed by bonding the color filter array substrate 170 and the thin film transistor array substrate 180 to each other.

As described above, the horizontal field application type liquid crystal display panel and the method of manufacturing the same according to the present invention form a dummy pattern between the gate line and the common line. The dummy pattern is simultaneously formed of the same material as the active layer of the semiconductor pattern on the gate insulating layer and has the same height as the thickness of the gate line and the common lines.

Accordingly, the step difference between the conventional gate line and the common line can be eliminated, so that the cell gap holding function by the ball spacer can be normally performed. As a result, it is possible to prevent deterioration in image quality due to conventional cell gap nonuniformity.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

A color filter array substrate; A thin film transistor array substrate bonded to the color filter array substrate with a liquid crystal interposed therebetween, The thin film transistor array substrate A gate line and a data line formed to cross each other on the substrate; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the thin film transistor; A common electrode formed in parallel with the pixel electrode to form a horizontal electric field with the pixel electrode; A common line formed parallel to the gate line on the same plane as the gate line and supplying a reference voltage to the common electrode; And a dummy pattern disposed between the common line and the gate line. The method of claim 1, A ball spacer for maintaining a gap between the color filter array substrate and the thin film transistor array substrate; The ball spacer And at least one of the gate line, the common line, and the dummy pattern. The method of claim 1, The thin film transistor is A gate electrode connected to the gate line; A source electrode connected to the data line; A drain electrode facing the source electrode; And an active layer forming a channel between the source electrode and the drain electrode. The method of claim 3, wherein And the dummy pattern is made of the same material as the active layer. The method of claim 1, And the dummy pattern has the same thickness as that of the gate line and the common line. The method of claim 1, And the dummy pattern has a line shape. The method of claim 1, The thin film transistor array substrate A gate insulating film formed on the substrate to cover the gate line and the common line; And the dummy pattern is formed on the gate insulating layer between the gate line and the common line. Forming a color filter array substrate; Forming a thin film transistor array substrate; Bonding the color filter array substrate and the color filter array substrate with liquid crystal interposed therebetween, Forming the thin film transistor array substrate Forming a gate pattern on the substrate, the gate pattern including the gate electrode, a gate line connected to the gate electrode, the gate line, and a common line parallel to the gate line; Forming a gate insulating film to cover the gate pattern; A source / drain pattern including a data line crossing the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and a channel between the source electrode and the drain electrode on the gate insulating layer; Forming a dummy pattern positioned between the active layer and the gate line and the common line; Forming a passivation layer having a first contact hole exposing the drain electrode and a second contact hole exposing the common line; And a pixel electrode in contact with the drain electrode through the first contact hole and a common electrode in contact with the common line through the second contact hole. The method of claim 8, Forming a ball spacer on the thin film transistor array substrate; And the ball spacer overlaps at least one of the gate line, the common line, and the dummy pattern. The method of claim 8, Forming the source / drain pattern, the active layer and the dummy pattern Sequentially forming a first semiconductor layer, a second semiconductor layer, and a first metal layer on the substrate on which the gate insulating film is formed; Forming a photoresist pattern in which a region in which the dummy pattern and the channel are to be formed has a relatively lower height than a region in which the source electrode and the drain pattern are to be formed by a photolithography process using a transflective mask; Removing the first semiconductor layer, the second semiconductor layer, and the first metal layer that are not overlapped with the photoresist pattern; Partially removing the photoresist pattern by an ashing process to expose the first metal layer only to the channel region and the region where the dummy pattern is to be formed; Removing the exposed first metal layer to form a source / drain pattern including a data line, a source electrode and a drain electrode and exposing a second semiconductor layer; Removing the remaining photoresist pattern; And removing the second semiconductor layer that is not overlapped with the source / drain pattern to expose the first semiconductor layer including the channel region, and to form the dummy pattern. Manufacturing method of display panel. The method of claim 10, And the thickness of the first semiconductor layer has the same height as the height of the gate pattern.

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