KR20080032294A - Method for fabricating semiconductor device with dual poly recess gate - Google Patents

Method for fabricating semiconductor device with dual poly recess gate Download PDF

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KR20080032294A
KR20080032294A KR1020060097821A KR20060097821A KR20080032294A KR 20080032294 A KR20080032294 A KR 20080032294A KR 1020060097821 A KR1020060097821 A KR 1020060097821A KR 20060097821 A KR20060097821 A KR 20060097821A KR 20080032294 A KR20080032294 A KR 20080032294A
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forming
semiconductor device
manufacturing
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gate
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KR100838377B1 (en
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유재선
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A method for manufacturing a semiconductor device with dual poly recess gate is provided to improve refresh property by a recess gate, and to achieve process speed enhancement and low power operation by forming the dual poly gate structure using a doped poly-silicon. A cell region and a peripheral region are defined on a substrate(11). A first conductive type poly-silicon layer(13A) is formed on the peripheral region. A carbon based hard mask for opening a recess reservation region of the cell region is formed at the entire surface of the resultant structure including the first conductive type poly-silicon layer. A recess pattern is formed at the cell region by using the hard mask as an etch mask. A second conductive type poly-silicon layer(20B) is formed on the entire surface of the resultant structure including the recess pattern of the cell region. The second conductive type poly-silicon layer which is formed on the first conductive type poly-silicon layer in the peripheral region is eliminated. A gate pattern is formed by patterning the first and second conductive type poly-silicon layers respectively.

Description

듀얼 폴리 리세스 게이트를 갖는 반도체 소자의 제조방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH DUAL POLY RECESS GATE}Method for manufacturing a semiconductor device having a dual poly recess gate {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH DUAL POLY RECESS GATE}

도 1a 내지 도 1j는 본 발명의 바람직한 실시예에 따른 듀얼 폴리 리세스 게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.1A to 1J are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly recess gate according to a preferred embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

11 : 반도체 기판 12 : 희생산화막11 semiconductor substrate 12 sacrificial oxide film

13A,B : P형 폴리실리콘막 14 : 제1감광막13A, B: P-type polysilicon film 14: First photosensitive film

15 : 하드마스크 16 : 반사방지막15: hard mask 16: antireflection film

17 : 제2감광막 18 : 리세스패턴17 second photosensitive film 18 recess pattern

19 : 게이트절연막 20A,B : N형 폴리실리콘막19: gate insulating film 20A, B: N-type polysilicon film

21 : 제3감광막 22 : 금속전극층21: third photosensitive film 22: metal electrode layer

23 : 게이트하드마스크층 24 : 제4감광막23: gate hard mask layer 24: fourth photosensitive film

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 듀얼 폴리 리세스 게이트를 갖는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a dual poly recess gate.

반도체 소자가 초고집적화 됨에 따라 게이트를 평탄한 활성영역 위에 형성하는 기존의 플라나 게이트(Planar Gate)배선 형성 방법은 게이트 채널길이(Gate channel Length)가 점점 작아지고 이온주입도핑(Implant Dopping)농도가 증가함에 따라 전계(Electric Filed) 증가에 의해 접합 누설전류(Junction Leakage)가 생겨 소자의 리프레시특성을 확보하기가 어렵다.As the semiconductor devices become highly integrated, the conventional planar gate wiring forming method for forming a gate over a flat active region becomes smaller as the gate channel length and the ion implantation doping concentration increase. As a result, an increase in electric filed causes junction leakage, which makes it difficult to secure refresh characteristics of the device.

이를 개선하기 위해 게이트 배선 형성방법으로 활성영역 기판을 리세스패턴으로 식각 후 게이트를 형성하는 리세스 게이트 공정이 실시되고 있다. In order to improve this, a recess gate process is performed in which a gate is formed after the active region substrate is etched into the recess pattern using a gate wiring method.

또한, 소자특성 향상을 위한 게이트형성 방법으로 PMOS게이트와 NMOS게이트 형성시 동일 폴리실리콘을 사용하지 않고 PMOS는 P형 폴리실리콘, NMOS는 N형폴리실리콘을 사용하여 소자의 동작 속도와 저전력 동작을 구현하는 듀얼 폴리 게이트(Dual Poly Gate;DPG)방법이 도입되고 있다. In addition, as a gate forming method for improving device characteristics, PMOS gate and NMOS gate do not use the same polysilicon, and PMOS uses P-type polysilicon and NMOS uses N-type polysilicon to realize device operation speed and low power operation. The Dual Poly Gate (DPG) method has been introduced.

특히, 패턴 크기가 작은 소자에서 상기의 소자 특성을 갖도록 하기 위해서는 셀영역의 리세스 게이트 구조에서의 듀얼 폴리 게이트 구조가 동시에 사용되어야 한다. 듀얼 폴리 게이트는 웨이퍼 전면에 도핑되지 않은 폴리실리콘(un-doped Poly Silicon)을 증착한 후, N+, P+ 감광막을 사용하여 N+영역에는 인산(Phosphorous)과 같은 N형 이온주입 공정을, P+영역에는 보론(Boron)과 같은 P형 이온주입 공정을 선택적으로 행하여 N형 폴리실리콘과 P형 폴리실리콘을 형성하는 것이다.In particular, in order to have the above device characteristics in a device having a small pattern size, a dual poly gate structure in a recess gate structure of a cell region should be used simultaneously. The dual poly gate is formed by depositing undoped poly silicon on the front surface of the wafer, and then using an N + and P + photoresist, using an N-type ion implantation process such as phosphorous in the N + region and a P + region in the P + region. P-type ion implantation processes such as boron are selectively performed to form N-type polysilicon and P-type polysilicon.

듀얼 폴리 게이트와 리세스 게이트가 함께 적용되는 구조에서는 셀영역 역시 도핑되지 않은 폴리실리콘에 N형 이온주입공정을 실시해야 하는데, 'Ｕ'자형의 리세스 게이트 내부는 폴리실리콘의 두께가 두꺼워지므로 리세스 게이트 내부 폴리실리콘까지 N형 이온주입을 할 경우에 활성영역 기판의 채널 대미지(Active sub Channel Damage)가 발생하므로 듀얼 폴리 게이트 구조에서는 리세스 내부 폴리실리콘을 N형으로 변화시킬 수 없는 문제점이 있다.In the structure where the dual poly gate and the recess gate are applied together, the N-type ion implantation process should be performed on the polysilicon which is also not doped with the cell region, and the thickness of the polysilicon is increased in the 'Ｕ'-shaped recess gate. When N-type ion implantation is performed to the polysilicon inside the recess gate, active sub-channel damage occurs in the active region substrate. Therefore, the polysilicon structure cannot change the polysilicon inside the recess to N-type. .

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 듀얼 폴리 게이트 구조에서 리세스 내부의 폴리실리콘을 N형으로 변화시킬 수 없는 문제를 해결하기 위한 듀얼 폴리 리세스 게이트를 갖는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and a semiconductor device having a dual poly recess gate for solving a problem in which the polysilicon inside the recess cannot be changed to an N-type in the dual poly gate structure. Its purpose is to provide a method of manufacturing.

상기 목적을 달성하기 위한 본 발명의 듀얼 폴리 리세스 게이트를 갖는 반도체 소자의 제조방법은 셀영역과 주변영역을 갖는 기판의 상기 주변영역의 상부에 제1도전형 폴리실리콘막을 형성하는 단계, 상기 제1도전형 폴리실리콘막을 포함하는 결과물의 전면에 상기 반도체 기판의 셀영역에 리세스예정지역을 오픈시키는 카본계 하드마스크를 형성하는 단계, 상기 카본계 하드마스크를 식각마스크로 상기 셀영역에 리세스패턴을 형성하는 단계, 상기 셀영역의 리세스패턴을 포함하는 결과 물의 전면에 제2도전형 폴리실리콘막을 형성하는 단계, 상기 주변영역에서 제1도전형 폴리실리콘막 상에 형성된 제2도전형 폴리실리콘막을 제거하는 단계, 상기 제1도전형 및 제2도전형 폴리실리콘막을 각각 패터닝하여 게이트패턴을 형성하는 단계를 포함한다.A method of manufacturing a semiconductor device having a dual poly recess gate of the present invention for achieving the above object comprises forming a first conductive polysilicon film on an upper portion of a peripheral region of a substrate having a cell region and a peripheral region, Forming a carbon-based hard mask on the front surface of the resultant product including a conductive polysilicon film to open a recessed region in the cell region of the semiconductor substrate, and recessing the carbon-based hard mask in the cell region using an etch mask. Forming a pattern, forming a second conductive polysilicon film on the entire surface of the resultant including the recess pattern of the cell region, and forming a second conductive polysilicon film on the first conductive polysilicon film in the peripheral region. Removing the silicon layer, and patterning the first conductive type and the second conductive type polysilicon layers, respectively, to form a gate pattern.

특히, 제1도전형 폴리실리콘막은 P형 불순물이 도핑된 것으로, 제2도전형 폴리실리콘막은 N형 불순물이 도핑된 것으로 형성하는 것을 특징으로 한다.In particular, the first conductive polysilicon film is doped with P-type impurities, and the second conductive polysilicon film is formed with doped N-type impurities.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시에를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, the most preferred embodiment of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도 1a 내지 도 1j는 본 발명의 바람직한 실시예에 따른 듀얼 폴리 리세스 게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.1A to 1J are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly recess gate according to an exemplary embodiment of the present invention.

도 1a에 도시된 바와 같이, 셀영역, 주변영역의 NMOS 및 PMOS가 정의된 반도체 기판(11) 상에 희생산화막(12)을 형성한다.As shown in FIG. 1A, a sacrificial oxide film 12 is formed on a semiconductor substrate 11 in which NMOS and PMOS in a cell region and a peripheral region are defined.

이어서, 희생산화막(12) 상에 P형 폴리실리콘막(13A, 13B)을 형성한다. Subsequently, P-type polysilicon films 13A and 13B are formed on the sacrificial oxide film 12.

이어서, P형 폴리실리콘막(13A, 13B) 상에 감광막을 코팅하고, 노광 및 현상으로 주변영역의 PMOS에만 존재하는 감광막패턴(14)을 형성한다. Subsequently, a photosensitive film is coated on the P-type polysilicon films 13A and 13B, and the photosensitive film pattern 14 existing only in the PMOS in the peripheral region is formed by exposure and development.

도 1b에 도시된 바와 같이, 감광막패턴(14)을 식각마스크로 셀영역 및 주변영역의 NMOS에 형성된 P형 폴리실리콘막(13B)을 식각하여 주변영역의 PMOS에만 P형 폴리실리콘막(13A)을 잔류시킨다.As shown in FIG. 1B, the P-type polysilicon film 13B formed on the NMOS in the cell region and the peripheral region is etched using the photoresist pattern 14 as an etch mask, so that only the P-type polysilicon layer 13A is in the PMOS region of the peripheral region. Is left.

여기서, 셀영역 및 주변영역의 NMOS에 형성된 P형 폴리실리콘막(13B)을 식각하는 공정은 Cl2, HBr 또는 BCl3 중에서 선택된 어느 하나 또는 두가지 이상의 혼합가스를 메인가스로 하고 O2 또는 N2를 첨가하여 하부 희생산화막(12)과의 선택비를 증가시켜 실시한다. 즉, P형 폴리실리콘막(13B)이 식각되어도 희생산화막(12)의 선택비를 확보함으로써 희생산화막(12)이 식각되지 않고, 따라서 반도체 기판(11)의 손실을 방지할 수 있다.Here, the step of etching the P-type polysilicon film 13B formed in the NMOS in the cell region and the peripheral region is any one or two or more mixed gases selected from Cl 2 , HBr, or BCl 3 as a main gas, and O 2 or N 2. The addition is performed to increase the selectivity with the lower sacrificial oxide film 12. That is, even when the P-type polysilicon film 13B is etched, the sacrificial oxide film 12 is not etched by securing the selectivity of the sacrificial oxide film 12, so that the loss of the semiconductor substrate 11 can be prevented.

이어서, 감광막패턴(14)을 제거한다.Next, the photosensitive film pattern 14 is removed.

도 1c에 도시된 바와 같이, P형 폴리실리콘막(13A)을 포함하는 결과물의 전면에 카본계 하드마스크(15)와 반사방지막(16)을 순차로 형성한다. 여기서, 카본계 하드마스크(15)는 카본계 폴리머로 형성하되, 바람직하게는 비정질카본으로 형성한다. 또한, 반사방지막(16)은 카본계 하드마스크(15)를 식각하기 위한 마스크 역할 및 후속 감광막의 노광공정에서 반사방지 역할을 하기 위한 것으로 실리콘계 폴리머로 형성하되, 바람직하게는 SiON으로 형성한다.As shown in FIG. 1C, the carbon-based hard mask 15 and the anti-reflection film 16 are sequentially formed on the entire surface of the resultant including the P-type polysilicon film 13A. Here, the carbon-based hard mask 15 is formed of a carbon-based polymer, preferably formed of amorphous carbon. In addition, the anti-reflection film 16 serves as a mask for etching the carbon-based hard mask 15 and for anti-reflection in a subsequent exposure process of the photosensitive film, and is formed of a silicon-based polymer, preferably SiON.

이어서, 반사방지막(16) 상에 감광막을 코팅하고 노광 및 현상으로 셀영역에 리세스예정지역을 오픈시키는 감광막패턴(17)을 형성한다.Subsequently, a photoresist layer 17 is coated on the antireflection layer 16 and a photoresist pattern 17 is formed to open a region to be recessed in the cell region through exposure and development.

도 1d에 도시된 바와 같이, 감광막패턴(17)을 식각마스크로 반사방지막(16) 및 카본계 하드마스크(15)를 식각한다. 여기서, 식각은 카본계 하드마스크(15)가 수직프로파일을 갖도록 N2, O2 및 H2의 혼합가스로 실시하고, 카본계 하드마스크(15)는 예컨대 비정질카본으로 형성한다.As shown in FIG. 1D, the anti-reflection film 16 and the carbon-based hard mask 15 are etched using the photoresist pattern 17 as an etch mask. The etching is performed using a mixed gas of N 2 , O 2, and H 2 such that the carbon hard mask 15 has a vertical profile, and the carbon hard mask 15 is formed of amorphous carbon, for example.

이어서, 카본계 하드마스크(15) 식각 후 잔류하는 감광막패턴(17) 및 반사방지막(16)을 제거한다.Subsequently, the photoresist pattern 17 and the anti-reflection film 16 remaining after the carbon-based hard mask 15 is etched are removed.

이어서, 카본계 하드마스크(15)를 식각마스크로 희생산화막(12) 및 셀영역의 반도체 기판(11)을 식각하여 리세스패턴(18)을 형성한다.Subsequently, the sacrificial oxide film 12 and the semiconductor substrate 11 in the cell region are etched using the carbon hard mask 15 as an etch mask to form a recess pattern 18.

여기서, 리세스패턴(18)은 ICP, DPS, ECR 또는 MERIE 타입의 장비에서 Cl2, HBr, Ar 및 O2가스를 혼합하여 식각하되, Cl2, HBr 및 Ar은 각각 10sccm∼100sccm의 유량, O2는 1sccm∼20sccm의 유량으로 하고, 50Ｗ∼400Ｗ의 바텀파워, 5mT∼50mT의 압력으로 실시한다.Here, the recess pattern 18 is etched by mixing Cl 2 , HBr, Ar and O 2 gas in the ICP, DPS, ECR or MERIE type equipment, Cl 2 , HBr and Ar are respectively flow rate of 10sccm ~ 100sccm, O 2 is carried out at a flow rate of 1 sccm to 20 sccm, at a bottom power of 50 kPa to 400 kPa, and at a pressure of 5 mT to 50 mT.

특히, 리세스패턴(18)을 형성하기 위한 식각마스크로 카본계 하드마스크(15)를 바람직하게는 비정질카본을 형성하였기 때문에 리세스식각시 폴리실리콘과의 식각선택비가 높아서 손실되지 않는다. 따라서, 카본계 하드마스크(15) 하부의 희생산화막(12) 및 반도체 기판(11)의 손실을 방지할 수 있다.In particular, since the carbon-based hard mask 15 is preferably formed of amorphous carbon as an etching mask for forming the recess pattern 18, the etching selectivity with the polysilicon is not lost due to the high etching selectivity. Therefore, it is possible to prevent loss of the sacrificial oxide film 12 and the semiconductor substrate 11 under the carbon-based hard mask 15.

이어서, 카본계 하드마스크(15)를 제거한다.Next, the carbon-based hard mask 15 is removed.

도 1e에 도시된 바와 같이, 리세스패턴(18)에 후처리식각을 실시한다. 여기서, 후처리식각은 리세스패턴(18)의 탑부분을 라운딩 시키고, 리세스패턴(18) 바닥부의 첨점(Horn)을 감소시키면서, 리세스패턴(18) 형성시 반도체 기판(11)의 플라즈마 데미지(Damage)를 완화시키기 위해 CF와 O2로 실시한다.As shown in FIG. 1E, the recess pattern 18 is subjected to post-process etching. Here, the post-process etching rounds the top portion of the recess pattern 18 and reduces the peaks of the bottom portion of the recess pattern 18, while reducing the plasma of the semiconductor substrate 11 when the recess pattern 18 is formed. In order to mitigate damage, it is carried out with CF and O 2 .

이어서, 리세스패턴(18) 형성 후 반도체 기판(11)에 잔류하는 희생산화막(12)을 습식식각으로 제거한다. 이는, 리세스패턴(18) 형성 후 반도체 기판(11) 에 잔류하는 희생산화막(12)이 위치별 두께차이로 인해 신뢰성이 나쁜것을 보상하기 위한 것이다. Subsequently, the sacrificial oxide film 12 remaining on the semiconductor substrate 11 after the recess pattern 18 is formed is removed by wet etching. This is to compensate for the poor reliability of the sacrificial oxide film 12 remaining on the semiconductor substrate 11 after the recess pattern 18 is formed due to the positional thickness difference.

특히, 희생산화막(12)은 리세스식각이 실시된 셀영역 및 주변영역의 NMOS부분만 식각되고 주변영역의 PMOS부분은 P형 폴리실리콘막(13A)으로 인해 식각되지 않고 잔류하여 게이트절연막역할을 한다. 따라서, 이하 주변영역의 PMOS부분에 잔류하는 희생산화막(12A)을 '제1게이트절연막(12A)'이라고 한다.In particular, the sacrificial oxide film 12 may only etch the NMOS portion of the cell region and the peripheral region where the recess is etched, and the PMOS portion of the peripheral region remains unetched due to the P-type polysilicon layer 13A to serve as a gate insulating layer. do. Accordingly, the sacrificial oxide film 12A remaining in the PMOS portion of the peripheral region is referred to as a first gate insulating film 12A.

이어서, 셀영역 및 주변영역의 NMOS부분에 제2게이트절연막(19)을 형성한다.Subsequently, a second gate insulating film 19 is formed in the NMOS portions of the cell region and the peripheral region.

이어서, 리세스패턴(18)을 포함한 결과물의 전면에 N형 폴리실리콘막(20A, 20B)을 형성한다. 특히, 제2게이트절연막(19) 상에 형성된 N형 폴리실리콘막(20B)은 후속 게이트배선막으로 사용하기 위한 것이다. 이때, 셀영역의 N형 폴리실리콘막(20B)은 리세스패턴(18)의 깊이로 인해 첨점(Ｈ)이 발생한다.Subsequently, N-type polysilicon films 20A and 20B are formed on the entire surface of the resultant including the recess pattern 18. In particular, the N-type polysilicon film 20B formed on the second gate insulating film 19 is for use as a subsequent gate wiring film. At this time, the point H is generated in the N-type polysilicon film 20B in the cell region due to the depth of the recess pattern 18.

도 1f에 도시된 바와 같이, 셀영역과 주변영역의 NMOS부분에 형성된 N형 폴리실리콘막(20B) 상에 제3감광막(21)을 형성한다. 이는, 주변영역의 PMOS에 형성된 N형 폴리실리콘막(20A)은 제거하고, 셀영역과 주변영역의 NMOS에만 게이트배선막으로 사용할 수 있도록 잔류시키기 위한 것이다.As shown in FIG. 1F, a third photosensitive film 21 is formed on the N-type polysilicon film 20B formed in the NMOS portions of the cell region and the peripheral region. This is to remove the N-type polysilicon film 20A formed in the PMOS in the peripheral region, and to leave the N-type polysilicon film 20A so as to be used as the gate wiring film only in the NMOS in the cell region and the peripheral region.

도 1g에 도시된 바와 같이, 제3감광막(21)을 식각마스크로 오픈된 N형 폴리실리콘막(20A)을 식각한다.As shown in FIG. 1G, the N-type polysilicon film 20A having the third photoresist film 21 opened as an etching mask is etched.

따라서, 셀영역 및 주변영역의 NMOS에는 N형 폴리실리콘막(20B)이, 주변영역의 PMOS에는 P형 폴리실리콘막(13A)이 잔류한다.Therefore, the N-type polysilicon film 20B remains in the NMOS of the cell region and the peripheral region, and the P-type polysilicon film 13A remains in the PMOS of the peripheral region.

이어서, 제3감광막(21)을 제거한다.Next, the third photosensitive film 21 is removed.

도 1h에 도시된 바와 같이, N형 폴리실리콘막(20B)의 첨점(Ｈ)을 제거한다. 여기서, 첨점(Ｈ)은 평탄화공정을 통해 제거하는데 평탄화공정은 바람직하게 부분 화학적기계적연마(Chemical Mechanical Polishing;CMP)를 실시한다. As shown in Fig. 1H, the peaks H of the N-type polysilicon film 20B are removed. Here, the point (H) is removed through a planarization process, which is preferably subjected to partial chemical mechanical polishing (CMP).

이는, 후속 게이트 패턴 형성이 원활하도록 하기 위한 것으로, 셀영역의 N형 폴리실리콘막(20B)의 화학적기계적연마와 동시에 주변영역의 N형 폴리실리콘막(20B) 및 P형 폴리실리콘막(13A)도 화학적기계적연마로 인해 연마량만큼 두께가 낮아진다.This is to facilitate the subsequent gate pattern formation, and the chemical mechanical polishing of the N-type polysilicon film 20B in the cell region and the N-type polysilicon film 20B and P-type polysilicon film 13A in the peripheral region at the same time. Also, due to chemical mechanical polishing, the thickness is lowered by the amount of polishing.

이로 인해, 평탄화된 N형 및 P형 폴리실리콘막(20C, 13C)을 형성할 수 있다.As a result, planarized N-type and P-type polysilicon films 20C and 13C can be formed.

도 1i에 도시된 바와 같이, N형 폴리실리콘막(20C) 및 P형 폴리실리콘막(13C) 상에 금속전극층(22)과 게이트하드마스크층(23)을 차례로 적층한다. 특히, 금속전극층(22)은 예컨대 텅스텐(Ｗ), 텅스텐실리사이드(ＷSix), 코발트실리사이드(CoxSix) 및 티타늄실리사이드(TixSix)의 그룹 중에서 선택된 어느 하나로 형성하고, 게이트하드마스크층(23)은 예컨대 질화막으로 형성한다.As shown in FIG. 1I, the metal electrode layer 22 and the gate hard mask layer 23 are sequentially stacked on the N-type polysilicon film 20C and the P-type polysilicon film 13C. In particular, the metal electrode layer 22 is formed of any one selected from, for example, tungsten, tungsten silicide (Xix), cobalt silicide (CoxSix) and titanium silicide (TixSix), and the gate hard mask layer 23 is formed of, for example, a nitride film. To form.

이어서, 게이트하드마스크층(23) 상에 게이트패턴을 정의하는 제4감광막(24)을 형성한다. Subsequently, a fourth photosensitive film 24 defining a gate pattern is formed on the gate hard mask layer 23.

도 1j에 도시된 바와 같이, 제4감광막(24)을 식각마스크로 게이트하드마스크층(23), 금속전극층(22), N형 및 P형 폴리실리콘막(13C, 20C)을 차례로 식각하여 게이트패턴을 형성한다.As shown in FIG. 1J, the gate hard mask layer 23, the metal electrode layer 22, the N-type and P-type polysilicon layers 13C and 20C are sequentially etched using the fourth photoresist layer 24 as an etch mask. Form a pattern.

여기서, 게이트하드마스크층(23) 및 금속전극층(22)의 식각은 ICP, DPS 또는 ECR과 같은 고밀도플라즈마 식각장치에서 BCl3, CxFx(예컨대 CF4, C2F6, C3F8), NFx(예컨대 NF3), SFx(예컨대 SF6) 및 Cl2 로 구성된 그룹 중에서 선택된 어느 하나 또는 두가지 이상의 가스를 혼합한 혼합가스를 메인가스로 실시하고, BCl3, CxFx, NFx 및 SFx 는 각각 10sccm∼50sccm의 유량, Cl2는 50sccm∼200sccm의 유량으로 실시한다. Here, the etching of the gate hard mask layer 23 and the metal electrode layer 22 may be performed using BCl 3 , CxFx (eg, CF 4 , C 2 F 6 , C 3 F 8 ), in a high density plasma etching apparatus such as ICP, DPS, or ECR. The main gas is a mixed gas of any one or two or more selected from the group consisting of NFx (eg NF 3 ), SFx (eg SF 6 ) and Cl 2 , and BCl 3 , CxFx, NFx and SFx are each 10 sccm A flow rate of -50 sccm and Cl 2 are performed at a flow rate of 50 sccm-200 sccm.

특히, ICP 또는 DPS타입의 장비에서 실시할때는 500Ｗ∼2000Ｗ의 소스파워로 실시하고, O2, N2, Ar 및 He 로 구성된 그룹 중에서 선택된 어느 하나 또는 두가지 이상의 가스를 혼합한 혼합가스를 첨가하여 실시하되, O2는 1sccm∼20sccm, N2는 1sccm∼100sccm, Ar은 50sccm∼200sccm, He는 50sccm∼200sccm의 유량으로 실시한다. 또한, ECR타입의 장비에서 실시할때는 1000Ｗ∼3000Ｗ의 마이크로웨이브파워로 실시하고, O2, N2, Ar 및 He 로 구성된 그룹 중에서 선택된 어느 하나 또는 두가지 이상의 가스를 혼합한 혼합가스를 첨가하여 실시하되, O2는 1sccm∼20sccm, N2는 1sccm∼100sccm, Ar은 50sccm∼200sccm, He는 50sccm∼200sccm의 유량으로 실시한다.Particularly, in the case of ICP or DPS type equipment, source power of 500 kW to 2000 kW is performed, and mixed gas mixed with one or two or more selected from the group consisting of O 2 , N 2 , Ar, and He is added. However, O 2 is carried out at a flow rate of 1 sccm to 20 sccm, N 2 to 1 sccm to 100 sccm, Ar to 50 sccm to 200 sccm, and He to 50 sccm to 200 sccm. In the case of the ECR type equipment, the microwave power of 1000 kW to 3000 kW is used, and a mixed gas of one or two or more gases selected from the group consisting of O 2 , N 2 , Ar, and He is added. , O 2 is 1 sccm- 20 sccm, N 2 is 1 sccm-100 sccm, Ar is 50 sccm-200 sccm, He is performed at a flow rate of 50 sccm-200 sccm.

이어서, N형 폴리실리콘막(20C) 및 P형 폴리실리콘막(13C)을 식각한다. 이를 위해, ICP, DPS 또는 ECR 중에서 선택된 어느 하나의 고밀도 플라즈마 식각장치에서 HBr과 산소가 혼합된 플라즈마를 사용하여 실시하되, ICP 또는 DPS의 경우 소스 파워를 500Ｗ∼2000Ｗ로 하고, HBr을 50sccm∼200sccm, O2를 2sccm∼20sccm의 유량으로 플로우하여 실시한다. 또한, ECR의 경우 마이크로웨이브파워를 1000Ｗ∼3000Ｗ로 하고, HBr을 50sccm∼200sccm, O2를 2sccm∼20sccm의 유량으로 플로우하여 실시한다.Subsequently, the N-type polysilicon film 20C and the P-type polysilicon film 13C are etched. To this end, the plasma is mixed with HBr and oxygen in any one of the high-density plasma etching apparatus selected from ICP, DPS or ECR, in the case of ICP or DPS source power 500 ~ 2000Ｗ, HBr 50sccm ~ 200sccm And O 2 at a flow rate of 2 sccm to 20 sccm. In the case of ECR, microwave power is set to 1000 mW to 3000 mW, HBr is performed at a flow rate of 50 sccm to 200 sccm and O 2 at a flow rate of 2 sccm to 20 sccm.

이어서, 과도식각을 실시한다. 여기서, 과도식각은 제1 및 제2게이트절연막(12A, 19)과 고선택비를 갖는 조건으로 실시한다. 이를 위해, Cl2/N2의 플라즈마 또는 Cl2/N2에 O2 또는 He를 첨가한 플라즈마로 실시하되, Cl2는 20sccm∼150sccm, N2는 10sccm∼100sccm의 유량으로 실시한다. 이는, N형 및 P형 폴리실리콘막(20C, 13C) 하부의 제1 및 제2게이트절연막(12A, 19)이 과도식각시 드러나더라도 손상을 입지 않도록 하기 위한 것이다.Subsequently, transient etching is performed. Here, the transient etching is performed under the condition of having a high selectivity with the first and second gate insulating films 12A and 19. To this end, the synthesis was carried out by the addition of O 2 plasma or a plasma He or Cl 2 / N 2 of Cl 2 / N 2, Cl 2 is 20sccm~150sccm, N 2 is carried out at a flow rate of 10sccm~100sccm. This is to prevent damage even when the first and second gate insulating films 12A and 19 under the N-type and P-type polysilicon films 20C and 13C are exposed during the excessive etching.

따라서, 제1 및 제2게이트절연막(12A, 19)의 손상없이 셀영역 및 주변영역의 NMOS에는 N형 폴리실리콘전극(20D), 금속전극(22A)과 게이트하드마스크(23A)가 적층된 게이트패턴, 주변영역의 PMOS에는 P형 폴리실리콘전극(20D), 금속전극(22A)과 게이트하드마스크(23A)가 적층된 게이트패턴이 형성된다.Accordingly, a gate in which an N-type polysilicon electrode 20D, a metal electrode 22A, and a gate hard mask 23A are stacked in the NMOS of the cell region and the peripheral region without damaging the first and second gate insulating layers 12A and 19. In the PMOS of the pattern and the peripheral region, a gate pattern in which the P-type polysilicon electrode 20D, the metal electrode 22A and the gate hard mask 23A are stacked is formed.

상기한 본 발명은, 도핑된 N형 및 P형폴리실리콘막(13A, 20B)을 직접 형성하여 게이트전극으로 사용함으로써, 특히 셀영역에 형성되는 리세스패턴(18)의 깊이로 인해 폴리실리콘막에 이온주입이 균일하게 되지 않아서 N형 폴리실리콘막으로 변화시킬 수 없는 문제점을 방지하는 장점이 있다.According to the present invention, the doped N-type and P-type polysilicon films 13A and 20B are directly formed and used as gate electrodes, and in particular, due to the depth of the recess pattern 18 formed in the cell region, the polysilicon film is formed. Since ion implantation is not uniform, there is an advantage of preventing a problem that cannot be changed into an N-type polysilicon film.

본 발명의 기술 사상은 상기 바람직한 실시예들에 따라 구체적으로 기록되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명에 의한 듀얼 폴리 리세스 게이트를 갖는 반도체 소자의 제조방법은 리세스 게이트를 사용하여 소자의 리프레시특성을 향상시키고, 도핑되어 있는 폴리실리콘을 사용한 듀얼 폴리 게이트구조를 형성하여 소자의 속도 향상 및 저전력 동작을 이룰 수 있어, 미세한 패턴 크기의 소자에서 고품질의 소자 제조가 가능한 효과가 있다.The method of manufacturing a semiconductor device having a dual poly recess gate according to the present invention described above improves the refresh characteristics of a device using a recess gate, and forms a dual poly gate structure using a doped polysilicon to increase the speed of the device. Improvements and low power operations can be achieved, resulting in high quality device fabrication in fine pattern size devices.

Claims (19)

셀영역과 주변영역을 갖는 기판의 상기 주변영역의 상부에 제1도전형 폴리실리콘막을 형성하는 단계;Forming a first conductive polysilicon film on the peripheral region of the substrate having a cell region and a peripheral region; 상기 제1도전형 폴리실리콘막을 포함하는 결과물의 전면에 상기 반도체 기판의 셀영역에 리세스예정지역을 오픈시키는 카본계 하드마스크를 형성하는 단계;Forming a carbon-based hard mask on a front surface of the resultant product including the first conductive polysilicon film to open a region to be recessed in a cell region of the semiconductor substrate; 상기 카본계 하드마스크를 식각마스크로 상기 셀영역에 리세스패턴을 형성하는 단계;Forming a recess pattern in the cell region using the carbon hard mask as an etch mask; 상기 셀영역의 리세스패턴을 포함하는 결과물의 전면에 제2도전형 폴리실리콘막을 형성하는 단계;Forming a second conductive polysilicon film on the entire surface of the resultant product including the recess pattern of the cell region; 상기 주변영역에서 제1도전형 폴리실리콘막 상에 형성된 제2도전형 폴리실리콘막을 제거하는 단계; 및Removing the second conductive polysilicon film formed on the first conductive polysilicon film in the peripheral region; And 상기 제1도전형 및 제2도전형 폴리실리콘막을 각각 패터닝하여 게이트패턴을 형성하는 단계Forming a gate pattern by patterning the first conductive type and the second conductive type polysilicon layers, respectively 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제1도전형 폴리실리콘막은,The first conductive polysilicon film, 상기 주변영역이 갖는 NMOS영역 및 PMOS영역 중 PMOS영역에만 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The semiconductor device manufacturing method of claim 1, wherein the peripheral region is formed only in the PMOS region of the NMOS region and PMOS region. 제2항에 있어서,The method of claim 2, 상기 제1도전형 폴리실리콘막을 형성하는 단계는,Forming the first conductive polysilicon film, 상기 셀영역과 주변영역이 정의된 반도체 기판 상에 희생산화막을 형성하는 단계;Forming a sacrificial oxide film on the semiconductor substrate in which the cell region and the peripheral region are defined; 상기 희생산화막 상에 제1도전형 폴리실리콘막을 형성하는 단계;Forming a first conductive polysilicon film on the sacrificial oxide film; 상기 제1도전형 폴리실리콘막 상에 감광막을 형성하는 단계;Forming a photoresist film on the first conductive polysilicon film; 노광 및 현상으로 상기 주변영역의 상부를 덮는 감광막패턴을 형성하는 단계;Forming a photoresist pattern covering the upper portion of the peripheral region by exposure and development; 상기 감광막을 식각마스크로 상기 제1도전형 폴리실리콘막을 식각하는 단계Etching the first conductive polysilicon layer using the photosensitive layer as an etching mask 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제3항에 있어서,The method of claim 3, 상기 제1도전형 폴리실리콘막을 식각하는 단계는,The etching of the first conductive polysilicon film may include: Cl2, HBr 또는 BCl3 중에서 선택된 어느 하나 또는 두가지 이상의 혼합가스를 메인가스로 하되, 산화막과의 식각선택비를 높이기 위해 O2 또는 N2를 첨가하여 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device, characterized in that any one or two or more of the mixed gas selected from Cl 2 , HBr or BCl 3 as the main gas, by adding O 2 or N 2 to increase the etching selectivity with the oxide film . 제1항에 있어서,The method of claim 1, 상기 카본계 하드마스크를 형성하는 단계는,Forming the carbon-based hard mask, 상기 제1도전형 폴리실리콘층을 포함하는 결과물의 전면에 카본계 하드마스크를 형성하는 단계;Forming a carbon-based hard mask on the entire surface of the resultant product including the first conductive polysilicon layer; 상기 카본계 하드마스크 상에 실리콘계 폴리머를 형성하는 단계;Forming a silicon-based polymer on the carbon-based hard mask; 상기 반사방지막 상에 상기 반도체 기판의 셀영역에 리세스예정지역을 오픈시키는 감광막패턴을 형성하는 단계; 및Forming a photoresist pattern on the anti-reflection film to open a recessed area in a cell region of the semiconductor substrate; And 상기 감광막패턴을 식각마스크로 상기 반사방지막 및 카본계 하드마스크를 식각하는 단계Etching the anti-reflection film and the carbon-based hard mask using the photoresist pattern as an etching mask 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제5항에 있어서,The method of claim 5, 상기 카본계 하드마스크는 카본계 폴리머를 사용하되, 비정질카본을 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The carbon-based hard mask is a method of manufacturing a semiconductor device, characterized in that using a carbon-based polymer, amorphous carbon. 제5항에 있어서,The method of claim 5, 상기 반사방지막은 실리콘계 폴리머를 사용하되, SiON을 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The anti-reflection film is a silicon-based polymer, a method of manufacturing a semiconductor device, characterized in that using SiON. 제5항 내지 제7항 중 어느 한 항에 있어서,The method according to any one of claims 5 to 7, 상기 SiON 및 비정질카본은 N2, O2 및 H2의 혼합가스로 식각하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device, characterized in that the SiON and amorphous carbon is etched with a mixed gas of N 2 , O 2 and H 2 . 제1항에 있어서,The method of claim 1, 상기 리세스패턴을 형성하는 단계는,Forming the recess pattern, ICP, DPS, ECR 또는 MERIE타입의 장비에서 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.A manufacturing method of a semiconductor device, characterized in that carried out in the equipment of the ICP, DPS, ECR or MERIE type. 제9항에 있어서,The method of claim 9, 상기 리세스패턴을 형성하는 단계는,Forming the recess pattern, Cl2, HBr, O2 및 Ar가스의 혼합가스로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, characterized in that it is carried out with a mixed gas of Cl 2 , HBr, O 2 and Ar gas. 제10항에 있어서,The method of claim 10, 상기 혼합가스는,The mixed gas, Cl2, HBr 및 Ar을 각각 10sccm∼100sccm의 유량, O2를 1sccm∼20sccm의 유량으로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.A method for manufacturing a semiconductor device, wherein Cl 2 , HBr, and Ar are respectively performed at a flow rate of 10 sccm to 100 sccm, and O 2 at a flow rate of 1 sccm to 20 sccm. 제9항에 있어서,The method of claim 9, 상기 리세스패턴을 형성하는 단계는,Forming the recess pattern, 50Ｗ∼400Ｗ의 바텀파워, 5mT∼50mT의 압력으로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.A method for manufacturing a semiconductor device, characterized by performing at a power of 50 mW to 400 mW and a pressure of 5 mT to 50 mT. 제1항에 있어서,The method of claim 1, 상기 제2도전형 폴리실리콘막을 형성하기 전에,Before forming the second conductive polysilicon film, 리세스의 탑부분을 라운딩시키기 위한 후처리공정을 실시하는 단계;Performing a post-treatment process to round the top portion of the recess; 상기 희생산화막을 제거하는 단계; 및Removing the sacrificial oxide film; And 상기 반도체 기판 상에 게이트절연막을 형성하는 단계Forming a gate insulating film on the semiconductor substrate 를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device further comprising. 제13항에 있어서,The method of claim 13, 상기 후처리공정은 CF와 O2 플라즈마를 사용하여 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The post-treatment step is a method of manufacturing a semiconductor device, characterized in that carried out using CF and O 2 plasma. 제13항에 있어서,The method of claim 13, 상기 희생산화막을 제거하는 단계는 습식식각으로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.Removing the sacrificial oxide film is a method of manufacturing a semiconductor device, characterized in that the wet etching. 제1항에 있어서,The method of claim 1, 상기 게이트패턴을 형성하기 전에,Before forming the gate pattern, 상기 셀영역의 제2도전형 폴리실리콘막의 균일도를 위해 소정두께 화학적기계적연마하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.And chemically polishing a predetermined thickness for uniformity of the second conductive polysilicon film in the cell region. 제1항에 있어서,The method of claim 1, 상기 게이트패턴을 형성하는 단계는,Forming the gate pattern, 상기 제1도전형 및 제2도전형 폴리실리콘막 상에 도전물질과 게이트하드마스크를 순차로 적층하는 단계; 및Sequentially depositing a conductive material and a gate hard mask on the first conductive type and the second conductive type polysilicon layers; And 상기 게이트하드마스크, 도전물질 및 폴리실리콘막을 식각하여 게이트패턴을 형성하는 단계Etching the gate hard mask, the conductive material and the polysilicon layer to form a gate pattern 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제17항에 있어서,The method of claim 17, 상기 도전물질은 텅스텐, 텅스텐실리사이드, 코발트실리사이드 및 티타늄실리사이드의 그룹 중에서 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The conductive material is a semiconductor device manufacturing method, characterized in that formed by any one selected from the group of tungsten, tungsten silicide, cobalt silicide and titanium silicide. 제1항에 있어서,The method of claim 1, 상기 제1도전형 폴리실리콘막은 P형 불순물이 도핑된 것이고, 상기 제2도전형 폴리실리콘막은 N형 불순물이 도핑된 것을 특징으로 하는 반도체 소자의 제조방법.The first conductive polysilicon film is doped with P-type impurities, and the second conductive polysilicon film is doped with N-type impurities.
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