KR20080029626A - A dielectric layer, forming method thereof and a capacitor of semiconductor device and forming method thereof using the same - Google Patents

Abstract

A dielectric layer for use in a semiconductor device is provided to substantially reduce a leakage current and simplify the process by using a dielectric having an amorphous layer instead of the use of a single dielectric layer. A dielectric layer(23) for use in a semiconductor device includes a plurality of crystallized high-k dielectric layers and an amorphous layer. The amorphous layer is formed of the same kind of material as the high-k dielectric layer between the pluralities of high-k dielectric layers to remove a continuous grain boundary of the high-k dielectric layer. The high-k dielectric layer is formed of any one high-k dielectric layer selected from the high-k dielectric layers having a dielectric constant of at least 9. The high-k dielectric layer is formed of any one high-k dielectric layer selected from a series of high-k dielectric layers such as ZrO2, Al2O3, Ta2O5, TiO2, Y2O3, HfO2 and La2O3.

Description

A dielectric film, a method of forming the same, and a capacitor and a method of forming the semiconductor device using the same {A DIELECTRIC LAYER, FORMING METHOD THEREOF AND A CAPACITOR OF SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF USING THE SAME}

1A to 1H are cross-sectional views illustrating a capacitor and a method of forming the semiconductor device according to the embodiment of the present invention.

FIG. 2 shows the ZrO ₂ film deposition process shown in FIG. 1G. FIG.

FIG. 3 shows the ZrON film deposition process shown in FIG. 1G. FIG.

<Explanation of symbols for main parts of drawing>

10 semiconductor substrate 11 interlayer insulating film

12: storage node contact hole 13: storage node contact plug

14: Ti film 15: TiN film

16: etching metal barrier layer 17: etching barrier layer

18: sacrificial insulating film 19: lower electrode

20, 22: ZrO ₂ film 21: ZrON film

23 dielectric film 24 upper electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a method of forming a capacitor of a semiconductor device, and more particularly, a method of forming a metal-insulator-metal (MIM) capacitor.

In the manufacturing process of DRAM (Dynamic Random Access Memory) device among semiconductor memory devices, as the design rule of device decreases, efforts are being actively made to secure cell capacitance within a limited area. .

One of the methods for securing cell capacitance is to use a material having a high dielectric constant. That is, instead of the conventional ONO (Oxide / Nitride / Oxide) film, a high dielectric film having a larger dielectric constant, such as Al ₂ O ₃ (ε = 9), HfO ₂ (ε = 25), ZrO ₂ (ε = 25) is used as the dielectric film.

Typically, the dielectric film is crystallized when the thickness of the thin film increases over a certain thickness. For example, in the case of ZrO ₂ , crystallization occurs at a thickness of ˜40 kPa or more. As such, when the dielectric film is crystallized, the dielectric constant increases compared to the amorphous film, which is advantageous in increasing cell capacitance, but the grain boundary is vulnerable to leakage current due to the crystallization, that is, the leakage current characteristic is degraded due to the path of leakage current. I have a problem.

Therefore, there is a need for a method capable of improving the leakage current characteristics of a capacitor while increasing the dielectric constant. One such method is to improve leakage current characteristics by depositing another dielectric film, such as Al ₂ O ₃ , having a different dielectric constant between ZrO ₂ dielectric films.

However, the above method has the following problems.

First, ZrO ₂ film and Al ₂ O ₃ When the film is formed by using different deposition chambers, a new deposition chamber is additionally required and manufacturing costs increase. In addition, ZrO ₂ film and Al ₂ O ₃ When the film is formed using the same chamber, the Al ₂ O ₃ → ZrO ₂ deposition process proceeds sequentially after all the wafers (ZrO ₂ deposition process), the process is more complicated.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and has the following objects.

First, an object of the present invention is to provide a dielectric film of a semiconductor device and a method of forming the same, which can improve leakage current characteristics while increasing capacitance.

Second, another object of the present invention is to provide a capacitor and a method of forming the semiconductor device using the dielectric film and the method of forming the semiconductor device.

Third, another object of the present invention is to provide a method for forming a capacitor of a semiconductor device, which can simplify the process through an in-situ process using a single deposition chamber.

In accordance with an aspect of the present invention, a plurality of crystallized high dielectric films and a material of the same type as the high dielectric film are formed between the high dielectric films to remove continuous grain boundaries of the high dielectric films. A dielectric film of a semiconductor device including an amorphous film is provided.

In addition, the present invention according to another aspect for achieving the above object is formed on the lower electrode, the lower electrode, a plurality of crystallized high dielectric film, the plurality of crystal grains to remove the continuous grain boundary of the high dielectric film A dielectric device including a dielectric film including an amorphous film formed of the same material as the high-k dielectric film between the high-k dielectric and the upper electrode formed on the dielectric film.

In addition, the present invention according to another aspect for achieving the above object, the step of preparing a substrate in which the lower electrode is formed, the same type using an in-situ process using the same chamber on the lower electrode A method of forming a capacitor of a semiconductor device, the method including forming a dielectric film including a crystalline film, an amorphous film, and a crystalline film as a high dielectric film, and forming an upper electrode on the dielectric film.

The present invention is based on the formation of a new dielectric film by two concepts. First, a high dielectric film having a large dielectric constant is used, and the dielectric constant is increased by crystallizing the high dielectric film. Second, when the high dielectric film is crystallized, in order to minimize leakage current components due to grain boundaries, the continuity of the grain boundaries of the high dielectric film is removed to form a discontinuous crystalline film.

The high dielectric film is as described in Table 1 below.

Here, Table 1 shows the G.D. Wilk et al., Journal of Applied Physics, vol. 89; no. 10, pp5243-5275 (2001) shows the dielectric film and its properties disclosed in the literature.

matter Dielectric constant (k) Bandgap Eg (eV) Crystal structure (s) SiO ₂ 3.9 8.9 Amorphous Si ₃ N ₄ 7 5.1 Amorphous Al ₂ O ₃ 9 8.7 Amorphous Y ₂ O ₃ 15 5.6 Cuboid La ₂ O ₃ 30 4.3 Hexagonal Cube Shape, Cube Shape Ta ₂ O ₅ 26 4.5 Tetragonal TiO ₂ 80 3.5 Square system type (Rutile, Anatase) HfO ₂ 25 5.7 Monoclinic, Rhombic, Cube ZrO ₂ 25 7.8 Monoclinic, Rhombic, Cube

For example, as shown in Table 1, ZrO ₂ has a value of about 25, which is much higher than that of the conventional ONO film. However, when using ZrO ₂ alone, crystallization is easily performed even at a very low temperature (~ 300 ° C.) and a thin thickness (<40 mA), which is vulnerable to leakage current characteristics. Therefore, it is not suitable for using ZrO ₂ alone as a dielectric film.

Therefore, the present invention does not use crystallized ZrO ₂ alone as a dielectric film, but forms a dielectric film with a ZrO ₂ / ZrON (amorphous) / ZrO ₂ stacked structure in order to remove continuity of grain boundaries. Through this, ZrO ₂ can be crystallized to secure a high dielectric constant, and the leakage current characteristics can be greatly improved than when the crystallized ZrO ₂ is used alone as a dielectric film.

In addition, the technical idea of the present invention is not limited to ZrO ₂ . All of the high dielectric films shown in Table 1 can be applied. For example, HfO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , Y ₂ O ₃ , La ₂ O _{3 is} also possible. That is, it is sufficient if the dielectric film is not formed of a material having continuous grain boundaries _.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals throughout the specification represent the same elements.

Example

1A to 1H are cross-sectional views illustrating a MIM capacitor and a method of forming the same according to an embodiment of the present invention. 1A to 1H are cross-sectional views illustrating an example of a method of forming a capacitor of a DRAM device for convenience of description.

First, as shown in FIG. 1A, a gate electrode, a junction region, and a landing plug of a well, an isolation layer, a word line transistor, and the like are manufactured through a series of semiconductor manufacturing processes. And a semiconductor substrate 10 on which a bit line, a cell driving transistor, an insulating film, and the like are formed.

Subsequently, an interlayer insulating film 11 is deposited on the substrate 10. In this case, the interlayer insulating layer 11 may be formed of an oxide-based material, for example, an HDP (High Density Plasma) oxide film, a Boron Phosphorus Silicate Glass (BPSG) film, a Phosphorus Silicate Glass (PSG) film, and a Plasma Enhanced Tetra Ethyle Ortho Silicate (PETOS) film. , USG (Un-doped Silicate Glass) film, Fluorinated Silicate Glass (FSG) film, Carbon Doped Oxide (CDO) film and OSG (Organo Silicate Glass) film formed of a single layer consisting of any one film, or at least these It is formed by a laminated film laminated with two or more layers.

Subsequently, the interlayer insulating layer 11 is etched to form a storage node contact plug contact hole 12 (hereinafter referred to as a storage node contact hole) to which the landing plug is exposed.

Subsequently, as illustrated in FIG. 1B, a polysilicon layer (not shown) is deposited on the entire structure including the storage node contact hole 12 so that the storage node contact hole 12 is filled.

Subsequently, the polysilicon film is polished by performing a chemical mechanical polishing (CMP) process. In this case, in the CMP process, the polysilicon film is selectively polished using a slurry having a polishing selectivity between the polysilicon film and the oxide film (interlayer insulating film). As a result, all of the polysilicon layers deposited on the interlayer insulating layer 11 are removed, and the polysilicon layers are isolated and remain only in the storage node contact holes 12.

Subsequently, a front etch process such as an etch back is performed to recess the polysilicon layer in the storage node contact hole 12 to a predetermined depth. In this case, the etch back process selectively etches only the polysilicon layer without losing the interlayer insulating layer 11 by using an etching selectivity between the polysilicon layer and the interlayer insulating layer 11. As a result, a storage node contact plug 13 electrically connected to the landing plug is formed in the storage node contact hole 12.

Subsequently, as illustrated in FIG. 1C, the Ti film 14 and the TiN film 15 are sequentially deposited along a step of the upper surface of the entire structure including the storage node contact plug 13.

Subsequently, the TiN film 15 and the Ti film 14 are etched by performing a CMP process or an etch back process. For example, in the etch back process, the TiN film 15 and the Ti film 14 are selectively etched using the interlayer insulating film 11 as an etch stop film. As a result, an etch metal barrier layer 16 is formed in which the groove-storage node contact plug 13 formed on the storage node contact plug 13 and the interlayer insulating film 11 are formed.

Subsequently, as shown in FIG. 1D, an etch barrier layer 17 is deposited over the entire structure including the etch metal barrier layer 16. In this case, the etching barrier layer 17 is formed using a nitride film-based material. For example, the etching barrier layer 17 is formed of a SiN film.

Subsequently, an insulating film 18 for forming a storage node pattern (hereinafter, referred to as a sacrificial insulating film) is deposited on the etch barrier layer 17 to implement a capacitor having a concave structure. In this case, the sacrificial insulating film 18 is formed of any one oxide film selected from oxide film-based films constituting the interlayer insulating film 11.

Subsequently, as shown in FIG. 1E, a photoresist film (not shown) is coated on the sacrificial insulating layer 18 (see FIG. 1D), and then an exposure and development process using a photo mask is performed to form a storage node pattern. A mask (hereinafter referred to as an etch mask) is formed.

Subsequently, the sacrificial insulating layer 18 is selectively etched by performing an etching process using the etching mask. As a result, a storage node pattern hole (not shown) is formed in the sacrificial insulating layer 18. Here, '18A' represents the sacrificial insulating layer 18 etched through the etching process, hereinafter referred to as a sacrificial insulating layer pattern 18A.

Subsequently, the etch barrier layer 17 (see FIG. 1D) exposed through the storage node pattern hole is etched. As a result, an etch barrier layer pattern 17A through which the etch metal barrier layer 16 is exposed is formed.

Subsequently, as illustrated in FIG. 1F, an electrode material (not shown) for lower electrodes is deposited along a step of an upper surface of the entire structure formed by the storage node pattern hole. In this case, the electrode material is any one of the metal electrode selected from the group of metal electrodes such as Ti, Ta, W, Hf, Zr, Ru, Pt, Ir, or TiN, TaN, WN, HfN, ZrN One of the nitride electrodes selected from the group of nitride electrodes may be used.

For example, when TiN is used as the electrode material, the deposition method is as follows. First, TiCl ₄ is used as the source gas, NH ₃ is used as the reaction gas, and the flow rates per second of the source gas and the reactant gas are 10 to 1000 sccm, respectively. At this time, the pressure of the reaction chamber (chamber) is maintained at 0.1 ~ 10torr, the temperature of the substrate 10 is maintained at 500 ~ 700 ℃. Under these process conditions, the thickness of the TiN film is carried out until the thickness is 200 to 400 kPa.

Subsequently, the lower electrode electrode material is separated by performing a CMP process or an etch back process. As a result, the lower electrode 19 is formed along the inner surface of the storage node pattern hole.

The lower electrode 19 may be formed of a structure in which a metal electrode and an oxide electrode are stacked, such as Ru / RuO ₂ , Ir / IrO ₂ , or the like, or an oxide electrode such as SrRuO ₃ .

Subsequently, as shown in FIG. 1G, the dielectric layer 23 is formed along the step of the upper surface of the entire structure including the lower electrode 19 using ALD (Atomic Layer Deposition) equipment. In this case, the dielectric layer 23 is formed in a stacked structure of ZrO ₂ (crystalline) / ZrON (amorphous) / ZrO ₂ (crystalline) as the same material through an in-situ process using the ALD equipment.

First, the ZrO ₂ film 20 deposition method is as follows. Use the ALD equipment. The deposition conditions were Zr (O-tBu) ₄ , Zr [N (CH ₃ ) ₂ ] ₄ , Zr [N (C ₂ H ₅ ) (CH ₃ )] ₄ , Zr [N (C ₂ H ₅ ) ₂ ] ₄ , Using a source gas selected from a group of Zr gases, such as Zr (tmhd) ₄ , Zr (OiC ₃ H ₇ ) ₃ (tmtd), Zr (OtBu) _4, and Zr (NEtMe) _4, and the substrate 10. ) Is maintained at 200 ~ 350 ℃, the pressure of the reaction chamber is maintained at 0.1 ~ 1torr. Further, the carrier gas for carrying the source gas using the Ar and, with an oxidizing agent is used for O _3, and the purge (purge) gas, uses a N _2.

As shown in FIG. 2, Zr source gas and Ar are injected into the reaction chamber of the ALD equipment for 0.1 to 10 seconds at a flow rate of 150 to 250 sccm per second, respectively, to adsorb Zr on top of a wafer (not shown). Then, N ₂ gas is injected into the reaction chamber into the reaction chamber for 3 to 10 seconds at a flow rate of 200 to 400 sccm per second to purge the Zr source gas remaining inside the reaction chamber without being adsorbed to the wafer. Let's do it. Then, O ₃ is injected into the reaction chamber into the reaction chamber for 3 to 10 seconds at a flow rate of 200 to 500 sccm per second to oxidize Zr adsorbed on the wafer to form a ZrO ₂ film. Then, N ₂ gas is injected into the reaction chamber into the reaction chamber for 3 to 10 seconds at a flow rate of 50 to 200 sccm per second to purge the unreacted O ₃ .

By repeating the above process, the ZrO ₂ film is repeatedly formed to have a thickness of 30 to 70 mm 3.

Next, the deposition method of the ZrON film 21 is as follows. ZrO ₂ film 20 deposition process and in-situ (in-situ). The ALD equipment is used as it is. The deposition conditions are the same as those of the ZrO ₂ film 20 deposition process, except that N ₂ O or N ₂ gas is used for nitriding.

As shown in FIG. 3, Zr source gas and Ar are injected into the reaction chamber of the ALD equipment for 0.1 to 10 seconds at a flow rate of 150 to 250 sccm per second, respectively, to adsorb Zr onto the wafer. Then, N ₂ gas is injected into the reaction chamber into the reaction chamber for 3 to 10 seconds at a flow rate of 200 to 400 sccm per second to purge the Zr source gas remaining inside the reaction chamber without being adsorbed to the wafer. Let's do it. Then, O ₃ is injected into the reaction chamber into the reaction chamber for 3 to 10 seconds at a flow rate of 200 to 500 sccm per second to oxidize Zr adsorbed on the wafer to form a ZrO ₂ film. Then, while injecting N ₂ O or N ₂ gas into the reaction chamber into the reaction chamber for 3 to 10 seconds at a flow rate of 500 to 2000 sccm per second, RF power (Radio Frequency power) is maintained at 30 to 500 W to maintain the plasma. (plasma) Nitriding.

By repeating the above process, the thickness of the ZrON film is repeatedly performed so that the thickness of the ZrON film becomes 2 to 20Å. The reason why the thickness of the ZrON film is controlled to 20 mW or less is to control the ZrON film as an amorphous film. This removes the continuous grain boundaries of the dielectric film 23.

Next, the method of depositing the ZrO ₂ film 22 is the same as the method of depositing the ZrO ₂ film 20, which is a lower layer of the dielectric film. At this time, the ZrO ₂ film 22 is formed to a thickness of about 30 ~ 70Å.

The dielectric layer 23 is performed in-situ in the same chamber using ALD equipment.

Meanwhile, plasma annealing and UV / O ₃ annealing (Ultra Violet / O ₃ ) to remove defects such as impurities such as carbon and hydrogen and oxygen vacancies in the film after ZrO ₂ film 20 and 22 are deposited. anneal). At this time, the plasma annealing process and the UV / O ₃ annealing process is carried out in-situ process using the ALD as it is.

First, the plasma annealing process is as follows. The pressure of the chamber is maintained at a temperature of 300 to 400 ° C. of the substrate 10 while maintaining the pressure at 0.1 to 1 torr, and 30 to 120 seconds in a mixed gas atmosphere in which 0 ₂ , N ₂ O or N ₂ and O ₂ are mixed. While plasma treatment with RF power of 50-200W. At this time, 0 ₂ , N ₂ O or inflow of the mixed gas mixed with N ₂ and O ₂ is maintained at 100 ~ 200sccm per second. The UV / O ₃ annealing process is performed for 2 to 10 minutes at a temperature of about 300 to 400 ° C. and maintaining the intensity of the lamp at 15 to 30 mV / cm ² .

On the other hand, O ₃ is used as an oxidant in the process of forming the dielectric film 23 including ZrO ₂ (20) / ZrON (21) / ZrO ₂ (22), but in addition to O ₃ , H ₂ O or an oxygen plasma is used. It can also be used. Further, although subjected to a purging process using an N ₂ gas, this may also be a vacuum pump as an example, or performed by using an Ar gas.

Subsequently, as shown in FIG. 1H, the upper electrode 24 is formed on the dielectric film 23. In this case, the upper electrode 24 is formed in a stacked structure of a TiN film formed by a chemical vapor deposition (CVD) process having good step coverage and a TiN film formed by a physical vapor deposition (PVD) process. At this time, the CVD TiN film is formed to a thickness of about 200 ~ 400 kPa, and the PVD TiN film is formed to a thickness of 600 ~ 1000 kPa.

For example, the CVD TIN film is formed by the following deposition process. TiCl ₄ is used as a source gas and NH ₃ gas is used as a reaction gas. Then, TiCl ₄ as a source gas and NH ₃ gas as a reaction gas are supplied at a flow rate of 10 to 1000 sccm per second, respectively. At this time, the pressure of the reaction chamber is maintained at 0.1 ~ 10torr, the temperature of the substrate 10 is maintained at a temperature of 500 ~ 600 ℃. This process is carried out until the CVD TiN film is deposited to a thickness of 200 ~ 400Å.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, an embodiment of the present invention has been described with respect to a capacitor forming method of a cone cave structure, but this is also an example, and a capacitor forming method of a cylinder structure is also applicable, and a dielectric film such as a flash memory device which is a nonvolatile memory device may be applied. It can apply to all the elements which are needed. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, according to the present invention, the intrinsic crystallized while securing a high dielectric constant by forming a dielectric film having an amorphous film blocking the continuity of the grain boundary in order to remove the continuity of the grain boundary, rather than using the high dielectric film alone as a dielectric film. The leakage current characteristics can be significantly improved compared with the case where the whole film is used alone as the dielectric film.

Second, according to the present invention, by forming a dielectric layer having a laminated structure in an in-situ process using a single chamber, the process can be simplified without additional equipment investment.

Claims (26)

A plurality of crystallized high dielectric films; And An amorphous film formed of the same material as the high dielectric film between the plurality of high dielectric films to remove continuous grain boundaries of the high dielectric film. Dielectric film of a semiconductor device comprising a The method of claim 1, The high dielectric film is a semiconductor dielectric film consisting of any one of a high dielectric film selected from high dielectric films having a dielectric constant of at least 9. The method of claim 1, The high dielectric film is ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , Y ₂ O ₃ , HfO ₂ and Among a series of high dielectric films such as La ₂ O ₃ A dielectric film of a semiconductor device composed of any one of the selected high dielectric films. The method of claim 3, wherein The ZrO ₂ film is a dielectric film of a semiconductor device formed to a thickness of 30 ~ 70Å. The method of claim 4, wherein The amorphous film is a ZrON film, the ZrON film is a dielectric film of a semiconductor device formed to a thickness of 2 ~ 20 ~. Lower electrode; A dielectric film formed on the lower electrode and having the configuration of any one of claims 1 to 5; And An upper electrode formed on the dielectric layer Capacitor of a semiconductor device comprising a. The method of claim 6, The lower electrode is made of any one metal electrode selected from a group of metal electrodes such as Ti, Ta, W, Hf, Zr, Ru, Pt, and Ir, or a group of nitrides such as TiN, TaN, WN, HfN, and ZrN. A capacitor of a semiconductor device comprising a nitride electrode selected from any one of electrodes, a stacked structure in which a metal electrode and an oxide electrode are laminated, such as Ru / RuO ₂ and Ir / IrO ₂ , or an oxide electrode such as SrRuO ₃ . The method of claim 6, The upper electrode is a capacitor of a semiconductor device made of TiN. Preparing a substrate having a lower electrode formed thereon; Forming a dielectric film including a crystalline film, an amorphous film, and a crystalline film as a homogeneous high-k dielectric film using an in-situ process using the same chamber on the lower electrode; And Forming an upper electrode on the dielectric layer Capacitor formation method of a semiconductor device comprising a. The method of claim 9, The high dielectric film is a capacitor forming method of a semiconductor device consisting of any one of the high dielectric film selected from the high dielectric film having a dielectric constant of at least 9. The method of claim 9, The high dielectric film is ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , Y ₂ O ₃ , HfO ₂ and Among a series of high dielectric films such as La ₂ O ₃ A method of forming a capacitor of a semiconductor device comprising any one selected high dielectric film. The method of claim 9, The dielectric layer is a capacitor forming method of a semiconductor device formed by the ALD process. The method of claim 12, The crystallization film is a ZrO ₂ film, and the amorphous film is a ZrON film is a capacitor forming method of a semiconductor device. The method of claim 13, The ZrO ₂ film and the ZrON film are Zr (O-tBu) ₄ , Zr [N (CH ₃ ) ₂ ] ₄ , Zr [N (C ₂ H ₅ ) (CH ₃ )] ₄ , Zr [N (C ₂ H) ₅ ) ₂ ] ₄ , Zr (tmhd) ₄ , Zr (OiC ₃ H ₇ ) ₃ (tmtd), Zr (OtBu) ₄ and Zr (NEtMe) ₄ source gas selected from any one selected from the group of Zr gas Capacitor formation method of a semiconductor device formed by. The method of claim 14, The ZrO ₂ film maintains the temperature of the substrate at 200 to 350 ° C., the chamber pressure to 0.1 to 1 torr, uses Ar as a carrier gas for transporting the source gas, and uses O ₃ as an oxidant. Capacitor formation method of a semiconductor device formed using N ₂ as the purge gas. The method of claim 15, The ZrO ₂ film, Adsorbing Zr onto the substrate by injecting the source gas and the Ar into the chamber for 0.1 to 10 seconds at a flow rate of 150 to 250 sccm per second, respectively; Injecting the N ₂ gas into the reaction chamber for 3 to 10 seconds at a flow rate of 200 to 400 sccm per second to purge the source gas remaining inside the chamber without being adsorbed onto a wafer; Injecting O ₃ into the chamber for 3 to 10 seconds at a flow rate of 200 to 500 sccm per second to oxidize Zr adsorbed on the substrate to form the ZrO ₂ film; And Purging the unreacted O ₃ by injecting the N ₂ gas into the chamber for 3 to 10 seconds at a flow rate of 50 to 200 sccm per second into the chamber. Capacitor formation method of a semiconductor device formed through. The method of claim 16, The ZrO ₂ film is a capacitor forming method of the semiconductor device to form a thickness of 30 ~ 70Å. The method of claim 14, The ZrON film, Injecting the source gas and Ar into the chamber for 0.1 to 10 seconds at a flow rate of 150 to 250 sccm per second to adsorb Zr on the wafer; Injecting N ₂ gas into the chamber at a flow rate of 200 to 400 sccm per second for 3 to 10 seconds to purge the Zr source gas remaining inside the chamber without being adsorbed to the substrate; Injecting O ₃ into the chamber at a flow rate of 200 to 500 sccm per second for 3 to 10 seconds to oxidize Zr adsorbed on the substrate to form a ZrO ₂ film; And Plasma nitriding treatment while injecting N ₂ O or N ₂ gas into the chamber for 3 to 10 seconds at a flow rate of 500 to 2000 sccm per second. Capacitor formation method of a semiconductor device formed through. The method of claim 18, The plasma nitridation process is a capacitor forming method of a semiconductor device performed by maintaining the RF power (Radio Frequency power) to 30 ~ 500W. The method of claim 9, After the forming of the dielectric film, the capacitor of the semiconductor device further comprises the step of performing a plasma annealing process or UV / O ₃ annealing process to remove impurities such as impurities such as carbon, hydrogen and oxygen vacancies in the crystalline film Formation method. The method of claim 20, And the plasma annealing process is performed in the dielectric film forming process and the in-situ process using the chamber. The method of claim 20, The plasma annealing process is maintained at a temperature of 300 ~ 400 ℃ of the substrate while maintaining the pressure of the chamber at 0.1 ~ 1torr, in a mixed gas atmosphere of 0 ₂ , N ₂ O or N ₂ and O ₂ mixed Capacitor formation method of a semiconductor device to perform at 50 ~ 200W RF power for 30 to 120 seconds. The method of claim 22, The 0 ₂ , the N ₂ O or the inflow amount of the mixed gas of the N ₂ and O ₂ is mixed to maintain a capacitor of a semiconductor device at 100 ~ 200sccm per second. The method of claim 20, In the UV / O ₃ annealing process, a capacitor of a semiconductor device is formed for 2 to 10 minutes while maintaining a temperature of about 300 to 400 ° C. and an intensity of a lamp at 15 to 30 mV / cm ² . Way. The method of claim 9, The lower electrode is made of any one metal electrode selected from a group of metal electrodes such as Ti, Ta, W, Hf, Zr, Ru, Pt, and Ir, or a group of nitrides such as TiN, TaN, WN, HfN, and ZrN. Forming a capacitor of a semiconductor device consisting of a nitride electrode of any one selected from among the electrodes, a laminated structure in which a metal electrode and an oxide electrode are laminated, such as Ru / RuO ₂ and Ir / IrO ₂ , or an oxide electrode such as SrRuO ₃ Way. The method of claim 9, And the upper electrode is formed of TiN.

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