KR20080029604A - Method for manufacturing flash memory device - Google Patents

Abstract

A method for manufacturing a flash memory device is provided to realize a relatively fine design rule by employing a polysilicon layer/tungsten layer process in a gate pattern and to easily manufacture flash memory devices in the technology of 90mn or below. A method for manufacturing a flash memory device includes defining a cell area on a substrate(30); forming a plurality of floating gates in the cell area of the substrate; forming an insulation film(32) on the floating gate; producing a recess part to expose the floating gate by patterning the insulation film; forming a dielectric thin film(36) along the recess part; forming a first conductive film for a control gate on the dielectric thin film; and forming a second conductive film on the first conductive film. The method further includes eliminating the second conductive film until the first conductive film is exposed by performing a first chemical mechanical polishing process; and removing the first and second conductive films by performing a second chemical mechanical polishing process until the dielectric film is exposed.

Description

Manufacturing Method of Flash Memory Device {METHOD FOR MANUFACTURING FLASH MEMORY DEVICE}

1 is a cross-sectional view of a flash memory device according to the prior art.

2A to 2C are process cross-sectional views showing a method of manufacturing a flash memory device according to a preferred embodiment of the present invention, in particular, a process cross-sectional view showing a method of manufacturing a first gate pattern.

3A to 3E are cross-sectional views illustrating a method of manufacturing a flash memory device, particularly a method of manufacturing a cell region, according to a preferred embodiment of the present invention.

4A to 4G are cross-sectional views illustrating a method of manufacturing a flash memory device according to a preferred embodiment of the present invention, particularly a method of manufacturing a peripheral region.

5 to 7 are process cross-sectional views showing features of a flash memory device of the present invention.

Explanation of symbols on the main parts of the drawings

30 substrate 32 insulating film

33 polysilicon film 35 insulating film

36 dielectric film 37 polysilicon film

38: metal film

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for manufacturing a flash memory device.

Flash memory devices are widely used in recent years because they can store data without applying power. As the degree of integration of semiconductor memory devices increases and design rules decrease, it is increasingly difficult to make semiconductor memory devices reliable. In particular, the flash memory device doublely forms a gate pattern, and since the double gate pattern is used to store data, precise manufacturing of the gate pattern is of paramount importance.

Previously, a polysilicon film / tungsten silicide film was formed by laminating a gate pattern. However, in this case, the conductivity of the gate pattern is too low. Recently, development of a gate pattern made of a polysilicon film / tungsten film or a tungsten film has been developed.

1 is a cross-sectional view of a flash memory device according to the prior art. 1 is a cross-sectional view of a cell region, and a right diagram is a block diagram of a peripheral region.

As shown in FIG. 1, a cell region of a flash memory device includes a substrate 10, a dielectric thin film 11, a first polysilicon film 12, a dielectric thin film 13, a second polysilicon film 14, The tungsten silicide film 15, the silicon nitride film 16, and the silicon oxide film 17 are provided. The peripheral region of the flash memory device includes a substrate 10, a dielectric thin film 13, a second polysilicon film 14, a tungsten silicide film 15, a silicon nitride film 16, and a silicon oxide film 17.

In general, the SAFG (Self-Aligned Floating Gate) method is a trench etching in the word line direction to form a floating gate pattern using a polysilicon film pattern. Next, during the etching process for the control gate pattern, the polysilicon layer pattern for the floating gate pattern is floated by etching in the bit line direction in the RIE manner. Although this method has strength in the word line direction, there is a problem in increasing the degree of integration by using the RIE method in the bit line direction.

That is, the SAFG thin film etching a plurality of layers in which the first polysilicon film, the dielectric thin film, the second polysilicon film, the tungsten silicide film, the silicon nitride film, and the silicon oxide film are etched in one process is difficult when the design rule is small. have.

In particular, since the MOS transistor formed in the peripheral region has no floating gate, the first polysilicon and the silicon oxide film formed by the SAFG process are removed, and then the silicon oxide film is formed again, and then the MOS transistor must be manufactured by the subsequent process.

In addition, when the control gate pattern is etched using the hard mask, a gap between the gate patterns as well as the substrate is generated due to the high stepped film, which makes the gap fill difficult in subsequent steps. In the RIE method, after forming the control gate, a space nitride film is generally used to protect the control gate and form a metal contact plug. At this time, an etching material having a high selectivity between the silicon nitride film and the silicon oxide film is required. In this process, it is difficult to find an appropriate etching material. In addition, the contact process proceeds to a self-aligned process, which causes a problem that the width of the contact plug decreases due to the thickness of the silicon nitride film for protecting the gate pattern, thereby increasing the resistance value.

In addition, the morph transistors formed in the cell region and the morph transistors formed in the peripheral region have different heights because of different structures. Since the height of the MOS transistor in the peripheral area is low, it is very difficult to form the contact plug in the peripheral area.

An object of the present invention is to provide a method of manufacturing a flash memory device including a gate pattern of a polysilicon film / tantalum silicon nitride film / tungsten structure which is advantageous for high deposition.

The present invention includes the steps of defining a cell region on a substrate; Forming a plurality of floating gates in a cell region on the substrate; Forming an insulating film on the floating gate; Patterning the insulating layer to form a recess exposing the floating gate; forming a dielectric thin film along the recess; Forming a first conductive film for a control gate on the dielectric thin film; And forming a second conductive film on the first conductive film.

The present invention includes the steps of defining a peripheral region on a substrate; Forming a first conductive layer in the peripheral region, the first conductive layer serving as a floating gate of the cell region; Forming an insulating film on the first conductive film; Patterning the insulating film to expose the first conductive film; Performing an etching process to further widen the gap between the plurality of insulating layer patterns; Forming a second conductive film along the insulating film pattern; Forming a third conductive film on the second conductive film; And removing the third conductive film until the second conductive film is exposed.

The present invention includes the steps of defining a cell region and a peripheral region on a substrate; Forming a first conductive layer in the cell region and in the peripheral region in the cell region; Forming an insulating film on the first conductive film; Patterning the insulating film to expose the first conductive film; Forming a dielectric thin film along the insulating film pattern to be formed on the first exposed conductive film; Removing the dielectric thin film formed on the peripheral region; Performing an etching process to further widen the gap between the insulating layer patterns formed on the peripheral region; Forming a second conductive layer in the cell region and a peripheral region in the cell region along the insulating layer; and forming a third conductive layer on the second conductive layer. to provide.

In the present invention, when using a tungsten gate pattern, when forming the gate pattern by a chemical mechanical polishing process, the problem is that the resistance of the other gate pattern increases as the area of the tungsten film decreases. In order to solve this problem, the present invention proposes a process method of forming a gate pattern using a dry etching process and a Pd-sputtering pretreatment method, thereby reducing the total number of processes and increasing the area of the gate pattern. .

The technical principles of the present invention include forming a control gate pattern with damascene fixation, and techniques for applying the present invention to separate the polysilicon film for the floating gate before the polysilicon film for the control gate is deposited.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2C are cross-sectional views illustrating a method of manufacturing a flash memory device according to a preferred embodiment of the present invention. In particular, it is a cross-sectional view of a process for forming a first gate pattern for a floating gate of a cell region.

A feature of the method of manufacturing a flash memory device according to the present embodiment uses SAFG technology, but separates the polysilicon film for the floating gate before depositing the polysilicon film for the control gate. Subsequently, a control gate of the polysilicon film / tungsten film is formed by the damascene process, and the insulating film is tilted by the dry etching process before the polysilicon film for the control gate is formed, and subsequent tungsten using a pretreatment method using a sputtering method. To form a film. When the tungsten film is formed in this way, the adhesion and unit area are increased to decrease the resistance, thereby increasing the program speed of the flash memory.

2A to 2C are upper cross sectional views of the cell regions, and lower views are process cross sectional views of the peripheral regions.

As shown in FIG. 2A, a buffered silicon oxide film / silicon nitride film 31 is formed on the substrate 30, and trench etching is performed in the word line direction. The silicon oxide film 32 is formed in the trench formed in this etching process. A silicon oxide film is formed in the trench and planarized using a chemical mechanical polishing process so that the silicon oxide film is embedded only in the trench.

Then, as shown in FIG. 2B, the buffer silicon oxide film / silicon nitride film 31 is removed. Subsequently, a process of reducing the width of the silicon oxide film 32 formed in the uneven form is performed.

Then, as shown in Fig. 2C, a polysilicon film 33 for the floating gate is formed. Subsequently, an ion implantation process for the operation of the transistor is performed. That is, a tunneling oxide film is formed and impurities are injected into the polysilicon film 33.

Subsequently, the polysilicon film 33 is separated by the silicon oxide film 32 in the word line and bit line directions using a chemical mechanical smoke film process.

3A to 3E are cross-sectional views illustrating a method of manufacturing a flash memory device according to a preferred embodiment of the present invention, particularly a method of manufacturing a cell region.

Subsequently, with reference to FIGS. 3A to 3E, first, a subsequent process will be described centering on the cell region.

As shown in FIG. 3A, a silicon nitride film 34 is formed as an etch stop film, and an insulating film 35 is formed to a thickness such that a control gate is formed thereon.

Subsequently, as shown in FIG. 3B, the insulating film 35 for the damascene process is patterned. Subsequently, the silicon nitride film 34 is removed to form a hole. The hole generated at this time is subjected to an over-etching process to a certain extent so that the polysilicon film to be used as a control gate in the subsequent process and the lower dielectric thin film are in contact with the polysilicon thin film 34 in the largest possible area. Subsequently, the dielectric thin film 36 is formed of an ONO film.

Subsequently, as shown in FIG. 3C, polysilicon 35 for the control gate is formed along the step of the insulating film 35. Next, a tungsten nitride film / tungsten film 38 is formed on the polysilicon 35.

Then, as shown in Fig. 3D, the planarization process is performed to remove the step between the tungsten nitride film / tungsten film 38 and the polysilicon film 37. At this time, step removal is performed by first removing the tungsten film by chemical mechanical polishing fixation. At this time, the polysilicon film serves as a polishing stop film. The polysilicon film is then removed by chemical mechanical polishing fixation.

Subsequently, as shown in Fig. 3E, an insulating film 39 is formed.

4A to 4G are cross-sectional views illustrating a method of manufacturing a flash memory device according to a preferred embodiment of the present invention, particularly a method of manufacturing a peripheral region. Each layer in the peripheral region is a film forming the same process when the layers in the cell region are formed. Subsequently, the peripheral area will be described with reference to FIGS. 4A to 4G.

As shown in Fig. 4A, a silicon nitride film 34 is formed as an etch stop film, and an insulating film 35 is formed thereon.

Subsequently, as shown in FIG. 4B, the insulating film 35 and the silicon nitride film 34 are patterned so that the polysilicon film 33 is exposed. At this time, the silicon nitride film 34 serves as an etch stop film. Subsequently, after forming the entire surface of the substrate to form the dielectric thin film 36 in the cell region, the dielectric thin film 36 in the peripheral region is removed. Since the dielectric thin film 36 in the peripheral region is removed, the peripheral region is electrically connected to the polysilicon film 33 and the polysilicon film to be formed in a subsequent process.

Subsequently, as shown in FIG. 4C, the insulating layer 35 is removed to some extent through an over etching process to generate a slope. This slope is made to increase the deposition area of the tungsten film to be formed in a subsequent process.

Next, as shown in FIG. 4D, a polysilicon film 37 is formed along the insulating film 35. This polysilicon film 37 is for a control gate in the cell region.

Then, as shown in Fig. 4E, a tungsten film / tungsten nitride film 38 is formed.

Next, as shown in FIG. 4F, the planarization process is performed to remove the step between the tungsten nitride film / tungsten film 38 and the polysilicon film 37. At this time, the step removal is performed by first removing the tungsten film by chemical mechanical polishing fixation and then removing the polysilicon film by chemical mechanical polishing fixation.

Subsequently, as shown in Fig. 4G, an insulating film 39 is formed.

Each of the layers in the above-described cell region and the peripheral region is not formed separately, and those represented by the same drawing notation are formed by the same process. In forming a tungsten film, a tantalum silicon nitride film (TaSiN) is formed at the bottom of the tungsten diffusion preventing film. In addition, before the deposition of the tungsten barrier film, the pd-sputtering process is performed to improve the adhesion. A tantalum silicon nitride film (TaSiN) is deposited by a reactive sputtering process using Ta ₃ Si ₃ as a target gas in a mixed gas atmosphere of Ar gas and N 2 gas.

The polysilicon film for the control gate is formed at about 500 kV and the tungsten film is formed at the range of 500 to 2000 kV.

In addition, when the flash memory device is manufactured, the chemical mechanical polishing process of the tungsten film is performed first, followed by the chemical mechanical polishing process of the polysilicon film. Therefore, in the chemical mechanical polishing process of the tungsten film, the polysilicon film 37 at the bottom thereof serves as a barrier film, and the loss of tungsten is almost upsected in the chemical mechanical polishing process of the polysilicon film.

5 to 7 are process cross-sectional views illustrating features of the flash memory device of the present invention.

As shown in FIG. 5, in the flash memory device according to the present invention, after the polysilicon film 33 for the floating gate is formed, a process of damaging the polysilicon film / tungsten film for the control gate is performed. At this time, in order to enlarge the contact area between the control gate and the floating gate, the polysilicon film 33 is overetched.

Fig. 6 uses a tantalum silicon nitride film as the barrier film of the tungsten film when laminating a polysilicon film and a tungsten film for the control gate.

6 shows a case where a titanium nitride film (TiN) and a titanium film (Ti) are used as the barrier film of the tungsten film, and a diagram on the right shows a case where a tantalum silicon nitride film is used as the barrier film of the tungsten film.

7 is a cross-sectional view showing a cell region and a peripheral region of a flash memory device finally completed by the present invention.

When manufacturing a flash memory device according to the present embodiment, the gate difference is about 2750 ~ 3000Å, the thickness of about 50 to 70% is reduced than the gate pattern by the conventional self-aligned etching process.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention, when the polysilicon film / tungsten film process is introduced into the gate pattern of the flash memory device, the total number of processes for forming the gate is greatly reduced, and a finer design rule can be realized. In addition, the formation area of tungsten can be increased, so that a flash memory device can be easily manufactured in a technology of 90mn or less.

Claims (22)

Defining a cell region on the substrate; Forming a plurality of floating gates in a cell region on the substrate; Forming an insulating film on the floating gate; Patterning the insulating film to form a recess exposing the floating gate; Forming a dielectric thin film along the recess; Forming a first conductive film for a control gate on the dielectric thin film; And Forming a second conductive film on the first conductive film Method of manufacturing a flash memory device comprising a. The method of claim 1, Performing a first chemical mechanical polishing process to remove the second conductive film until the first conductive film is exposed; And And removing the first conductive film and the second conductive film by performing a second chemical mechanical polishing process until the dielectric thin film is exposed. The method of claim 2, And the first conductive film is a polysilicon film. The method of claim 3, wherein And the second conductive film is a tungsten film. The method of claim 4, wherein And forming a tantalum silicon nitride film under the second conductive film to prevent diffusion of the tungsten film. The method of claim 5, wherein And forming a tantalum silicon nitride film and then proceeding with a pd-sputtering process for improving the adhesion of the tungsten film. The method of claim 1, And the floating gate is partially etched in the process of forming the recess. The method of claim 7, wherein Forming the floating gate Forming a buffer film on the substrate; Patterning the buffer layer to define an isolation region; Forming a plurality of trenches by removing a predetermined region of the substrate using the buffer layer pattern as an etch stop layer; Embedding an insulating film in the trench Removing the buffer layer pattern; Removing a portion of the protruding portion of the insulating layer pattern to widen the gap between the insulating layer and the insulating layer; And And embedding a third conductive film between the insulating film on the substrate and the insulating film on the substrate. The method of claim 8, And said third conductive film is a polysilicon film. Defining a peripheral region on the substrate; Forming a first conductive layer in the peripheral region, the first conductive layer serving as a floating gate of the cell region; Forming an insulating film on the first conductive film; Patterning the insulating film to expose the first conductive film; Performing an etching process to further widen the gap between the plurality of insulating layer patterns; Forming a second conductive film along the insulating film pattern; Forming a third conductive film on the second conductive film; And Removing the third conductive film until the second conductive film is exposed Method of manufacturing a flash memory device comprising a. The method of claim 10, And the second conductive film is a polysilicon film. The method of claim 11, And the third conductive film is a tungsten film. The method of claim 12, And forming a tantalum silicon nitride film on top of the second conductive film to prevent diffusion of the tungsten film. The method of claim 13, And forming a tantalum silicon nitride film and then performing a pd-sputtering process for improving adhesion of the tungsten film. The method of claim 10, The etching process is a manufacturing method of a flash memory device, characterized in that the dry etching process. Defining a cell region and a peripheral region on the substrate; Forming a first conductive layer in the cell region and in the peripheral region in the cell region; Forming an insulating film on the first conductive film; Patterning the insulating film to expose the first conductive film; Forming a dielectric thin film along the insulating film pattern to be formed on the first exposed conductive film; Removing the dielectric thin film formed on the peripheral region; Performing an etching process to further widen the gap between the insulating layer patterns formed on the peripheral region; Forming a second conductive layer in the cell region and a peripheral region in the cell region along the insulating layer; and Forming a third conductive film on the second conductive film Method of manufacturing a flash memory device comprising a. The method of claim 16, Performing a first chemical mechanical polishing process to remove the third conductive film until the second conductive film is exposed; And And removing the first conductive film and the second conductive film by performing a second chemical mechanical polishing process until the dielectric thin film of the cell region is exposed. The method of claim 16, And the first conductive film is a polysilicon film. The method of claim 18, And the second conductive film is a tungsten film. The method of claim 19, And forming a tantalum silicon nitride film under the second conductive film to prevent diffusion of the tungsten film. The method of claim 20, And forming a tantalum silicon nitride film and then performing a pd-sputtering process for improving adhesion of the tungsten film. The method of claim 16, And a first conductive layer serving as a floating gate is partially etched in the process of patterning the insulating layer.

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