KR20080029275A - Thin flip chip package and manufacturing process of the same - Google Patents

Thin flip chip package and manufacturing process of the same Download PDF

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Publication number
KR20080029275A
KR20080029275A KR1020060095100A KR20060095100A KR20080029275A KR 20080029275 A KR20080029275 A KR 20080029275A KR 1020060095100 A KR1020060095100 A KR 1020060095100A KR 20060095100 A KR20060095100 A KR 20060095100A KR 20080029275 A KR20080029275 A KR 20080029275A
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South Korea
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substrate
circuit pattern
flip chip
semiconductor chip
core material
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KR1020060095100A
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Korean (ko)
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김재면
박창준
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주식회사 하이닉스반도체
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Priority to KR1020060095100A priority Critical patent/KR20080029275A/en
Publication of KR20080029275A publication Critical patent/KR20080029275A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A thin flip chip package and a manufacturing method thereof are provided to downsize the package by removing a core material serving as a support for a circuit pattern and a solder ball land formed under the core material and attaching a solder ball to a bottom surface of a bump land. A substrate has a circuit pattern and a solder resist(110) for exposing a portion of the circuit pattern, and a core material is removed from the substrate by grinding, polishing or wet etching. A semiconductor chip(130) is flip-chip bonded to the upper surface of the exposed circuit pattern via a bump(134). A filler material(140) is disposed between the semiconductor chip and the substrate, and a solder ball(150) is attached to the lower surface of the exposed circuit pattern.

Description

박형 플립 칩 패키지 및 이의 제조 방법{THIN FLIP CHIP PACKAGE AND MANUFACTURING PROCESS OF THE SAME}Thin flip chip package and manufacturing method thereof {THIN FLIP CHIP PACKAGE AND MANUFACTURING PROCESS OF THE SAME}

도 1은 종래 기술에 따른 박형 플립 칩 패키지를 도시한 단면도.1 is a cross-sectional view showing a thin flip chip package according to the prior art.

도 2는 본 발명의 실시예에 따른 박형 플립 칩 패키지를 도시한 단면도.2 is a cross-sectional view showing a thin flip chip package according to an embodiment of the present invention.

도 3a 내지 도 3f는 본 발명의 실시예에 따른 박형 플립 칩 패키지의 제조 방법을 설명하기 위하여 도시한 단면도.3A to 3F are cross-sectional views illustrating a method of manufacturing a thin flip chip package according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

110 : 솔더 레지스트 120 : 회로 패턴 110: solder resist 120: circuit pattern

130 : 반도체 칩 132 : 본딩 패드130: semiconductor chip 132: bonding pad

134 : 범프 140 : 충진재134: bump 140: filler

150 : 솔더볼150 solder ball

본 발명은 반도체 패키지에 관한 것으로서, 보다 상세하게는, 경박단소하고 전기적인 특성이 우수한 박형 플립 칩 패키지 및 이의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a thin flip chip package excellent in light and simple electrical characteristics and a method of manufacturing the same.

전기·전자 제품이 고성능화되고 전자기기들이 경박단소화됨에 따라 핵심 소 자인 패키지의 박형화, 고밀도, 고실장화가 중요한 문제로 대두되고 있다. As electrical and electronic products become more efficient and electronic devices become thinner and shorter, the thinner, higher density, and higher mounting of core packages are becoming important issues.

현재, 컴퓨터, 노트북, 모바일폰 등의 경우 기억 용량의 증가에 따라 대용량의 램(Random Access Memory) 및 플래쉬 메모리(Flash Memory)와 같이 칩의 용량은 증대되지만, 패키지는 소형화되는 경향으로 연구되고 있으며, 이를 실현하기 위하여 핵심 부품으로 사용되는 패키지의 크기는 자연적으로 소형화되는 경향으로 연구되고 있고, 한정된 크기의 기판에 더 많은 수의 패키지를 실장하기 위한 여러 가지 기술들이 제안·연구되고 있다. Currently, in the case of computers, laptops, mobile phones, etc., as the memory capacity increases, the chip capacity increases, such as a large amount of random access memory (RAM) and flash memory (Flash memory), but the package is being miniaturized. In order to realize this, the size of a package used as a core component is naturally tended to be miniaturized, and various techniques for mounting a larger number of packages on a limited size substrate have been proposed and studied.

이러한 패키지의 크기를 줄이기 위한 방법으로, 동일한 기억 용량의 칩을 사용하면서 패키지의 크기 및 두께를 최소화할 수 있는 기술이 제안된 바 있으며, 이는 통상 플립 칩 패키지(Flip Chip Package)라 통칭된다. As a method for reducing the size of such a package, a technique for minimizing the size and thickness of the package while using chips having the same storage capacity has been proposed, which is commonly referred to as a flip chip package.

플립 칩 패키지는 고밀도 패키징이 가능한 본딩 프로세스로 반도체 칩 내부 회로에서 본딩 패드의 위치를 필요에 따라 결정할 수 있으므로 회로 설계를 단순화시키고, 회로선에 의한 저항을 감소시켜 소요 전력을 줄일 수 있으며, 전기적 신호의 경로가 짧아져 반도체 패키지의 동작 속도를 향상시킬 수 있어 전기적 특성이 우수하고, 반도체 칩의 배면이 외부로 노출되어 있어 열적 특성이 우수하며, 작은 형태의 패키지를 구현할 수 있고, 솔더 자기정렬(Self-Alignment) 특성 때문에 본딩이 용이한 잇점이 있다.The flip chip package is a high-density packaging bonding process that can determine the location of the bonding pads in the circuitry inside the semiconductor chip as needed, simplifying circuit design, reducing resistance by circuit lines, and reducing power consumption. The shorter path of the semiconductor package can improve the operation speed of the semiconductor package, so the electrical characteristics are excellent, and the backside of the semiconductor chip is exposed to the outside, so the thermal characteristics are excellent, and a small package can be realized. Self-Alignment) has the advantage of easy bonding.

그러나, 전술된 바와 같은 플립 칩 패키지의 우수한 특성에도 불구하고 상기 플립 칩 패키지의 크기를 줄이기 위한 요구가 증대되고 있으며, 이에 따라, 플립 칩 패키지의 특성을 그대로 유지하면서 그 크기를 줄인, 소위, 박형 플립 칩 패키 지가 제안되었다.However, in spite of the excellent characteristics of the flip chip package as described above, there is an increasing demand for reducing the size of the flip chip package. Flip chip packages have been proposed.

박형 플립 칩 패키지는 종래 플립 칩 패키지의 구성물 중에서 반도체 칩의 두께를 줄이고, 반도체 칩을 외부로부터 보호하기 위하여 봉지하는 봉지부의 두께를 조절하며, 솔더볼의 크기를 조절하는 등 패키지의 제조 과정 중 조절 가능한 여러 가지 구성 변수들을 변경하여 박형의 플립 칩 패키징된 구조를 갖도록 구성되어 있다.The thin flip chip package is adjustable in the manufacturing process of the package, such as reducing the thickness of the semiconductor chip among the components of the conventional flip chip package, adjusting the thickness of the encapsulation part to protect the semiconductor chip from the outside, and adjusting the size of the solder balls. Various configuration variables are modified to have a thin flip chip packaged structure.

도 1은 종래 기술에 따른 박형 플립 칩 패키지를 도시한 단면도이다.1 is a cross-sectional view showing a thin flip chip package according to the prior art.

도시된 바와 같이, 반도체 칩(20)은 상부면에 본딩 패드(22)가 구비되어 있고, 본딩 패드(22) 상에는 외부와 전기적인 신호를 교환하는 전기 도선으로 범프(24)가 형성되어 있다. 그리고, 반도체 칩(20)과 전자기기 사이의 신호전달을 위한 매개체로 사용되는 기판(10)은 코아 물질(18)과 그의 상/하부에 형성된 회로 패턴(14, 15, 16, 17)들 및 회로 패턴(14, 15, 16, 17)과 코아 물질(18)의 상/하부에 도포되고 회로 패턴(14, 15, 16, 17)들 중 상기 반도체 칩(20)의 범프(24)와 전기적 연결을 이루는 부분을 제외한 나머지 부분을 외부와 절연시키고 산화되는 것을 방지하는 패터닝된 솔더 레지스트(11, 12)로 구성되어 있다. 또한, 반도체 칩(20)과 기판(10) 사이에는 충진재(30)가 형성되어 있고, 기판(10)의 하부면에 구비된 솔더볼랜드(15)에 솔더볼(40)이 부착되어 있다. As illustrated, the semiconductor chip 20 is provided with a bonding pad 22 on an upper surface thereof, and a bump 24 is formed on the bonding pad 22 by electrical wires that exchange electrical signals with the outside. In addition, the substrate 10 used as a medium for signal transmission between the semiconductor chip 20 and the electronic device includes the core material 18 and circuit patterns 14, 15, 16, and 17 formed on and under the core material 18. The circuit patterns 14, 15, 16, 17 and the core material 18 are applied to the upper and lower parts of the circuit patterns 14, 15, 16, and 17 and electrically connected to the bumps 24 of the semiconductor chip 20. It is composed of patterned solder resists 11 and 12 that insulate the rest of the body except the connecting part from the outside and prevent oxidation. In addition, a filler 30 is formed between the semiconductor chip 20 and the substrate 10, and the solder balls 40 are attached to the solder ball lands 15 provided on the lower surface of the substrate 10.

여기서, 상기 반도체 칩(20)은 기판(10)에 플립 칩 본딩되어 있고, 반도체 칩(20)의 본딩 패드(22)에 형성되어 있는 범프(24)와 기판(10)의 상부면에 형성되어 있는 범프 랜드(14)는 일대일 대응으로 개별 콘택하여 전기적으로 연결되어 있 다.Here, the semiconductor chip 20 is flip chip bonded to the substrate 10, and is formed on the bump 24 formed on the bonding pad 22 of the semiconductor chip 20 and the upper surface of the substrate 10. The bump lands 14 are electrically connected by individual contacts in a one-to-one correspondence.

그리고, 도시하지는 않았지만, 상기 반도체 칩(20)을 포함하여 기판(10)의 상부면을 봉지하는 봉지부를 형성시켜 박형 플립 칩 패키지를 제조할 수도 있다.Although not shown, a thin flip chip package may be manufactured by forming an encapsulation part including the semiconductor chip 20 to encapsulate the upper surface of the substrate 10.

그러나, 이와 같은 종래의 박형 플립 칩 패키지에서, 패키지의 두께를 줄이기 위하여 반도체 칩의 두께를 추가적으로 축소시키는 방법과 그 외 패키지의 다른 구성 요소의 두께 및 크기를 줄이는 방법등 패키지의 구성 변수를 조절하여 패키지의 두께를 줄이는 것은 공정 장비 및 기술적인 문제로 한계를 가짐에 따라 경박단소한 박형 플립 칩 패키지를 제조하기 어려운 문제점들이 있다.However, in such a conventional thin flip chip package, in order to reduce the thickness of the package, by adjusting the configuration variables of the package, such as further reducing the thickness of the semiconductor chip and other methods of reducing the thickness and size of the other components of the package Reducing the thickness of packages has limitations due to process equipment and technical problems, making it difficult to manufacture thin and thin flip chip packages.

본 발명은 상기와 같은 종래의 제반 문제점들을 해결하기 위해 안출된 것으로서, 경박단소하고 전기적인 특성이 우수한 박형 플립 칩 패키지를 제공함에 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above-mentioned general problems, and an object thereof is to provide a thin flip chip package which is light and simple and has excellent electrical characteristics.

상기의 목적을 달성하기 위하여, 본 발명은, 회로 패턴과 상기 회로 패턴의 일부분을 노출시키도록 형성된 솔더 레지스트를 포함하는 기판; 상기 기판의 노출된 회로 패턴 부분의 상면에 범프를 매개로 플립 칩 본딩된 반도체 칩; 상기 반도체 칩과 기판 사이에 형성된 충진재; 및 상기 노출된 회로 패턴 부분의 하면에 부착된 솔더볼;을 제공한다.In order to achieve the above object, the present invention, a substrate comprising a circuit pattern and a solder resist formed to expose a portion of the circuit pattern; A semiconductor chip flip-chip bonded to the upper surface of the exposed circuit pattern portion of the substrate via bumps; A filler formed between the semiconductor chip and the substrate; And a solder ball attached to a lower surface of the exposed circuit pattern portion.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명 하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 실시예에 따른 박형 플립 칩 패키지를 도시한 단면도이다. 2 is a cross-sectional view illustrating a thin flip chip package according to an embodiment of the present invention.

도시된 바와 같이, 기판은 상부면에 구비된 회로 패턴(120)과 그의 일부분들이 노출되도록 도포 및 패터닝된 솔더 레지스트(110)를 포함하여 구성되어 있다. 그리고, 상기 기판상에 패터닝된 솔더 레지스트(110)로 노출된 회로 패턴(120) 부분들의 상면에 다수의 범프(134)가 형성되어 있는 본딩 패드(132)들을 구비한 반도체 칩(130)이 플립 칩 본딩되어 있다. 또한, 상기 반도체 칩(130)과 기판 사이에는 반도체 칩(130)을 지지하고 범프(134)들과 이들과 부착된 접합부를 보호하기 위하여 충진재(140)가 형성되어 있고, 상기 노출된 회로 패턴(120) 부분의 하면에는 외부와 전기적 연결을 이루는 솔더볼(150)이 부착되어 있다.As shown, the substrate includes a circuit pattern 120 provided on the top surface and a solder resist 110 coated and patterned to expose portions thereof. In addition, the semiconductor chip 130 having the bonding pads 132 having a plurality of bumps 134 formed on the upper surface of portions of the circuit pattern 120 exposed by the patterned solder resist 110 on the substrate is flipped. Chip bonded. In addition, a filler 140 is formed between the semiconductor chip 130 and the substrate to support the semiconductor chip 130 and to protect the bumps 134 and the bonding portion attached thereto, and the exposed circuit pattern ( The lower surface of the 120 is attached to the solder ball 150 making an electrical connection with the outside.

여기서, 반도체 칩(130)의 본딩 패드(132)에 형성되어 있는 범프(134)와 기판의 상면에 형성되어 있는 노출된 회로 패턴(120)들은 일대일 대응으로 개별 콘택되어 전기적인 연결을 형성하고 있다.Here, the bumps 134 formed on the bonding pads 132 of the semiconductor chip 130 and the exposed circuit patterns 120 formed on the upper surface of the substrate are individually contacted in a one-to-one correspondence to form electrical connections. .

본 발명에서는, 종래 플립 칩 패키지와 달리 회로 패턴을 형성하기 위하여 기본 물질로 사용되는 코아 물질과 그의 하부면에 형성되어 있는 솔더볼랜드 및 회로 패턴들을 제거하고, 외부와의 전기적인 연결을 형성하는 솔더볼을 회로 패턴의 하면에 부착시킴으로써 플립 칩 패키지의 크기를 줄일 수 있다.In the present invention, unlike the conventional flip chip package, the solder ball to remove the core material used as a base material and the solder ball land and circuit patterns formed on the lower surface thereof to form a circuit pattern, and to form an electrical connection with the outside By attaching to the lower surface of the circuit pattern can reduce the size of the flip chip package.

이하에서는 본 발명의 실시예에 따른 박형 패키지의 제조 방법을 도 3a 내지 도 3f를 참조하여 설명하도록 한다.Hereinafter, a method of manufacturing a thin package according to an embodiment of the present invention will be described with reference to FIGS. 3A to 3F.

도 3a에 도시된 바와 같이, 우선, 기판(200)을 구성하는 코아 물질(100)의 상면에 형성되어 있는 회로 패턴(120)들을 외부와 절연시키고, 회로 패턴(120)들이 산화되는 것을 방지하기 위하여 솔더 레지스트(110)를 코아 물질(100) 상에 도포하고, 일부분의 회로 패턴(이하 "범프 랜드"라고함 : 120)들이 노출되도록 패터닝한다.As shown in FIG. 3A, first, the circuit patterns 120 formed on the upper surface of the core material 100 constituting the substrate 200 are insulated from the outside, and the circuit patterns 120 are prevented from being oxidized. The solder resist 110 is applied onto the core material 100 and patterned to expose a portion of the circuit pattern (hereinafter referred to as "bump land") 120.

그런 다음, 도 3b에 도시된 바와 같이, 웨이퍼 레벨 단계에서 각 본딩 패드(132) 상에 형성된 다수의 범프(134)가 구비한 반도체 칩(130)들을 포함하는 웨이퍼를 쏘잉(Sawing) 하여 개별 반도체 칩(130)으로 분리시킨다. Then, as illustrated in FIG. 3B, at the wafer level step, the wafer including the semiconductor chips 130 provided with the plurality of bumps 134 formed on each bonding pad 132 is sawed to separate semiconductors. The chip 130 is separated.

이후, 도 3c에 도시된 바와 같이, 상기 다수의 본딩 패드(132)에 범프(134)들이 구비된 반도체 칩(130)을 기판(200) 상에 페이스 다운(Face-Down) 타입으로 플립 칩 본딩시킨다. 이때, 반도체 칩(130)의 본딩 패드(132) 상에 형성되어 있는 범프(134)와 기판(200)의 범프 랜드(120)는 일대일 대응으로 개별 콘택되어 전기적으로 연결된다.Afterwards, as illustrated in FIG. 3C, the semiconductor chip 130 including the bumps 134 in the plurality of bonding pads 132 is flip-chip bonded to the face-down type on the substrate 200. Let's do it. In this case, the bump 134 formed on the bonding pad 132 of the semiconductor chip 130 and the bump land 120 of the substrate 200 are individually contacted and electrically connected in a one-to-one correspondence.

이어서, 도 3d에 도시된 바와 같이, 범프(134)를 포함하여 범프(134)와 부착되어 있는 기판(200)의 범프 랜드(120)와 반도체 칩(130)의 본딩 패드(132)의 접합부를 보호하기 위하여 반도체 칩(130)과 기판(200) 사이에 충진재(140)를 형성시킨다.Subsequently, as illustrated in FIG. 3D, the junction between the bump land 120 of the substrate 200 and the bonding pad 132 of the semiconductor chip 130 including the bump 134 is attached to the bump 134. In order to protect the filler 140, a filler 140 is formed between the semiconductor chip 130 and the substrate 200.

여기서, 충진재(140)는 일반적으로 에폭시 레진(Epoxy Resin) 복합체로 이루어진 액상 물질을 반도체 칩(130)과 기판(100) 사이에 모세관 현상을 이용하여 주입하고 경화 공정을 진행하여 형성시킨다.Here, the filler 140 is generally formed by injecting a liquid material composed of an epoxy resin (Epoxy Resin) composite between the semiconductor chip 130 and the substrate 100 by using a capillary phenomenon and proceeding the curing process.

그런 다음, 도 3e에 도시된 바와 같이, 패키지의 두께를 축소시키기 위하여 기판(미도시)을 구성하는 코아 물질(미도시)을 제거한다. Then, as shown in FIG. 3E, the core material (not shown) constituting the substrate (not shown) is removed to reduce the thickness of the package.

여기서, 상기 코아 물질(미도시)은 물리적인 방법인 기계를 사용한 그라인딩(Grinding)이나 폴리싱(Polishing) 등으로 제거되거나, 또는 화학적인 방법인 습식 식각등으로 제거된다.Here, the core material (not shown) may be removed by grinding or polishing using a mechanical method, or by wet etching using a chemical method.

마지막으로, 도 3f에 도시된 바와 같이, 외부와의 전기적인 연결을 이루는 솔더볼(150)을 기판(미도시)의 범프 랜드(120) 하면에 형성시켜 반도체 칩(130)의 본딩 패드(132) 상에 형성된 범프(134)와 전기적으로 연결시킴으로써 박형 플립 칩 패키지를 완성한다.Finally, as illustrated in FIG. 3F, solder balls 150, which form an electrical connection with the outside, are formed on the bottom surface of the bump land 120 of the substrate (not shown) to bond the pads 132 of the semiconductor chip 130. The thin flip chip package is completed by electrically connecting with bumps 134 formed thereon.

이후, 도시하지는 않았지만, 경우에 따라 상기 반도체 칩을 포함하여 기판의 상부면에 봉지부를 형성시킬 수도 있다.Subsequently, although not shown, an encapsulation portion may be formed on the upper surface of the substrate including the semiconductor chip in some cases.

본 발명에 따르면, 박형 플립 칩 패키지를 구성하기 위하여 패키지의 크기를 줄일 수 있는 패키지의 구성 변수 중 기판을 구성하는 코아 물질을 제거하고 기판 상의 범프 랜드에 외부와의 전기적인 연결을 이루는 솔더볼을 부착시킴으로써 경박단소하고 전기적인 특성이 우수한 박형 플립 칩 패키지 제조할 수 있다.According to the present invention, in order to construct a thin flip chip package, core material constituting the substrate is removed from the configuration variables of the package that can reduce the size of the package, and a solder ball forming electrical connection with the outside is attached to the bump land on the substrate. By doing so, it is possible to manufacture a thin flip chip package which is light and thin and has excellent electrical characteristics.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명에서는 회로 패턴을 형성하기 위하여 지지대 역할 을 하는 물질로 사용하고 있는 코아 물질과 그의 하부면에 형성되는 솔더볼랜드 및 회로 패턴을 제거하고, 외부와의 전기적인 연결을 위하여 솔더볼을 기판의 범프 랜드 하면에 부착시킴으로써 경박단소한 박형 플립 칩 패키지를 제공할 수 있다. As described above, in the present invention, the core material and the solder ball land and the circuit pattern formed on the lower surface of the core material used as a support to form a circuit pattern is removed, and the solder ball for the electrical connection to the outside By attaching to the bump land lower surface of the substrate can be provided a thin and thin flip chip package.

그리고, 전기적인 패스의 경로가 단축됨으로써 전기적인 특성이 우수한 박형 플립 칩 패키지를 제공할 수 있다. The short path of the electrical path can provide a thin flip chip package having excellent electrical characteristics.

Claims (3)

코아 물질이 제거되어 있고, 상부의 회로 패턴과 상기 회로 패턴의 일부분을 노출시키도록 형성된 솔더 레지스트를 포함하는 기판;A substrate, the core material being removed, the substrate comprising a solder resist formed to expose a circuit pattern thereon and a portion of the circuit pattern; 상기 기판의 노출된 회로 패턴 부분의 상면에 범프를 매개로 플립 칩 본딩된 반도체 칩;A semiconductor chip flip-chip bonded to the upper surface of the exposed circuit pattern portion of the substrate via bumps; 상기 반도체 칩과 기판 사이에 형성된 충진재; 및A filler formed between the semiconductor chip and the substrate; And 상기 노출된 회로 패턴 부분의 하면에 부착된 솔더볼;A solder ball attached to a lower surface of the exposed circuit pattern portion; 을 포함하는 것을 특징으로 하는 박형 플립 칩 패키지.Thin flip chip package comprising a. 코아 물질과 그 상부에 형성된 회로 패턴으로 구성되고, 상기 코아 물질과 회로 패턴 상에 솔더 레지스트를 도포 및 패터닝하여 상기 회로 패턴의 일부분을 노출시킨 기판을 준비하는 단계;Preparing a substrate comprising a core material and a circuit pattern formed thereon, wherein the substrate is exposed and patterned with a solder resist on the core material and the circuit pattern to expose a portion of the circuit pattern; 상기 기판의 노출된 회로 패턴의 상면에 범프가 형성되어 있는 본딩 패드를 구비한 반도체 칩을 플립 칩 본딩 시키는 단계;Flip chip bonding a semiconductor chip having a bonding pad having bumps formed on an upper surface of an exposed circuit pattern of the substrate; 상기 반도체 칩과 기판 사이에 충진재를 형성시키는 단계;Forming a filler between the semiconductor chip and the substrate; 상기 기판을 구성하는 코아 물질을 제거하는 단계; 및Removing core material constituting the substrate; And 상기 기판의 노출된 회로 패턴의 하면에 솔더볼을 부착시키는 단계; Attaching a solder ball to a bottom surface of an exposed circuit pattern of the substrate; 를 포함하는 것을 특징으로 하는 박형 플립 칩 패키지의 제조 방법.Method of manufacturing a thin flip chip package comprising a. 제 2 항에 있어서,The method of claim 2, 상기 기판의 코아 물질은 그라인딩(Grinding)이나 폴리싱(Polishing) 또는 습식 식각하는 방법으로 제거되는 것을 특징으로 하는 박형 플립 칩 패키지의 제조 방법.The core material of the substrate is a method of manufacturing a thin flip chip package, characterized in that the removal by grinding (Polishing) or wet etching (Polishing) method.
KR1020060095100A 2006-09-28 2006-09-28 Thin flip chip package and manufacturing process of the same KR20080029275A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100881024B1 (en) * 2007-08-10 2009-02-05 에스티에스반도체통신 주식회사 A chip scale package having a improved rf characteristics and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100881024B1 (en) * 2007-08-10 2009-02-05 에스티에스반도체통신 주식회사 A chip scale package having a improved rf characteristics and manufacturing method thereof

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