KR20080020938A - Method for fabricating semiconductor devise - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to stably form a bottom surface of a contact plug on an upper surface of a silicide layer or to stably form a contact plug within a contact hole formed inside the silicide layer. A first and second transistor regions are defined on a semiconductor substrate(100). A gate electrode having a first silicide layer(127a) and a first transistor having a first conductive type source/drain region, a gate electrode having a second silicide layer(127b), and a second transistor having a second conductive type source/drain region are formed in the first and second transistor regions. A first and second stress layers are formed in the first and second transistor regions, respectively. The first and second stress layers are overlapped on a third silicide layer(127c) formed in a boundary between the first and second transistor regions. The second stress layer is removed from the third silicide layer. An interlayer dielectric is formed on the semiconductor substrate. A contact hole is formed in the interlayer dielectric. A contact plug is formed to bury the contact hole.

Description

Method for fabricating semiconductor devise

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a stable structure contact and a method of manufacturing the same.

In general, various methods for forming transistors having better performances have been studied while overcoming the limitations of MOSFETs having high integration and speed. In particular, many methods for increasing the mobility of electrons or holes have been developed to implement high-performance transistors.

As a method of increasing the mobility of electrons or holes, there is a method of changing the energy band structure of the channel region by applying physical stress to the channel region. For example, NMOS transistors improve performance when a tensile stress is applied to a channel, and PMOS transistors perform when compressive stress is applied to a channel.

Accordingly, since a tensile stress film is formed on the NMOS transistor and a compressive stress film is formed on the PMOS transistor, the performance of both the NMOS transistor and the PMOS transistor can be improved at the same time. It is preferable to use a stress layer.

1 is a cross-sectional view of a semiconductor device having a dual stress film according to the prior art. Referring to FIG. 1, in the first transistor region I, for example, an NMOS transistor region, a tensile stress film 31 and an etch stop layer 33 covering an NMOS transistor are positioned, and a second transistor region II, For example, the compressive stress film 35 covering the PMOS transistor is located in the PMOS transistor region.

However, in the boundary portion II between the NMOS transistor region I and the PMOS transistor region II, there is a region where the tensile stress film 31, the etch stop film 33, and the compressive stress film 35 overlap each other. This may occur in regions where the photoresist patterns overlap due to process margins in the etching process for forming the respective stress films. As shown in the drawing, the boundary portion II is positioned in the device isolation region 11 and the gate electrode 25c may be positioned on the boundary portion II. In addition, although not shown, the boundary portion II may be located in the active region and may include a predetermined gate line and / or a source / drain region.

Typically, contact resistances are lowered on the upper surfaces of the gate electrodes 25a, 25b, 25c and the source / drain regions 21a, 21b, which are provided in the NMOS transistor region I, the PMOS transistor region II, and the boundary portion II. Silicide films 27a, 27b, and 27c are provided as ohmic films, and the silicide films 27a, 27b, and 27c are formed by capacitors, bit lines, or the like by contacts 61, 63, and 65 formed in the interlayer insulating film 40. It is electrically connected to wiring and the like.

In order to form the contact of the device having the dual stress film shown in Figure 1 it is necessary to form a contact hole to expose the silicide film through each stress film. However, a single stress film exists in the NMOS transistor region I and the PMOS transistor region II, whereas the boundary portion II has a laminated film structure in which the respective stress films overlap. In this case, when the contact holes 51, 53, and 55 are simultaneously formed in all regions, the etching end point is aligned with the silicide layer 27c of the boundary portion II, and the upper surface of the silicide layer 27c is formed at the boundary portion II where the laminated layer is formed. While it can be stably exposed, transient etching occurs in the NMOS transistor region I and the PMOS transistor region II having a single stress film, so that the silicide films 27a and 27b are lost and the contact holes 51 and 53 are removed. Source / drain regions 21a and 21b and gate electrodes 25a and 25b may be exposed on the bottom surface. Therefore, even if the contact hole 51 is stably formed in the boundary portion III without losing the silicide film 27c, this is not the case in the NMOS transistor region I and the PMOS transistor region II. In this case, the reliability and characteristics of the semiconductor device may be degraded, such as an increase in contact resistance.

On the contrary, although not illustrated in a separate drawing, if the etching end point is aligned with the top surface of the silicide film of the NMOS and PMOS transistor regions I and II, the contact hole formed in the boundary portion III does not penetrate the laminated film. . Therefore, since the electrical signal cannot be transmitted at the boundary, the reliability and characteristics of the semiconductor device may be degraded.

An object of the present invention is to provide a method for manufacturing a semiconductor device having a stable contact and formed on the silicide layer to improve the reliability and characteristics.

The technical problem to be achieved by the present invention is not limited to the above-mentioned problem, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including a gate electrode having a first transistor region and a second transistor region, the first electrode layer having a first silicide layer formed thereon; A first transistor including a first conductivity type source / drain region, a gate electrode having a second silicide layer formed thereon, and a second transistor including a second conductivity type source / drain region, respectively, include the first transistor region and the second transistor. A third stress film formed in each of the regions, a first stress film formed in the first transistor region, and a second stress film formed sequentially in the second transistor region, and provided in a boundary portion between the first transistor region and the second transistor region. The first stress film and the second stress film are sequentially stacked on the silicide film, and the third silicide Removing the second stress film superimposed on the passivation layer, forming an interlayer insulating film on the entire surface of the semiconductor substrate, and penetrating the interlayer insulating film, and having a bottom surface of the first to third silicide films or in contact therewith; And forming a contact plug to fill the contact hole.

Specific details of other embodiments are included in the detailed description and the drawings.

As described above, according to the exemplary embodiments of the present invention, the contact plug may be stably formed in the contact hole having the bottom surface of the silicide layer. Therefore, the characteristics and the reliability of the semiconductor device can be further improved.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims.

Thus, in some embodiments, well known process steps, well known structures and well known techniques are not described in detail in order to avoid obscuring the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, including and / or comprising includes the presence or addition of one or more other components, steps, operations and / or elements other than the components, steps, operations and / or elements mentioned. Use in the sense that does not exclude. And “and / or” includes each and all combinations of one or more of the items mentioned. In addition, like reference numerals refer to like elements throughout the following specification.

In addition, the embodiments described herein will be described with reference to cross-sectional and / or schematic views, which are ideal illustrations of the invention. Accordingly, shapes of the exemplary views may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. In addition, each component in each drawing shown in the present invention may be shown to be somewhat enlarged or reduced in view of the convenience of description.

In the following description, an NMOS transistor is used as the first transistor, a PMOS transistor is used as the second transistor, a tensile stress film is used as the first stress film, and a compressive stress film is used as the second stress film, respectively, but the present invention is not limited thereto. no. That is, the type of the conductive type and the stress film of the transistor may not only be applied inversely to each other but also may be of the same type.

Hereinafter, a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 2.

Referring to FIG. 2, the semiconductor device according to the embodiment includes a semiconductor substrate 100 having an NMOS transistor region I and a PMOS transistor region II. A predetermined boundary III exists between the NMOS transistor region I and the PMOS transistor region II.

In the semiconductor substrate 100, an active region is defined by an isolation region 111. As the substrate 100, a substrate made of at least one semiconductor material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP, a silicon on insulator (SOI) substrate, or the like may be used. This is merely illustrative. Although not shown in the drawings, if necessary, a P type well may be formed in the semiconductor substrate 100 of the NMOS transistor region I and an N type well may be formed in the semiconductor substrate 100 of the PMOS transistor region II. have.

The NMOS transistor located in the NMOS transistor region I is formed on the gate electrode 125a formed on the gate insulating film 123 and the source / drain region 121a formed on both substrates of the gate electrode 125a and doped with N-type impurities. ). The gate electrode 125a may be, for example, a single film such as a polysilicon film, a metal film, or a stacked film thereof. In this case, the polysilicon film may be polysilicon doped with N-type impurities, but is not limited thereto. The polysilicon film may have the same conductivity type as the gate electrode 125b of the PMOS transistor to be described later.

The spacer 129 may be positioned on the sidewall of the gate electrode 125a, and the first silicide layer 127a may be formed on the gate electrode 125a and the source / drain region 121a. The metal component of the first silicide layer 127a may be, for example, Co, Ni, Ti, Ta, W, or the like, but is not limited thereto.

On the other hand, the PMOS transistor located in the PMOS transistor region II is a gate electrode 125b formed on the gate insulating film 123 and a source / drain region formed in both substrates of the gate electrode 125b and doped with P-type impurities. (121b). The gate electrode 125b may be, for example, a single film such as a polysilicon film, a metal film, or a stacked film thereof. In this case, the polysilicon film may be polysilicon doped with P-type impurities, but is not limited thereto. The gate electrode 125a of the NMOS transistor and the gate electrode 125b of the PMOS transistor are preferably of different conductivity types, but embodiments of the present invention do not exclude the case where both gate electrodes are of the same conductivity type.

The spacer 129 is positioned on the sidewall of the gate electrode 125b, and the second silicide layer 127b is formed on the gate electrode 125b and the source / drain region 121b. The metal component of the second silicide layer 127b may be Co, Ni, Ti, Ta, W, or the like, but is not limited thereto.

In the boundary portion III positioned between the NMOS transistor region I and the PMOS transistor region II, a predetermined gate electrode 125c having a third silicide layer 127c may be present on an upper surface thereof. As shown in FIG. 2, the gate electrode 125c may be positioned on the isolation region 111, but is not limited thereto. The gate electrode 125c may also be disposed on the active region. Although not shown in the drawings, a predetermined source / drain region having a silicide film may be disposed on the boundary portion III.

In the NMOS transistor region I, a tensile stress film 131 capable of applying tensile stress to a channel region of the NMOS transistor is located. The tensile stress film 131 may increase the mobility of the carrier by applying a tensile stress to the channel region of the NMOS transistor.

As the tensile stress film 131, for example, SiN, SiON, SiC, SiCN, SiO 2 or a combination thereof may be used, but is not limited thereto. In addition, the thickness of the tensile stress film 131 may be appropriately adjusted within a thickness of about 50 ~ 1000Å.

An etch stop layer 133 may be further disposed on the tensile stress layer 131. As the etch stop layer 133, for example, a low temperature oxide (LTO) film may be used, but is not limited thereto. The etch stop layer 133 is a tensile stress film 131 or a compressive stress film 135 in accordance with the manufacturing process, such as forming a tensile stress film 133 first in the manufacturing process, or first to form a compressive stress film 135 to be described later May be selectively positioned on the

In the PMOS transistor region II, a compressive stress film 135 capable of applying compressive stress to the channel region is located on the PMOS transistor. The compressive stress film 135 may increase carrier mobility by applying compressive stress to the channel region of the PMOS transistor.

As the compressive stress film 135, for example, SiN, SiON, SiC, SiCN, SiO 2 or a combination thereof may be used, but is not limited thereto. In addition, the thickness of the compressive stress film 135 may be appropriately adjusted within a thickness of about 50 ~ 1000Å.

A tensile stress film 131, an etch stop film 133, and a compressive stress film 135 may coexist at the boundary portion III. That is, the tensile stress film 131, the etch stop film 133, and the compressive stress film 135 extend to the boundary portion. In one embodiment of the present invention, a tensile stress film 131 is present on the third silicide film 127c positioned at the boundary portion III.

An interlayer insulating layer 140 covering the entire surface of the substrate is disposed on the NMOS transistor region I, the PMOS transistor region II, and the boundary portion III. First to third contact holes 151, 153, and 155 penetrate the interlayer insulating layer 140.

In detail, the first contact hole 151 is positioned in the NMOS transistor region I. The first contact hole 151 is formed through the interlayer insulating layer 140, the etch stop layer 133, and the tensile stress layer 131. 1 is located on or inside the silicide film 127a. In addition, the second contact hole 153 is positioned in the PMOS transistor region II, and is formed through the interlayer insulating layer 140 and the compressive stress layer 135, and a bottom surface thereof is formed on the top surface of the second silicide layer 127b. Or located inside. The third contact hole 155 is positioned on the boundary portion III, and is formed through the interlayer insulating layer 140, the etch stop layer 133, and the tensile stress layer 131, and a bottom surface thereof is formed through the third silicide layer ( It is located on or inside the upper surface of 127c).

The contact plugs 161, 163, and 165, which are conductive materials, are formed in the first to third contact holes 151, 153, and 155. The bottom surfaces of the contact plugs 161, 163, and 165 may be located on or in the upper surface of any one of the first to third silicide layers 127c.

The contact plugs 161, 163, and 165 may be filled with a metal material such as W, Cu, or Al, or a conductive material such as conductive polysilicon. Although not shown in the drawings, a barrier layer (not shown) may be further provided along the inside of each of the contact holes 151, 153, and 155 before filling with the conductive material. The barrier layer may include an ohmic layer to improve contactability of the metal layer embedded in the contact holes 151, 153, and 155, and a diffusion barrier to prevent the metal material from diffusing and reacting with the silicon. For example, the ohmic layer may be formed by conformally depositing a high melting point metal (refractory metal) such as Ti or Ta along the contact hole, and the diffusion barrier layer may be formed of TiN or TaN along the surface of the ohmic layer. .

As described above, in the semiconductor device according to the exemplary embodiment of the present invention, the silicide layer positioned at the bottom of each contact hole is not exhausted or punched through, and the bottom surface of the contact plug is in contact with the top surface or the inside of the silicide layer. It is formed to. Therefore, the reliability and characteristics of the semiconductor device can be improved.

Hereinafter, a method of manufacturing the semiconductor device shown in FIG. 2 will be described with reference to FIGS. 3 to 13. 3 to 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. Since the descriptions of materials, dimensions, and the like for each component in the semiconductor device described above apply equally to the manufacturing method, the following description will be omitted or briefly described in order to avoid duplication of description. In addition, the process that can be formed according to the process steps that are well known to those skilled in the art in the following description of the manufacturing method will be outlined in order to avoid being ambiguously interpreted.

First, referring to FIG. 3, a semiconductor substrate 100 including an NMOS transistor region I and a PMOS transistor region II is provided. At this time, the boundary III is located between the NMOS transistor region I and the PMOS transistor region II.

In more detail, first, a device isolation region 111 is formed by performing a local oxide of silicon (LOCOS) process or a shallow trench isolation (STI) process on a predetermined region of the semiconductor substrate 100.

Although not shown in the drawings, a well region may be formed in the NMOS transistor region I and / or the PMOS transistor region II. For example, when a P-type substrate is used, n-well may be formed by implanting n-type impurities into the PMOS transistor region II, and p-well may be formed by implanting p-type impurities into the NMOS transistor region I. Can be formed.

In the drawing, the boundary portion III is illustrated as being formed in the device isolation region 111, but is not limited thereto, and may be formed in the active region.

4, an NMOS transistor and a PMOS transistor are formed in the NMOS transistor region I and the PMOS transistor region II, respectively. In this case, the gate electrode 125c may be formed at the boundary portion III.

The NMOS transistor includes a gate electrode 125a and an N-type source / drain region 121a and a first silicide layer 127a thereon. In addition, the PMOS transistor includes a gate electrode 125b and a P-type source / drain region 121b and includes a second silicide layer 127b thereon. First to third silicide layers 127a, 127b, and 127c are formed on the gate electrode and the source / drain regions provided in the NMOS transistor region I, the PMOS transistor region II, and the boundary portion III.

Specifically, first, the gate insulating film and the conductive film for the gate electrode are formed and patterned on the entire surface of the semiconductor substrate 100 to form the gate electrodes 125a, 125b, and 125c. In this case, the gate insulating layer 123 may be formed of a silicon oxide film, but is not limited thereto. The gate insulating film 123 may be formed of a high dielectric constant film having a higher dielectric constant than that of the silicon oxide film. The gate electrodes 125a, 125b, and 125c may be formed of a single film or a stacked film of a polysilicon film or a metal film doped with impurities of the same or different conductivity types.

Then, a photoresist pattern exposing the NMOS transistor region I is formed, and n-type impurities are implanted into both sides of the gate electrode 125a to form the N-type source / drain region 121a. Thereafter, the photoresist pattern exposing the NMOS transistor region I is removed, and a photoresist pattern exposing the PMOS transistor region II is formed to form a P-type on both sides of the gate electrode 125b of the PMOS transistor region II. Source / drain regions 121b are formed. The N-type and P-type source / drain regions 121a and 121b formed as described above may be formed of a double diffused drain (DDD) or a lightly doped drain (LDD) structure. In this way, NMOS and PMOS transistors are completed. Reference numeral 129 not described refers to an insulating spacer.

Subsequently, a silicide metal film is deposited on the entire surface of the semiconductor substrate 100 on which the NMOS and PMOS transistors are formed, and then heat-treated to form a first layer on the gate electrodes 125a, 125b and 125c and the source / drain regions 121a and 121b. To third silicide layers 127a, 127b, and 127c, respectively.

Next, referring to FIGS. 5 and 8, a tensile stress film covering the NMOS transistor is formed in the NMOS transistor region, and a compressive stress film covering the PMOS transistor is formed in the PMOS transistor region, respectively.

Specifically, first, as shown in FIG. 5, the tensile stress film 131a is formed in each region by using chemical vapor deposition (CVD), for example, thermal CVD, PECVD, high density plasma CVD, and the like. The thickness and material of the tensile stress film 131a are as described above with reference to FIG. 2. For example, in order to form the SiN film-like tensile stress film 131a, a silicon source gas such as SiH4 and a nitrogen source gas such as NH3 or N2 are used as the source gas, and the temperature is about 300 to 600 캜. The deposition process may be performed under a pressure of 1 to 10 torr.

Subsequently, an etch stop film 133a may be further formed on the tensile stress film 131a. The etch stop film 133 may be formed of an LTO film as described above.

After the tensile stress film 131a and the etch stop film 133a are formed, a first mask pattern P1 for selectively exposing the PMOS transistor region II is formed. The first mask pattern P1 may be a photoresist pattern. In this case, a first mask pattern P1 covering the NMOS transistor region I may be formed over a portion of the boundary portion III in the process margin.

Then, as shown in FIG. 6, the tensile stress film and the etch stop film formed in the regions other than the NMOS transistor region I are removed, and thus the tensile stress film 131 and the etch stop film ( 133) is left. The tensile stress film and the etch stop film removal process may be by a dry or wet etching method commonly used in the art. In addition, the tensile stress film 131 and the etch stop film 133 remain at the boundary portion III.

The formed tensile stress film 131 may improve carrier mobility by applying a high tensile stress to the channel region of the NMOS transistor, so that the performance of the NMOS transistor may be further improved.

7 to 8, the compressive stress film 135 is formed in the PMOS transistor region II.

First, as shown in FIG. 7, the compressive stress film 135a is formed on the entire surface of the substrate. The compressive stress film 135 may be formed using chemical vapor deposition (CVD), for example, thermal CVD, PECVD, high density plasma CVD, or the like. The thickness and the material of the compressive stress film 135a are as described above with reference to FIG. 2. In this case, the compressive stress film 135a may also be formed on the previously formed NMOS transistor region I, that is, the tensile stress film 131 and the etch stop film 133.

Then, a second mask pattern P2, for example, a photoresist pattern, which selectively exposes the NMOS transistor region I is formed. In this case, a second mask pattern P2 covering the process margin PMOS transistor region II may be formed over a portion of the boundary portion III.

Then, as shown in FIG. 8, the compressive stress film is etched in the region exposed by the second mask pattern P2 and then the second mask pattern P2 is removed to compress the compressive stress in the PMOS transistor region II. The film 135 is left. At this time, the compressive stress film 135 remains at the boundary portion III. Thus, the tensile stress film 131, the etch stop film 133, and the compressive stress film 135 are all stacked on the boundary portion III. The laminated film may be located on the third silicide film 127c formed at the boundary portion III. This compressive stress film removal process may be by a dry or wet etching method commonly used in the art.

In the above-described method of manufacturing a semiconductor device, the tensile stress film forming process is performed before the compressive stress film forming process, but the present invention is not limited thereto. In contrast, the compressive stress film may be formed before the tensile stress film. In this case, the etch stop film may be formed on the compressive stress film instead of the tensile stress film.

Then, the compressive stress film 135 overlying the third silicide film 127c formed on the boundary portion III is removed. As a result, only the tensile stress film 131 may remain on the third silicide film 127c, and a stress film having a similar thickness may exist on the first to third silicide films 127a, 127b, and 127c. At this time, the etch stop film 133 may remain on the tensile stress film 131, or part or all of the etch stop film 131 may be removed.

Specifically, as shown in FIG. 9, the photoresist film P3 covering the entire surface of the semiconductor substrate is formed.

Subsequently, as shown in FIG. 10, the photoresist film P4 is selectively etched back so that the compressive stress film 135 superimposed on the third silicide film 127c protrudes and is exposed. ) Is left. In this case, the selective etch back may be performed by a RIE etch back process using an O 2 or O 3 plasma. Here, a separate etching gas may be further added within the scope of the present invention.

Then, as shown in FIG. 11, the exposed portion of the compressive stress film 135 is selectively removed. In this case, any etching method may be used as long as the photoresist film P4 is left in the condition that the protruding exposed portions of the compressive stress film 135 can be selectively removed. As a result, only a single stress film may be positioned on the third silicide layer 127c.

On the other hand, in the non-selective etch back process, the process of removing part of the photoresist and the process of removing part of the compressive stress film may be performed in a single process. That is, the result of FIG. 11 may be obtained without going through the step of FIG. 10.

At this time, the non-selective etch back process is a process that can remove the photoresist film and the compressive stress film at the same time, for example, can be performed by an etch back process using RIE using a gas of CxFy / CxHyFz / O2 series. .

Next, referring to FIG. 12, the remaining photoresist film (P4 of FIG. 11) is removed, an interlayer insulating layer 140 is formed on the entire surface of the semiconductor substrate, and then a contact hole is formed on the interlayer insulating layer 140. A mask pattern P5 having openings 151a, 153a, and 155a is formed.

The interlayer insulating layer 140 may include O ₃ -TEOS (O ₃ -Tetra Ethyl Ortho Silicate), USG (Undoped Silicate Glass), PSG (PhosphoSilicate Glass), BSG (Borosilicate Glass), BPOG (BoroPhosphoSilicate Glass), FSG (Fluoride Silicate Glass) ), Spin On Glass (SOG), Tonen SilaZene (TOSZ), or a combination thereof may be used. Here, the interlayer insulating layer 140 may be formed using a CVD method, a spin coating method, but is not limited thereto.

Subsequently, as shown in FIG. 13, an etching process is performed by using the mask pattern (P5 of FIG. 12) as an etch mask so that the bottom surface is located on or inside the first to third silicide layers 127c. The first to third contact holes 151, 153, and 155 are completed.

Thereafter, the mask pattern P5 may be removed, and contact plugs 161, 163, and 165 may be formed to fill the respective contact holes, thereby manufacturing the semiconductor device illustrated in FIG. 2.

The contact plugs 161, 163, and 165 may be filled with a metal material such as W, Cu, or Al, or a conductive material such as conductive polysilicon. Although not shown in the drawings, a barrier layer (not shown) may be further conformally formed along each of the contact holes 151, 153, and 155 before filling with the conductive material. The barrier layer may include an ohmic layer for improving contactability of the metal layer embedded in the contact holes 151, 153, and 155, and a diffusion barrier for preventing the metal material from diffusing and reacting with the silicon. For example, the ohmic film may be formed by conformally depositing a high melting point metal (refractory metal) such as Ti or Ta along the contact hole, and the diffusion barrier is formed by depositing TiN or TaN along the surface of the ohmic film. can do.

In the process of forming the contact plug, a planarization process such as chemical mechanical polishing (CMP) or etch back may be performed until the surface of the interlayer insulating layer 140 is exposed.

As described above, according to the exemplary embodiments of the present invention, since the contact plug may be stably formed in the contact hole which is not over-etched and the bottom surface is present on or inside the silicide layer, the characteristics of the semiconductor device such as resistance or leakage current are improved. Can be.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1 is a cross-sectional view showing a semiconductor device according to the prior art.

2 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

3 to 13 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols on main parts of the drawings>

100: semiconductor substrate 111: device isolation region

121a: N-type source / drain area 121b: P-type source / drain area

123: gate insulating film 125a, 125b, 125c: gate electrode

127a: first silicide film 127b: second silicide film

127c: third silicide film 131: tensile stress film

133: etch stop film 135: compressive stress film

140: interlayer insulating film 151: first contact hole

153: second contact hole 155: third contact hole

161,163,165: Contact Plug

Claims (5)

Providing a semiconductor substrate having a first transistor region and a second transistor region, A first transistor including a gate electrode having a first silicide layer formed thereon and a first conductivity type source / drain region, and a second including a gate electrode having a second silicide layer formed thereon and a second conductive source / drain region formed therein Transistors are formed in the first and second transistor regions, respectively, A first stress film is formed in the first transistor region and a second stress film is sequentially formed in the second transistor region, and the first stress film is formed on a third silicide layer provided at a boundary between the first transistor region and the second transistor region. The first stress film and the second stress film are sequentially superimposed, Removing the second stress film superimposed on the third silicide film, An interlayer insulating film is formed on the entire surface of the semiconductor substrate, A contact hole penetrating through the interlayer insulating layer and having a bottom surface formed on or in the upper surface of the first to third silicide layers; And forming a contact plug to fill the contact hole. The process of claim 1, wherein the removing of the second stress film is performed. After forming the first stress film and the second stress film, a photoresist film is formed on the entire surface of the semiconductor substrate, and is etched back to selectively remove a portion of the photoresist film, thereby exposing the second stress film on the third silicide film. Further includes, Removing the second stress film, and then removing the remaining photoresist film. The process of claim 1, wherein the removing of the second stress film is performed. After forming the first stress film and the second stress film, a photoresist film is formed on the entire surface of the semiconductor substrate, and a portion of the photoresist film is non-selectively etched back while simultaneously removing the second stress film on the third silicide film. Further includes, Removing the second stress film, and then removing the remaining photoresist film. The method of claim 1, The first transistor and the second transistor are NMOS transistors and PMOS transistors, respectively. And the first stress film and the second stress film are tensile stress films and compressive stress films, respectively. The method of claim 1, And said first stress film and said second stress film are SiN, SION, SiC, SiCN, SiO2, or a combination thereof, respectively.

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