KR20080018709A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR20080018709A
KR20080018709A KR1020060081275A KR20060081275A KR20080018709A KR 20080018709 A KR20080018709 A KR 20080018709A KR 1020060081275 A KR1020060081275 A KR 1020060081275A KR 20060081275 A KR20060081275 A KR 20060081275A KR 20080018709 A KR20080018709 A KR 20080018709A
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South Korea
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episilicon
film
gate
forming
epitaxial silicon
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KR1020060081275A
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Korean (ko)
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김재영
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주식회사 하이닉스반도체
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Priority to KR1020060081275A priority Critical patent/KR20080018709A/en
Publication of KR20080018709A publication Critical patent/KR20080018709A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Abstract

A method of fabricating a semiconductor device is provided to reduce overlap between a gate and a source/drain region by forming three epitaxial silicon layers on a semiconductor substrate. A gate(G) is formed on a semiconductor substrate(10), and then a first epitaxial silicon layer(100) is formed on the substrate at both sides of the gate. An LDD(Lightly Doped Drain) region(LDD) is formed in a surface of the first epitaxial silicon layer. A first spacer(15) and a second spacer(16) are formed at both sides of the gate. A second epitaxial silicon layer(200) is formed on the first epitaxial silicon layer at both sides of the gate. A source/drain region(S/D) is formed in the second epitaxial silicon layer, the first epitaxial silicon layer under the second epitaxial silicon layer, and the substrate under the first epitaxial silicon layer. A third epitaxial silicon layer(300) is formed on the second epitaxial silicon layer, and then is implanted with ion.

Description

반도체 소자의 제조방법{Method of manufacturing semiconductor device} Method of manufacturing semiconductor device

도 1 내지 도 5는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.1 to 5 are cross-sectional views for each process for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10: 반도체기판 11: 게이트 절연막10: semiconductor substrate 11: gate insulating film

12: 폴리실리콘막 13: 텅스텐실리사이드막12: polysilicon film 13: tungsten silicide film

14: 게이트 하드마스크막 15: 제1스페이서14: gate hard mask layer 15: first spacer

16: 제2스페이서 100: 제1에피실리콘막16: second spacer 100: first episilicon film

200: 제2에피실리콘막 300: 제3에피실리콘막200: second episilicon film 300: third episilicon film

G: 게이트 LDD: LDD영역G: gate LDD: LDD area

S/D: 소오스/드레인영역S / D: Source / Drain Area

본 발명은 모스펫 소자의 제조방법에 관한 것으로, 보다 상세하게는, 소자의 고집적화에 따라 발생되는 문제점을 해결할 수 있는 방법에 관한 것이다.The present invention relates to a method for manufacturing a MOSFET device, and more particularly, to a method that can solve the problems caused by the high integration of the device.

최근, 모스펫 소자의 고집적화가 진행되면서, 셀(cell) 사이즈의 감소로 인 해 게이트 선폭 감소가 수반되고 있고, 상기 게이트 전극의 선폭 감소는 채널 길이의 감소를 초래하게 된다. In recent years, as the integration of MOSFET devices has progressed, the gate line width has been reduced due to the reduction of the cell size, and the reduction of the line width of the gate electrode leads to the reduction of the channel length.

이러한 채널 길이의 감소는, 반도체기판의 도핑(doping) 농도를 증가시키게 되는데, 그 결과, 소자의 누설전류 증가 및 문턱전압(threshold voltage)이 급격히 낮아지는, 이른바 단채널효과(short channel effect)가 심해지고 있다.This reduction in channel length increases the doping concentration of the semiconductor substrate, which results in a so-called short channel effect, in which the leakage current of the device and the threshold voltage are drastically lowered. It's getting worse.

또한, 소자의 고집적화로 인해, 소오스/드레인영역간의 간격이 점차로 좁아지게 되면서, 드레인영역의 증가에 따라 채널접합과 상호 작용하여 전위 장벽을 낮추는 드레인 유기 장벽 감소(DIBL:Drain Induced Barrier Lowering)의 특성이 취약해지는 문제를 발생시키고 있다.In addition, due to the high integration of the device, the gap between the source and drain regions gradually narrows, and as the drain region increases, the characteristics of the drain induced barrier lowering (DIBL) that interact with the channel junction and lower the potential barrier are reduced. This is causing the problem of becoming vulnerable.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 채널 길이를 확보하여 단채널효과를 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing a short channel effect by securing a channel length.

또한, 본 발명은 소오스/드레인영역간의 간격을 넓힘으로서 DIBL 특성을 개선시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 다른 목적이 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving DIBL characteristics by widening a gap between source and drain regions.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 반도체기판 상에 게이트를 형성하는 단계; 상기 게이트 양측의 기판 상에 제1에피실리콘막을 형성하는 단계; 상기 제1에피실리콘막의 표면 내에 LDD영역을 형성하는 단계; 상기 게이트 양측에 제1스페이서 및 제2스페이서를 차례로 형성하는 단계; 상기 제2스페이서를 포함한 게이트 양측의 상기 제1에피실리콘막 상에 제2에피실리콘막을 형성하는 단계; 상기 제2에피실리콘막과 상기 제2에피실리콘막 아래의 제1에피실리콘막 부분 및 상기 제1에피실리콘막 아래의 상기 반도체기판 내에 소오스/드레인영역을 형성하는 단계; 상기 제2에피실리콘막 상에 제3에피실리콘막을 형성하는 단계; 및 상기 제3에피실리콘막 내에 스토리지노드 콘택 및 비트라인 콘택의 저항 감소를 위한 이온주입을 수행하는 단계;를 포함하는 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention, forming a gate on a semiconductor substrate; Forming a first episilicon film on the substrate on both sides of the gate; Forming an LDD region in the surface of the first episilicon film; Sequentially forming a first spacer and a second spacer on both sides of the gate; Forming a second episilicon film on the first episilicon film on both sides of the gate including the second spacer; Forming a source / drain region in the portion of the first episilicon layer under the second episilicon layer and the second episilicon layer and in the semiconductor substrate under the first episilicon layer; Forming a third episilicon film on the second episilicon film; And performing ion implantation to reduce the resistance of the storage node contact and the bit line contact in the third epi-silicon film.

여기서, 상기 제1에피실리콘막은 300∼400Å 두께로 형성하는 것을 특징으로 한다.Here, the first episilicon film is characterized in that it is formed to a thickness of 300 ~ 400Å.

상기 제2에피실리콘막은 200∼300Å 두께로 형성하는 것을 특징으로 한다.The second episilicon film is formed to have a thickness of 200 to 300 GPa.

상기 제3에피실리콘막은 200∼300Å 두께로 형성하는 것을 특징으로 한다.The third episilicon film is formed to have a thickness of 200 to 300 GPa.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 설명하면, 본 발명은 게이트 양측의 기판 상에 에피택셜 성장법(Epitaxial Growth)을 이용하여 제1에피실리콘막을 형성하고 나서, 상기 제1에피실리콘막 표면 내에 LDD영역을 형성한다.First, the technical principle of the present invention will be described. According to the present invention, a first episilicon film is formed on a substrate on both sides of a gate by using epitaxial growth, and then an LDD region is formed on the surface of the first episilicon film. To form.

그리고, 상기 게이트 양측에 제1스페이서 및 제2스페이서를 형성한 후, 상기 제1에피실리콘막 상에 제2에피실리콘막을 형성하고 나서, 상기 제2에피실리콘막과 그 아래의 제1에피실리콘막 및 반도체기판 내에 소오스/드레인영역을 형성한다.After forming a first spacer and a second spacer on both sides of the gate, a second episilicon film is formed on the first episilicon film, and then the second episilicon film and the first episilicon film thereunder. And source / drain regions are formed in the semiconductor substrate.

그리고, 상기 제2에피실리콘막 상에 제3에피실리콘막을 형성한 후, 상기 제3 에피실리콘막 내에 후속의 스토리지 노드 콘택 및 비트라인 콘택 저항 감소를 위한 이온주입을 수행하는 것을 특징으로 한다.After the third episilicon layer is formed on the second episilicon layer, ion implantation for subsequent storage node contact and bit line contact resistance reduction is performed in the third episilicon layer.

이렇게 하면, 상기 반도체기판 상에 에피실리콘막(제1,제2 에피실리콘막)이 형성됨에 따라, 게이트와 소오스/드레인영역간의 오버랩(overlap)을 감소시킬 수 있으므로, 게이트의 채널길이를 확보할 수 있어 단채널효과를 방지할 수 있다.In this case, as the epi-silicon films (first and second epi-silicon films) are formed on the semiconductor substrate, overlap between the gate and the source / drain regions can be reduced, thereby ensuring the channel length of the gate. The short channel effect can be prevented.

또한, 상기 소오스/드레인영역간의 간격을 넓힐 수 있으므로, 넓어진 소오스/드레인영역간의 간격을 통해 DIBL 특성을 개선시킬 수 있다.In addition, since the interval between the source / drain regions can be widened, the DIBL characteristic can be improved through the widened interval between the source / drain regions.

게다가, 본 발명은 콘택 저항 개선용 고농도 이온주입을 수행함으로서, 스토리지 노드 콘택 및 비트라인 콘택 저항을 감소시킬 수 있다.In addition, the present invention can reduce the storage node contact and the bit line contact resistance by performing high concentration ion implantation for improving contact resistance.

자세하게, 도 1 내지 도 5는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다. 1 to 5 are cross-sectional views for each process for describing a method of manufacturing a semiconductor device according to the present invention.

도 1을 참조하면, 반도체기판(10) 상에 산화막 재질의 게이트 절연막(11)과 폴리실리콘막(12)과 금속막 계열의 막, 바람직하게는, 텅스텐실리사이드막(13)으로 적층된 게이트 도전막 및 게이트 하드마스크막(14)을 차례로 증착한 후, 이들을 식각하여 반도체기판(10) 상에 게이트(G)를 형성한다.Referring to FIG. 1, a gate conductive layer stacked on a semiconductor substrate 10 with a gate insulating film 11 made of an oxide film, a polysilicon film 12, and a metal film-based film, preferably a tungsten silicide film 13. The film and the gate hard mask film 14 are sequentially deposited and then etched to form a gate G on the semiconductor substrate 10.

그런다음, 상기 게이트(G)를 포함한 기판 전면 상에 산화 공정을 수행하여 상기 게이트(G)의 양측 및 기판(10) 표면 상에 얇은 두께의 산화막(미도시)을 형성한다.Then, an oxidation process is performed on the entire surface of the substrate including the gate G to form a thin oxide film (not shown) on both sides of the gate G and the surface of the substrate 10.

도 2를 참조하면, 상기 게이트(G)를 포함한 기판 전면에 에피택셜 성장법(Epitaxial Growth)을 이용하여 상기 게이트(G) 양측의 기판 상에 300∼400Å 두께로 제1에피실리콘막(100)을 형성한다.Referring to FIG. 2, the first episilicon film 100 may be formed on the substrate on both sides of the gate G by using a epitaxial growth method on the entire surface of the substrate including the gate G. To form.

그런다음, 상기 제1에피실리콘막(100)에 대해 저농도 이온주입을 수행하여 상기 제1에피실리콘막의 표면 내에 LDD영역(LDD)을 형성한다.Then, low concentration ion implantation is performed on the first episilicon film 100 to form an LDD region LDD on the surface of the first episilicon film.

여기서, 본 발명의 기술적 특징은 상기 반도체기판(10) 상에 제1에피실리콘막(100)을 형성하고 나서, 상기 제1에피실리콘막(100) 내에 LDD영역(LDD)을 형성함에 있다. The technical feature of the present invention is that after forming the first episilicon film 100 on the semiconductor substrate 10, the LDD region LDD is formed in the first episilicon film 100.

도 3을 참조하면, 상기 게이트(G)를 포함한 기판 전면 상에 스페이서용 절연막을 증착한 후, 이를 식각하여 상기 게이트 양측(G)벽에 제1스페이서(15)를 형성한다. 그런다음, 상기 제1스페이서(15)를 포함한 기판 전면 상에 스페이서용 절연막 증착한 후, 이를 식각하여 상기 제1스페이서(15)가 형성된 게이트(G) 양측벽에 제2스페이서(16)를 형성한다.Referring to FIG. 3, after the insulating film for spacers is deposited on the entire surface of the substrate including the gate G, the spacers are etched to form first spacers 15 on both side G walls of the gate. Then, an insulating film for a spacer is deposited on the entire surface of the substrate including the first spacer 15, and then etched to form second spacers 16 on both side walls of the gate G on which the first spacer 15 is formed. do.

도 4를 참조하면, 상기 제2스페이서(16)를 포함한 게이트(G) 양측의 상기 제1에피실리콘막(100) 상에 300∼400Å 두께로 제2에피실리콘막(200)을 형성한다. 그런다음, 상기 제2에피실리콘막(200)에 대해 고농도 이온주입을 수행하여 상기 제2에피실리콘막(200)과 상기 제2에피실리콘막 아래의 제1에피실리콘막(100) 부분 및 상기 제1에피실리콘막 아래의 상기 반도체기판(10) 내에 소오스/드레인영역(S/D)을 형성한다.Referring to FIG. 4, a second episilicon film 200 is formed on the first episilicon film 100 on both sides of the gate G including the second spacer 16 to a thickness of 300 to 400 Å. Then, a high concentration of ion implantation is performed on the second episilicon film 200 to form a portion of the first episilicon film 100 under the second episilicon film 200 and the second episilicon film and the first episilicon film 200. A source / drain region S / D is formed in the semiconductor substrate 10 under the one episilicon film.

여기서, 본 발명의 기술적 특징은, 게이트 양측벽에 제1 및 제2스페이서(15,16)를 형성하고 나서, 상기 LDD영역(LDD)이 형성된 제1에피실리콘막(100) 상에 제2에피실리콘막(200)을 형성한 후, 상기 제2에피실리콘막(200)과 그 아래의 제 1에피실리콘막(100) 및 반도체기판(10) 내에 소오스/드레인영역(S/D)을 형성함에 있다.Here, the technical feature of the present invention is that after forming the first and second spacers 15 and 16 on both side walls of the gate, the second epitaxial layer is formed on the first episilicon film 100 having the LDD region LDD formed thereon. After the silicon film 200 is formed, source / drain regions S / D are formed in the second episilicon film 200, the first episilicon film 100 and the semiconductor substrate 10 below. have.

이와 같이, 상기 제1에피실리콘막(100) 상에 제2에피실리콘막(200)이 형성됨에 따라, 상기 게이트(G)와 소오스/드레인영역(S/D)간의 오버랩(overlap)을 감소시킬 수 있으므로, 게이트의 채널길이를 확보할 수 있어 단채널효과를 방지할 수 있다.As such, as the second episilicon film 200 is formed on the first episilicon film 100, the overlap between the gate G and the source / drain regions S / D may be reduced. As a result, the channel length of the gate can be secured and the short channel effect can be prevented.

또한, 상기 소오스/드레인영역간의 간격을 넓어지게 되면서, 넓어진 소오스/드레인영역간의 간격을 통해 DIBL 특성을 개선시킬 수 있다.In addition, as the interval between the source / drain regions is widened, the DIBL characteristic may be improved through the widened interval between the source / drain regions.

도 5를 참조하면, 상기 소오스/드레인영역(S/D)이 형성된 제2에피실리콘막 (200)상에 제3에피실리콘막(300)을 형성한 후, 상기 제3에피실리콘막(300) 내에 후속의 스토리지 노드 콘택(Stroge Node Contact) 및 비트라인 콘택(Biteline Contact) 저항 감소를 위한 고농도 이온주입을 수행한다.Referring to FIG. 5, after forming the third episilicon film 300 on the second episilicon film 200 on which the source / drain regions S / D are formed, the third episilicon film 300 is formed. High concentration ion implantation is performed to reduce subsequent Storage Node Contact and Bitline Contact resistance within the substrate.

여기서, 본 발명의 기술적 특징은, 상기 제2에피실리콘막(200) 상에 제3에피실리콘막(300)을 형성한 후, 상기 제3에피실리콘막(300) 내에 후속의 스토리지 노드 콘택 및 비트라인 콘택의 저항 감소를 위한 이온주입을 수행함에 있다.Here, the technical feature of the present invention, after forming a third epi-silicon film 300 on the second epi-silicon film 200, subsequent storage node contact and bit in the third epi-silicon film 300 In performing ion implantation for reducing the resistance of the line contact.

이와 같이, 본 발명은 콘택 저항 개선용 고농도 이온주입을 수행함으로서, 후속의 스토리지 노드 콘택 및 비트라인 콘택 저항을 감소시킬 수 있다.As described above, the present invention can reduce the subsequent storage node contact and bit line contact resistance by performing high concentration ion implantation for improving contact resistance.

이후, 도시하지는 않았으나, 공지된 일련의 후속 공정을 차례로 진행하여 본 발명의 실시예에 따른 반도체 소자를 제조한다.Subsequently, although not shown, a series of successive known processes are sequentially performed to manufacture a semiconductor device according to an embodiment of the present invention.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지 만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다. Hereinbefore, the present invention has been illustrated and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

이상에서와 같이, 본 발명은 반도체기판에 대해 에피택셜 성장법을 이용하여 반도체기판 상에 에피실리콘막을 3차례 형성함으로서, 게이트와 소오스/드레인영역간의 오버랩을 감소시켜 채널길이를 확보할 수 있으며, 이로 인해, 단채널효과를 방지할 수 있다.As described above, the present invention forms epitaxial films three times on the semiconductor substrate by using the epitaxial growth method for the semiconductor substrate, thereby reducing the overlap between the gate and the source / drain regions, thereby securing the channel length. For this reason, the short channel effect can be prevented.

또한, 본 발명은 소오스/드레인영역간의 간격이 넓어짐에 따라 드레인 인가 전압에 의한 DIBL 특성을 개선시킬 수 있다.In addition, the present invention can improve the DIBL characteristics due to the drain applied voltage as the interval between the source and drain regions becomes wider.

게다가, 본 발명은 콘택 저항 개선용 고농도 이온주입을 수행함으로서, 스토리지 노드 콘택 및 비트라인 콘택 저항을 감소시킬 수 있다.In addition, the present invention can reduce the storage node contact and the bit line contact resistance by performing high concentration ion implantation for improving contact resistance.

Claims (4)

반도체기판 상에 게이트를 형성하는 단계;Forming a gate on the semiconductor substrate; 상기 게이트 양측의 기판 상에 제1에피실리콘막을 형성하는 단계;Forming a first episilicon film on the substrate on both sides of the gate; 상기 제1에피실리콘막의 표면 내에 LDD영역을 형성하는 단계;Forming an LDD region in the surface of the first episilicon film; 상기 게이트 양측에 제1스페이서 및 제2스페이서를 차례로 형성하는 단계;Sequentially forming a first spacer and a second spacer on both sides of the gate; 상기 제2스페이서를 포함한 게이트 양측의 상기 제1에피실리콘막 상에 제2에피실리콘막을 형성하는 단계;Forming a second episilicon film on the first episilicon film on both sides of the gate including the second spacer; 상기 제2에피실리콘막과 상기 제2에피실리콘막 아래의 제1에피실리콘막 부분 및 상기 제1에피실리콘막 아래의 상기 반도체기판 내에 소오스/드레인영역을 형성하는 단계;Forming a source / drain region in the portion of the first episilicon layer under the second episilicon layer and the second episilicon layer and in the semiconductor substrate under the first episilicon layer; 상기 제2에피실리콘막 상에 제3에피실리콘막을 형성하는 단계; 및Forming a third episilicon film on the second episilicon film; And 상기 제3에피실리콘막 내에 스토리지 노드 콘택 및 비트라인 콘택의 저항 감소를 위한 이온주입을 수행하는 단계;Performing ion implantation to reduce resistance of a storage node contact and a bit line contact in the third episilicon layer; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법. Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제1에피실리콘막은 300∼400Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The first epi-silicon film is 300 to 400 ∼ thickness manufacturing method of a semiconductor device, characterized in that formed. 제 1 항에 있어서,The method of claim 1, 상기 제2에피실리콘막은 200∼300Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.And the second episilicon film is formed to a thickness of 200 to 300 GHz. 제 1 항에 있어서,The method of claim 1, 상기 제3에피실리콘막은 200∼300Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The third episilicon film is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 200 ~ 300Å.
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