KR20080011918A - Delay locked loop circuit having low jitter and jitter reducing method thereof - Google Patents

Abstract

A delay locked loop circuit and a jitter reducing method thereof are provided to decrease an amount of bang-bang jitters in the DLL(Delay Locked Loop) by mixing two delay signals around a middle point between first edges of the delay signals. An auxiliary phase shifter(31) receives a clock signal and outputs a clock signal with or without a delay. A coarse delay line(32) receives an output signal from the auxiliary phase shifter, sequentially delays the received signal, and outputs plural delay signals. A phase selector(33) selects two of the delay signals and outputs the selected signals. A phase mixer(34) phase-mixes the two delays signals and outputs a feedback signal. A phase detector(35) compares the clock signal with the feedback signal and generates a detection signal corresponding to a phase difference between the clock signal and the feedback signal. A control circuit(36) controls the auxiliary phase shifter, the phase selector, and the phase mixer in response to the detection signal.

Description

Delay locked loop circuit having low jitter and jitter reducing method

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram showing a conventional DLL of the Register Controlled Type of the DLL.

FIG. 2 is a diagram illustrating phase mixing in the conventional DLL of FIG. 1.

3 is a block diagram illustrating a DLL according to an embodiment of the present invention.

4 is a diagram illustrating phase mixing in a DLL according to an embodiment of the present invention of FIG. 3.

FIG. 5 is a circuit diagram illustrating an example of the auxiliary phase shifter illustrated in FIG. 3.

FIG. 6 is a circuit diagram illustrating another example of the auxiliary phase shifter illustrated in FIG. 3.

The present invention relates to a delay locked loop circuit, and more particularly, to a delay locked loop circuit having small jitter and a method of reducing jitter thereof.

In the I / O (Input / Output) interface method, which transfers data in synchronization with a clock signal, such as data transfer between a memory device and a memory controller in the system, accurate timing synchronization between the clock signal and the data increases as the bus load increases and the transmission frequency increases. It is very important to achieve. Circuits that can be used for this purpose include a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit, but in general, a memory device uses a DLL to synchronize data to a clock signal. Many ways are implemented. An example of a conventional DLL is disclosed in US 2006/0001465 A1.

1 is a block diagram showing a conventional DLL of the Register Controlled Type of the DLL.

Referring to FIG. 1, a DLL of a register controlled type includes a buffer 11, a coarse delay line 12, a phase selector 13, a phase mixer 14, and a phase. It comprises a phase detector 15 and the control circuit 16. The DLL has a coarse / fine loop structure, and a coarse delay line 12 in the form of a tapped delay line is used as the coarse loop, and a phase mixer 14 is used as the fine loop. do.

In the process of reducing the phase error of the DLL, the phase difference between the phase error information (clock signal CLK and feedback signal OCLK) detected by the phase detector 15 is first determined by the control circuit 16. The up / down signal is generated according to the lead / lag state using the detection signal corresponding to the corresponding detection signal). The coarse delay line 12 receives the clock signal CLK via the buffer 11 and sequentially delays the clock signal CLK by a unit delay time to output a plurality of delay signals. Based on the up / down signals, two delay signals? I and? J of the plurality of delay signals, that is, adjacent ones of the plurality of unit coarse delay cells in the coarse delay line 12, may be adjacent to each other. Two signals output from the two delay cells are selected by the phase selector 13.

The delay signal Φ i (i = 0, 2, 4, ...) represents a signal output from an even-numbered delay cell among the unit coarse delay cells in the coarse delay line 12, and the delay signal phi j (j = 1, 3, 5, ...)) represents a signal output from an odd-numbered delay cell among the unit coarse delay cells in the coarse delay line 12.

Next, the phase mixer 14 phase-mixes the two delay signals? I and? J for fine lock, and outputs the final output signal OCLK in which the amount of phase error is minimized.

However, in the conventional DLL, when two delay signals Φi and Φj are phase-mixed near the edge of the delay signal Φi or near the edge of the delay signal Φj, as shown in FIG. This has the disadvantage of increasing the amount of bang jitter.

Therefore, the present invention is to provide a delayed synchronization loop circuit having a small bang bang jitter.

Another technical object of the present invention is to provide a method for reducing bang bang jitter in a delay locked loop circuit.

The delay synchronization loop circuit according to the present invention for achieving the above technical problem is controlled by a control circuit, and receives a clock signal and outputs it to a corse delay line without delaying the clock signal or the clock signal. And an auxiliary phase shifter for delaying a signal by a predetermined time and outputting the signal to the coarse delay line.

The coarse delay line receives the output signal of the auxiliary phase shifter and sequentially delays a unit delay time to output a plurality of delay signals. In particular, the predetermined time in the auxiliary phase shifter is set to be half the unit delay time of the unit coarse delay cell included in the coarse delay line.

A phase selector selects and outputs two delayed signals among the plurality of delayed signals, and a phase mixer outputs a feedback signal by phase blending the two delayed signals. The phase detector compares the clock signal with the feedback signal to generate a detection signal corresponding to the phase difference between the clock signal and the feedback signal.

The control circuit controls the auxiliary phase shifter, the phase selector, and the phase mixer in response to the detection signal.

In particular, the control circuit detects whether the delay locked loop circuit is initially locked and controls the auxiliary phase shifter to output the clock signal as it is without delay when the delay locked loop circuit is not initially locked. do.

The control circuit detects a point at which the two delay signals are phase-mixed in the phase mixer when the delay lock loop circuit is initially locked, and accordingly, the auxiliary phase shifter outputs the delayed clock signal without delaying the clock signal. Or delay and output the clock signal by the predetermined time.

In this case, the control circuit controls the auxiliary phase shifter to output the clock signal without delay when the point where the two delay signals are phase-mixed is near the middle between the first edges of the two delay signals. And the auxiliary circuit shifter delays the clock signal by the predetermined time when the point where the two delayed signals are phase-mixed is near the edge of any one of the first edges of the two delayed signals. To control the output.

According to an aspect of the present invention, a jitter reduction method includes: a coarse delay line for receiving an input signal and sequentially delaying a unit delay time to output a plurality of delay signals, and two selected ones of the plurality of delay signals. CLAIMS What is claimed is: 1. A method of reducing jitter in a delay locked loop circuit having a phase mixer for phase blending delay signals, the method comprising: (a) detecting whether the delay locked loop circuit is initially locked; (b) providing the input signal of the coarse delay line without delaying the clock signal when the delay lock loop circuit is not initially locked; And (c) when the delayed synchronization loop circuit is initially locked, detecting a point at which the two delayed signals are phase-mixed in the phase mixer and, accordingly, delaying the clock signal without delaying the clock signal. Providing as a signal or delaying the clock signal by a predetermined time to provide the signal as the input signal of the coarse delay line.

The predetermined time is set to be half of the unit delay time.

In step (c), when the point where the two delayed signals are phase-mixed is near the middle between the first edges of the two delayed signals, the step (c) is used as the input signal of the coarse delay line without delaying the clock signal. Providing; And when the point where the two delayed signals are phase-mixed is near the edge of any one of the first edges of the two delayed signals, delays the clock signal by the predetermined time so as to input the input signal of the coarse delay line. It provides as a step.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram illustrating a DLL according to an embodiment of the present invention.

Referring to FIG. 3, a DLL according to an embodiment of the present invention may include an auxiliary phase shifter 31, a coarse delay line 32, a phase selector 33, A phase mixer 34, a phase detector 35, and a control circuit 36 are provided.

The DLL according to the present invention is a register controlled type DLL having a core / fine loop structure, and a core delay line 32 having a tapped delay line type is used as a core loop and a fine loop. As a phase mixer 34 is used.

The auxiliary phase shifter 31 is controlled by the control circuit 36 as to adjust the point where the DLL is phase mixed in the phase mixer 34 after the initial lock. The auxiliary phase shifter 31 receives the clock signal CLK in response to the control signal CNT generated by the control circuit 36 and outputs the signal as it is without delaying the clock signal CLK, or the clock signal CLK. Is delayed by a predetermined time (θ / 2) and output.

The coarse delay line 32 includes a plurality of unit coarse delay cells connected in series, and receives the output signal ICLK of the auxiliary phase shifter 31 and sequentially through the unit coarse delay cells. A plurality of delay signals are output by delaying the unit delay time θ. In particular, the predetermined time θ / 2 in the auxiliary phase shifter 31 is set to be half of the unit delay time of the unit coarse delay cells included in the coarse delay line 32.

The phase selector 33 is based on an up / down signal generated by the control circuit 36 and includes two delay signals Φ i and Φ j of the plurality of delay signals, that is, a coarse delay line. 12, two signals output from two adjacent delay cells among the unit coarse delay cells are selected and output.

The delay signal Φ i (i = 0, 2, 4, ...) represents a signal output from an even-numbered delay cell among the unit coarse delay cells in the coarse delay line 32, and the delay signal phi j (j = 1 (3, 5, ...)) represents a signal output from an odd-numbered delay cell among the unit coarse delay cells in the coarse delay line 32.

The phase mixer 34 phase-mixes the two delay signals? I and? J for fine lock and outputs the final output signal OCLK corresponding to the feedback signal. The phase detector 35 compares the clock signal CLK and the feedback signal OCLK to generate a detection signal corresponding to the phase difference between the clock signal CLK and the feedback signal OCLK.

The control circuit 36 controls the control signal CNT and the phase selector 33 for controlling the auxiliary phase shifter 31 using the phase error information detected by the phase detector 35, that is, the detection signal. Generates an UP / DOWN signal. The control circuit 36 also controls the phase mixer 34.

In particular, the control circuit 36 detects whether the DLL is initially locked, and assists the auxiliary phase shifter 31 to output the clock signal CLK without delay when the DLL is not initially locked. The phase shifter 31 is controlled.

When the DLL is initially locked, the control circuit 36 detects the point at which the two delay signals Φ i and Φ j are phase-mixed in the phase mixer 34 and accordingly, the auxiliary phase shifter 31 according to the result. ) Controls the auxiliary phase shifter 31 to output the clock signal CLK without delay or to delay the clock signal CLK by the predetermined time [theta] / 2.

In other words, after the DLL is initially locked, the point at which the two delay signals? When near the middle, the control circuit 36 controls the phase shifter 31 so that the auxiliary phase shifter 31 outputs without delaying the clock signal CLK.

The edge of any one of the first edges of the two delay signals (for example, the rising edge of Φ i and the rising edge of Φ j) is the point where the two delay signals Φ i and Φ j are phase mixed after the DLL is initially locked. When near, the control circuit 36 causes the auxiliary phase shifter 31 to set the clock signal CLK to the predetermined time θ / to adjust the point at which the two delay signals Φ i and Φ j are phase mixed. The auxiliary phase shifter 31 is controlled to delay and output by 2). That is, the auxiliary phase shifter 31 delays and outputs the clock signal CLK by the predetermined time θ / 2, so that the two delay signals Φ i and Φ j are applied to the first edges (eg, Φ i). The phase mixing is not performed near the edge of any one of the rising edge of and the rising edge of Φ j, but near the middle between the first edges (eg, the rising edge of Φ i and the rising edge of Φ j).

Accordingly, in the DLL according to the present invention, the amount of bang-bang zitter is reduced as shown in FIG. 4.

FIG. 5 is a circuit diagram illustrating an example of the auxiliary phase shifter illustrated in FIG. 3.

Referring to FIG. 5, the auxiliary phase shifter 31A outputs a delay cell 51, a clock signal CLK, and a delay cell 51 which delay and output a clock signal CLK by the unit delay time θ. A phase mixer 53 for phase-mixing and outputting signals, and a selector for selecting one of the output signal of the clock signal CLK and the phase mixer 53 in response to the control signal CNT and outputting the output signal ICLK ( 55).

Since the phase mixer 53 phase-mixes the clock signal CLK and the output signal of the delay cell 51, the output signal of the phase mixer 53 becomes a delayed signal θ / 2 with respect to the clock signal CLK.

The control signal CNT is a signal generated by the control circuit 36 shown in FIG. When the DLL is not initially locked, the control signal CNT is brought into the first logical state by the control circuit 36, and the selector 55 selects the clock signal CLK and outputs it as the output signal ICLK.

After the DLL is initially locked, the point where the two delay signals? I and? J are phase-mixed is near the middle between the first edges of the two delay signals (for example, the rising edge of? I and the rising edge of? J). At that time, the control signal CNT is brought into the first logic state by the control circuit 36. Accordingly, the selector 55 selects the clock signal CLK and outputs it as the output signal ICLK.

The edge of any one of the first edges of the two delay signals (for example, the rising edge of phi i and the rising edge of phi j) after the DLL is initially locked In the vicinity, the control signal CNT is brought into the second logic state by the control circuit 36. Accordingly, the selector 55 selects an output signal of the phase mixer 53, that is, a signal delayed by θ / 2 with respect to the clock signal CLK and outputs the output signal ICLK.

FIG. 6 is a circuit diagram illustrating another example of the auxiliary phase shifter illustrated in FIG. 3.

Referring to FIG. 6, the auxiliary phase shifter 31B includes a delay cell 61, a first phase mixer 62, a second phase mixer 63, a third phase mixer 64, and a selector 65. do. The reason that the auxiliary phase shifter 31B of FIG. 6 further includes two phase mixers 62 and 64 as compared to the auxiliary phase shifter 31A of FIG. 5 is that the load of the input stages of the first phase mixer 62 is different. ) And the loads of the input terminals of the second phase mixer 63 are equal, and the loads of the output terminals of the first phase mixer 62 and the output terminals of the second phase mixer 63 are equal.

The delay cell 61 delays and outputs the clock signal CLK by the unit delay time θ. The first phase mixer 62 receives the clock signal CLK through two different input terminals, and phase-mixes two signals input through the two input terminals to the selector 65. The output signal of the first phase mixer 62 becomes a signal which is not delayed with respect to the clock signal CLK.

The second phase mixer 63 phase-mixes the clock signal CLK and the output signal of the delay cell 61 to the selector 65. Since the phase signal of the clock signal CLK and the output signal of the delay cell 61 are phase-mixed by the second phase mixer 63, the output signal of the second phase mixer 63 is delayed by θ / 2 with respect to the clock signal CLK. It becomes a signal. The third phase mixer 64 receives the output signal of the delay cell 61 through two different input terminals and phase-mixes the two signals inputted through the two input terminals.

The selector 65 selects one of an output signal of the first phase mixer 62 and an output signal of the second phase mixer 63 in response to the control signal CNT and outputs the output signal ICLK. The control signal CNT is the same signal as the control signal CNT shown in FIG. 5 and is a signal generated by the control circuit 36 shown in FIG.

The best embodiment has been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in the DLL according to the present invention, when the phase mixing is performed near the edge of any one of the first edges of the two delay signals after the DLL is initially locked, the point where the phase is mixed is delayed by two. Adjusted to occur near the middle of the first edges of the signals. As a result, the DLL according to the present invention has the effect of reducing the amount of bang bang jitter.

Claims (13)

An auxiliary phase shifter for receiving and outputting a clock signal without delaying the clock signal or delaying and outputting the clock signal by a predetermined time; A corse delay line receiving the output signal of the auxiliary phase shifter and sequentially delaying the output signal by a unit delay time to output a plurality of delay signals; A phase selector for selecting and outputting two delay signals from the plurality of delay signals; A phase mixer which phase-mixes the two delayed signals and outputs a feedback signal; A phase detector for comparing the clock signal with the feedback signal to generate a detection signal corresponding to a phase difference between the clock signal and the feedback signal; And And a control circuit for controlling the auxiliary phase shifter, the phase selector, and the phase mixer in response to the detection signal. The delay lock loop as recited in claim 1, wherein the predetermined time is half of the unit delay time. The method of claim 2, wherein the auxiliary phase shifter, A delay cell for delaying and outputting the clock signal by the unit delay time; A phase mixer for phase-mixing the clock signal and the output signal of the delay cell; And And a selector for selecting and outputting one of the clock signal and the output signal of the phase mixer. The method of claim 2, wherein the auxiliary phase shifter, A delay cell for delaying and outputting the clock signal by the unit delay time; A first phase mixer configured to receive the clock signal through two different input terminals and to phase-mix two signals inputted through the two input terminals to the selector; A second phase mixer for phase-mixing the clock signal and the output signal of the delay cell to the selector; And And a third phase mixer configured to receive an output signal of the delay cell through two different input terminals and to phase-mix two signals inputted through the two input terminals. The method of claim 1, wherein the control circuit, Detecting whether the delay lock loop circuit is initially locked, and controlling the auxiliary phase shifter to output the clock signal without delaying the clock signal when the delay lock loop circuit is not initially locked. Loop circuit. The method of claim 5, wherein the control circuit, When the delay lock loop circuit is initially locked, the phase mixer detects a point at which the two delay signals are phase-mixed, and accordingly, the auxiliary phase shifter outputs the clock signal without delaying the clock signal or outputs the clock signal. And controlling the delayed output by the predetermined time. The method of claim 6, wherein the control circuit, And the auxiliary phase shifter outputs the delayed clock signal without delaying the clock signal when the point where the two delayed signals are phase-mixed is near the middle between the first edges of the two delayed signals. Circuit. The method of claim 6, wherein the control circuit, Controlling the auxiliary phase shifter to delay and output the clock signal by the predetermined time when the point where the two delayed signals are phase-mixed is near the edge of any one of the first edges of the two delayed signals. A delayed synchronous loop circuit. The method of claim 1, wherein the coarse delay line includes a plurality of unit coarse delay cells connected in series, and the plurality of delay signals are output from the plurality of unit coarse delay cells. Delayed synchronization loop circuit. 10. The delay lock loop as recited in claim 9, wherein the two delay signals are signals output from two adjacent delay cells of the plurality of unit coarse delay cells. A delay having a coarse delay line for receiving an input signal and sequentially delaying the unit delay time to output a plurality of delay signals, and a phase mixer for phase blending two selected delay signals from the plurality of delay signals. In the jitter reduction method of a synchronous loop circuit, (a) detecting whether the delay locked loop circuit is initially locked; (b) providing the input signal of the coarse delay line without delaying the clock signal when the delay lock loop circuit is not initially locked; And (c) when the delay lock loop circuit is initially locked, the phase mixer detects a point where the two delay signals are phase mixed and accordingly results in the input of the coarse delay line without delaying the clock signal. Providing as a signal or delaying the clock signal by a predetermined time to provide the signal as the input signal of the coarse delay line. 12. The method of claim 11, wherein the predetermined time is half of the unit delay time. The method of claim 12, wherein step (c) comprises: Providing as the input signal of the coarse delay line without delaying the clock signal when the point where the two delayed signals are phase-mixed is near the middle between the first edges of the two delayed signals; And When the point where the two delayed signals are phase-mixed is near the edge of any one of the first edges of the two delayed signals, the clock signal is delayed by the predetermined time as the input signal of the coarse delay line. And reducing the jitter.

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