KR100858879B1 - Register controlled Delay locked loop - Google Patents

Abstract

The present invention relates to a register control delay locked loop which reduces the locking time and reduces the size of the shift register and the delay unit. To this end, the present invention provides an output stage for outputting an internal clock in response to an external clock; Displacement means for shifting a phase by receiving the external clock ECLK; Main phase comparison means for receiving the external clock and the internal clock of the output terminal and comparing phases with each other; Subphase comparison means for receiving an output signal of the displacement means and an internal clock of the output terminal and comparing phases with each other; Selection means for receiving an output signal of the external clock and the displacement means, selecting one of the output signals of the external clock and the displacement means and being controlled by the output signals of the main phase comparison means and the subphase comparison means; Delay means for delaying the output of said selection means; And a shift register which is controlled by an output of the main phase comparing means and adjusts a delay amount of the delay means.

Synchronous memory, delay lock loop, DL, register DL

Description

Register controlled delay locked loop             

1 is a block diagram showing an RDLL according to the prior art;

2 is a circuit diagram showing a delay unit in the RDLL according to the prior art;

3 is a block diagram conceptually illustrating an RDLL of the present invention;

4 is a block diagram illustrating an RDLL according to an embodiment of the present invention;

5 is a truth table relating to the operation of a decoder in a circuit according to an embodiment of the present invention;

Fig. 6 is a diagram showing the phase difference between an external clock signal and an internal clock signal in coordinates.

* Explanation of symbols for main parts of the drawings

310: delay unit 320: main phase comparator

330: sub phase comparator 340: shift register

350: selection unit 360: phase shift unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register controlled delay locked loop (hereinafter referred to as RDLL) used in a synchronous memory device operating at high speed, and more particularly, to an RDLL capable of fast locking of an RDLL. will be.

In general, each of the functional blocks of a synchronous semiconductor memory device reads or writes data from a memory cell in synchronization with a clock. The clock signal uses a clock signal provided from a clock generator. In a synchronous semiconductor memory device, a clock having a specific period is used to compensate for a skew between the clock signal and data and skew or another clock signal. Doing.

In particular, in memory devices such as synchronous DRAM (hereinafter referred to as SDRAM) or double data rate SDRAM (hereinafter referred to as DDR SDRAM) or system ICs (integrated circuits), skew between clock signals ( To compensate for skew, delay locked loop (DLL) is used.

In general, a DLL is a device that generates an internal clock signal consistent with a phase of an input clock signal despite a delay caused by a change in the surrounding environment with respect to a clock signal input from the outside. Referring to FIG. The RDLL circuit according to the prior art will be described.

As shown in FIG. 1, the RDLL receives the external clock signal ECLK and delays the external clock signal ECLK by a predetermined time according to the output of the shift register 104 to convert the internal clock signal ICLK. A phase comparator 102 for receiving an output delay unit 101, an external clock signal ECLK and an internal clock signal ICLK, and comparing phases with each other and outputting a result of the comparison, and the phase comparator 102 And a shift register 104 for outputting a plurality of control signals for controlling the delay time of the delay unit 101 after performing the shift operation in response to the output of the?

FIG. 2 is a diagram illustrating the configuration of the delay unit 101 shown in FIG. 1, wherein the delay unit 101 includes a unit delay unit including one NAND gates ND21 to ND2n and one inverter INV1 to INVn. 201, 202, and 20n and a plurality of flip-flops (FF1 to NR1) that receive, latch, and output shift left (SHL1 to SHLn) signals or shift write (SHR1 to SHRn) signals that are output signals of the shift register 104. FFn) and NAND gates ND1 to NDn that receive the outputs of the plurality of flip-flops and the external clock signal ECLK and output them to the unit delay units 201, 202, and 20n.

The operation of the conventional RDLL circuit constructed as described above is as follows.

The external clock signal ECLK is delayed by a predetermined time through the delay unit 101 and output as the internal clock signal ICLK. In this case, the delay time through the delay unit 101 is determined by the phase comparator 102.

As a result of the phase comparison in the phase comparator 102, when the internal clock signal is slower than the external clock signal, the phase comparator 102 outputs a corresponding phase comparison result to the shift register 104, and the shift register 104 In response to the signal, the delay time in the delay unit 101 is adjusted to synchronize the two clocks.

Even when the internal clock signal is faster than the external clock signal, the shift register 104 similarly adjusts the delay time of the delay unit 101 in response to the output of the phase comparator 102 to synchronize the external clock signal with the internal clock signal. do.

In current RDLL, the clock is locked by delaying the input signal unconditionally at the beginning. The delay in the delay part is not designed to delay half of one cycle of the clock signal. It is designed to delay the above values.

In the conventional RDLL circuit operating as described above, when the phase difference between the external clock signal and the internal clock signal is large, there is a problem in that it takes a long time to synchronize the two clock signals. That is, there is a problem in that the locking time is long.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to provide a register control delay lock loop which shortens the locking time and reduces the size of the delay unit and the shift register.

The present invention for achieving the above object, the output stage for outputting the internal clock in response to the external clock; Displacement means for shifting a phase by receiving the external clock ECLK; Main phase comparison means for receiving the external clock and the internal clock of the output terminal and comparing phases with each other; Subphase comparison means for receiving an output signal of the displacement means and an internal clock of the output terminal and comparing phases with each other; Selection means for receiving an output signal of the external clock and the displacement means, selecting one of the output signals of the external clock and the displacement means and being controlled by the output signals of the main phase comparison means and the subphase comparison means; Delay means for delaying the output of said selection means; And a shift register which is controlled by an output of the main phase comparing means and adjusts a delay amount of the delay means.

The present invention reduces the locking time of the delay lock loop by using not only an external clock signal but also a 90 ° shifted phase of the external clock signal as a control signal. Invention reduced to / 4.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

3 is a block diagram conceptually illustrating an RDLL according to the present invention.

Referring to FIG. 3, the RDLL includes an output terminal for outputting the internal clock ICLK in response to the external clock ECLK, a displacement unit 360 for shifting the phase by receiving the external clock ECLK, and an external clock. The main phase comparator 320 for receiving the ECLK and the internal clock ICLK of the output stage and comparing the phases with each other, and the output signal of the displacement unit 360 and the internal clock ICLK of the output stage are inputted. The external clock is controlled by the output signal of the sub phase comparison unit 330, the external clock ECLK and the displacement unit 360 to be compared, and is controlled by the output signals of the main phase comparison unit 320 and the sub phase comparison unit 330. The control unit 350 selects and outputs any one of the output signals of the over-displacement means, a delay unit 310 delaying the output of the selector 350, and a delay controlled by the output of the main phase comparator 320. It comprises a shift register 340 for adjusting the delay amount of the unit 310.

According to the present invention having the configuration as described above can significantly reduce the delay amount in the delay unit, for example, if the external clock (ECLK) and the internal clock (ICLK) has a skew with a 90 ° phase difference, conventionally In the technique, locking is possible only when a delay value corresponding to “90 ° + skew” is given by the delay unit. However, in the present invention, locking can be performed by giving only a delay value corresponding to “skew”. This is because the external clock ECLK is first shifted by the 90 ° phase difference in the displacement unit 360, and the shifted value is selected by the selection unit 350 to be delayed in the delay unit.

As a result, according to the present invention, the locking time can be greatly reduced, and the elements used in the delay unit 310 and the shift register 340 can be greatly reduced.

In the present invention of FIG. 3, when the output signal of the external clock ECLK and the displacement unit 360 are inverted, respectively, and the inverting element is further provided to the selector 350, the selector 350 has a 270 ° phase difference. When the displacement part 360 is a 90 ° shifter-the effect of the present invention can be doubled because it can preferentially export the delayed value.

In addition, in the present invention of Figure 3, the displacement portion 360 is composed of a plurality of shifters for shifting the phase value of the external clock (ECLK) to a value between 0 ° and 180 °, sub-phase ratio assignment portion 330 In addition, if a plurality of phase comparators corresponding to the shifter are configured, the locking time can be faster and the area of the delay unit and the shifter register can be greatly reduced.

4 is a circuit block diagram of an RDLL according to an embodiment of the present invention, and includes a first phase comparator 302 for receiving an external clock signal ECLK and an internal clock signal ICLK and comparing the phases of the two signals; A second phase comparator 303 which receives the internal clock signal ICLK and the external clock signal ECLK shifted in phase by 90 °, and compares the phases of the two signals; and an inverting and outputting the external clock signal ECLK. 1 the inverter 307, the second inverter 308 which inverts and outputs the external clock signal ECLK whose phase is shifted by 90 degrees, and the output A of the first phase comparator and the output of the second phase comparator ( A decoder 305 for outputting any one of four signals having an external clock signal ECLK and a phase difference of 0 °, 90 °, 180 °, and 270 ° using B) as a control signal, and the decoder 305 A delay unit 301 for receiving the output of the first phase comparator 302 and outputting the delayed output A of the first phase comparator 302 and the first phase comparator 302. The shift register 304 is controlled by the output A to control the delay amount of the delay unit 301.

The operation of the circuit according to the embodiment of the present invention having such a configuration will be described with reference to FIGS. 5 and 6. 5 illustrates outputs of the decoder selected according to the output signals A and B of the first phase comparator 302 and the second phase comparator 303 and the output signals of the first to second phase comparators shown in FIG. 6 is a diagram illustrating the phase difference between the external clock signal ECLK and the internal clock signal ICLK in coordinates.                     

First, referring to the definition of the output signal of the first phase comparator 302, when the internal clock signal ICLK is slower than the external clock signal ECLK, A, the output signal of the first phase comparator 302, is low. If the internal clock signal ICLK is faster than the external clock signal ECLK, the output signal A of the first phase comparator 302 is at a high level (hereinafter referred to as '0'). , '1').

Similarly, referring to the definition of the output signal of the second phase comparator 303, B, the output signal of the second phase comparator 303, is compared with the external clock signal ECLK having the internal clock signal ICLK shifted by 90 °. When it is slow, it is set to '0', and when the internal clock signal ICLK is faster than the external clock signal ECLK shifted by 90 °, the output signal B of the second phase comparator 303 is equal to '1'. It was set to.

A phase difference between the internal clock signal ICLKL and the external clock signal ECLK will be described with reference to FIG. 6 as follows. 6 illustrates an internal clock signal ICLK having a phase difference of θ when the X axis is the external clock signal ECLK in the X and Y coordinate systems, and an external clock signal ECLK shifted by 90 degrees.

If the internal clock signal ICLK is slower than the external clock signal ECLK, θ has a range of 0 ° to 180 °, that is, the internal clock signal ICLK is located in the first or second quadrant. Can be.

In addition, when the internal clock signal ICLK is faster than the external clock signal ECLK, θ has a range of 180 ° to 360 °, that is, the internal clock signal ICLK is located in the third or fourth quadrant. Can be.                     

Similarly, when the internal clock signal ICLK is slower than the external clock signal ECLK shifted by 90 °, θ has a range of 90 ° to 2700 °, that is, the internal clock signal ICLK is located in the second or third quadrant. It can be seen that.

In addition, when the internal clock signal ICLK is faster than the external clock signal ECLK shifted by 90 °, θ has a range of 270 ° to 90 °, that is, the internal clock signal ICLK is displayed in one or four quadrants. You can see that it is located.

In the circuit defined as above, a case in which A, which is an output of the first phase comparator 302, is '0' and an output of the second phase comparator 303, is '0', will be described below.

A is '0' because the internal clock signal ICLK is slower than the external clock signal ECLK. Therefore, the internal clock signal ICLK is located in one or two quadrants, and B is '0'. Since the internal clock signal ICLK is slower than the 90 shifted external clock signal ECLK, the internal clock signal ICLK is located in the second or third quadrant.

Since the internal clock signal having the phase difference satisfying the above two conditions is located in the quadrant, the output of the decoder 305 under the control of the two signals A and B becomes the external clock signal ECLK shifted by 90 ° and is delayed. 301 is entered.

Unlike the prior art, the delay unit 301 delays the external clock signal shifted by 90 ° to synchronize the internal clock signal located in two quadrants, thereby reducing the locking time.

Next, consider the case where A is '0' and B is '1'.

In this case, the internal clock signal is located in quadrant 1 and 2 as a result of the comparison with the external clock signal, and in the quadrant 1 and 4 according to the comparison with the external clock signal shifted by 90 °. Therefore, since the internal clock signal satisfying the two conditions is located in one quadrant, the output of the decoder 305 becomes an unshifted external clock signal.

Next, consider the case where A is '1' and B is '0'.

In this case, the internal clock signal is located in the third and fourth quadrants according to the comparison with the external clock signal and in the second and third quadrants according to the comparison with the external clock signal shifted by 90 °. Therefore, since the internal clock signal satisfying the two conditions is located in the quadrant three, the output of the decoder 305 becomes an external clock signal shifted by 180 degrees and is input to the delay unit 301.

Next, consider the case where A is '1' and B is '1'.

In this case, the internal clock signal is located in quadrant 3 and 4 according to the comparison with the external clock signal, and in the quadrant 1 and 4 according to the comparison with the external clock signal shifted by 90 °. Therefore, since the internal clock signal satisfying the two conditions is located in the quadrant, the output of the decoder 305 becomes an external clock signal shifted by 270 ° and is input to the delay unit 301.

The shift register 304 performs a shift write or shift left operation under the control of the output signal A of the first phase comparator 302, which is the same as the conventional art. There is an advantage that can be reduced to 1/4.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

The present invention can quickly reduce the area of the delay line and the shift register while quickly taking the locking time of the RDLL, it is possible to implement a high-speed operation and high integration of the RDLL.

Claims (7)

An output stage for outputting an internal clock in response to the external clock; Displacement means for shifting a phase by receiving the external clock ECLK; Main phase comparison means for receiving the external clock and the internal clock of the output terminal and comparing phases with each other; Subphase comparison means for receiving an output signal of the displacement means and an internal clock of the output terminal and comparing phases with each other; Selection means for receiving an output signal of the external clock and the displacement means, selecting one of the output signals of the external clock and the displacement means and being controlled by the output signals of the main phase comparison means and the subphase comparison means; Delay means for delaying the output of said selection means; And A shift register controlled by an output of the main phase comparing means to adjust a delay amount of the delay means; The resist control delay locked loop comprising a. The method of claim 1, And inverting means for inverting the output signal of the external clock and the displacement means to provide to the selection means. The method of claim 2, And the displacement means comprises a plurality of shifters for shifting the phase value of the external clock to a value between 0 ° and 180 °. The method of claim 3, The subphase comparison means includes a plurality of phase comparators corresponding to the shifter, And each of the phase comparators receives a signal provided from the corresponding shifter and an internal clock of the output stage, and compares phases with each other and outputs a signal to the selection means. The method according to any one of claims 1 to 4, The selection means, A decoder which receives an output signal of the external clock and the displacement means, selects and outputs one of the output signals of the external clock and the displacement means under control of the output signals of the main phase comparison means and the subphase comparison means; A resist control delay locked loop, characterized in that. In the delay lock loop to compensate for skew of the external clock and the internal clock, Displacement means for shifting the phase of the external clock by 90 °; A first phase comparator that receives the external clock and the internal clock and outputs a comparison result; A second phase comparator that receives the output signal of the displacement means and the internal clock and outputs a comparison result; Receiving the output signal of the first phase comparator and the output signal of the second phase comparator as a control signal and outputs any one of the signal of the phase shifted 0 °, 90 °, 180 ° or 270 ° of the external clock Decoder; A shift register for selecting a delay amount according to an output of the first phase comparator; And Delay means for receiving an output of the decoder and outputting an internal clock by subtracting a delay amount according to the output of the shift register; A register control delay lock loop configured to include. The method of claim 6, And a second inverter for inverting the external clock signal and outputting the inverted clock signal to the decoder and a second inverter for inverting and outputting the 90 ° shifted upper clock signal to the decoder. Loop.

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