KR20080010145A - Liquid crystal display panel and method for manufacturing the same - Google Patents

Abstract

A liquid crystal display panel and a method for manufacturing the same are provided to form a cutoff layer on gate lines and under pixel electrodes, to prevent a fringe electric field applied to liquid crystals and to prevent light leakage, thereby improving display quality. A color filter substrate(20) includes a black matrix(215) formed on an upper substrate(200) for dividing sub pixel areas, color filters(221) formed at the sub pixel areas, and a common electrode(251) covering the black matrix and the color filters. A thin film transistor substrate(10) is opposite to the color filter substrate, having liquid crystals(50) between the color filter substrate and the thin film transistor substrate, and includes first gate lines and second gate lines(113), data lines crossing the first and second gate lines to form sub pixel areas, first thin film transistors connected with the first gate lines and the data lines, second thin film transistors(152) connected with the second gate lines and the data lines, pixel electrodes(170) formed at the sub pixel areas and including first and second pixel parts(173,175) connecting with the first and second thin film transistors respectively, and cut patterns(171) formed between the first and second pixel parts for controlling an alignment direction of the liquid crystals. A cutoff layer is formed on one of the upper substrate and a lower substrate(100) to overlap one of the color filter substrate and the thin film transistor substrate with one of the first and second gate lines and the cut patterns.

Description

Liquid crystal display panel and manufacturing method thereof {LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME}

1 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating cut planes of I-I 'and II-II' shown in FIG. 1.

3A is a cross-sectional view illustrating an electric field between a pixel electrode and a gate line according to an exemplary embodiment of the present invention.

3B is a cross-sectional view illustrating an electric field between a blocking layer and a gate line according to an exemplary embodiment of the present invention.

4 is a plan view illustrating a liquid crystal display panel according to a second exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating cut planes of II ′ and II-II ′ of FIG. 4.

6 is a cross-sectional view of a liquid crystal display panel according to a third exemplary embodiment of the present invention, taken along the line I-I 'and II-II' of FIG. 4.

7A and 7B are cross-sectional views illustrating a method of manufacturing a liquid crystal display panel according to an exemplary embodiment of the present invention through the cut planes of lines II ′ and II-II ′ of FIG. 4.

<Explanation of symbols for the main parts of the drawings>

10: thin film transistor substrate 20: color filter substrate

50: liquid crystal 100: lower substrate

111: first gate line 113: second gate line

114: gate electrode 121: data line

151: first thin film transistor 152: second thin film transistor

153: gate insulating film 154: active layer

155: ohmic contact layer 157: source electrode

159: drain electrode 161: protective film

170: pixel electrode 171: incision pattern

173: first pixel portion 175: second pixel portion

191,210: blocking layer 200: upper substrate

215: black matrix 221: color filter

241: overcoat 251: common electrode

The present invention relates to a liquid crystal display panel, and more particularly, to a liquid crystal display panel in which a blocking layer is formed to prevent light leakage in the vertical alignment mode.

The liquid crystal display panel forms an electric field in the liquid crystal by applying a voltage to the common electrode and the pixel electrode, and adjusts the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal to obtain a desired image.

As a representative wide viewing angle technology of the liquid crystal display panel, a multi-domain vertical alignment (VA) mode is used. In VA mode, liquid crystal molecules having negative dielectric anisotropy are vertically oriented and driven perpendicular to the electric field direction to adjust light transmittance.

In the liquid crystal display panel, an S-PVA (Super-Patterned Vertical Aligment) mode has been developed in which a high gradation region and a low gradation region are divided into sub-pixels in a zigzag structure to improve visibility by gradation mixing between two gradation regions.

The liquid crystal display panel of the S-PVA mode is formed on the lower plate, and the gate line for supplying the gate voltage to the thin film transistor and the patterned pixel electrode drive the liquid crystal display panel with the organic layer interposed therebetween according to the gate on and off voltages. Form an electric field. The fringe electric field does not control the behavior of the liquid crystal in the portion where the pattern of the pixel electrode is formed, causing light leakage.

An object of the present invention is to provide a liquid crystal display panel in which a blocking layer is formed to prevent light leakage caused by a fringe electric field between a gate line and a pixel electrode in a vertical alignment mode.

In order to achieve the above technical problem, the present invention includes a black matrix formed on an upper substrate to separate sub pixel regions, a color filter formed in the sub pixel regions, and a common electrode formed to cover the black matrix and the color filters. A sub-pixel region intersecting each of the first and second gate lines and the first and second gate lines formed on the lower substrate, facing the color filter substrate, the color filter substrate and the liquid crystal interposed therebetween. A first thin film transistor connected to a data line, the first gate line and the data line, a second thin film transistor connected to the second gate line and the data line, and formed in the sub pixel area, and the first and second thin film transistors A pixel electrode including first and second pixel portions connected to each other, and formed between the first and second pixel portions And a thin film transistor substrate including a cutting pattern for adjusting an alignment direction of the liquid crystal, wherein any one of the color filter substrate and the thin film transistor substrate overlaps the cutting pattern with any one of the first and second gate lines. Accordingly, a liquid crystal display panel having a blocking layer formed on at least one of the upper substrate and the lower substrate is provided.

More specifically, the blocking layer is formed so as to float above the first and second gate lines and below the cutting pattern.

Here, the blocking layer is formed on the same plane as the data line with the same metal as the data line.

In addition, the blocking layer is formed on the same plane as the black matrix of the same material as the black matrix.

In this case, the blocking layer is formed in at least one of a circle, an ellipse, a polygon.

The blocking layer may include a first blocking layer formed on the same plane as the data line and made of the same metal as the data line, and a second blocking layer formed on the same plane as the black matrix and made of the same material as the black matrix. It includes.

In order to achieve the above technical problem, the present invention provides a data line and a first gate line intersecting each of the first and second gate lines, the first and second gate lines formed on a lower substrate, and providing a sub pixel region. And a first thin film transistor connected to a data line, a second thin film transistor connected to the second gate line and a data line, and a first thin film transistor formed in the sub-pixel region and connected to the first and second thin film transistors, respectively. A first step of providing a thin film transistor substrate including a pixel electrode including two pixel portions, a cutout pattern formed between the first and second pixel portions to separate the first and second pixel portions, and formed on an upper substrate facing the lower substrate; A black matrix dividing the sub pixel region, a color filter formed in the sub pixel region, the pixel electrode, and an electric field R includes a second step of providing a color filter substrate including a common electrode, and a third step of bonding the thin film transistor substrate and the color filter substrate with a liquid crystal interposed therebetween, among the first and second steps. One step includes forming a blocking layer on at least one of the upper substrate and the lower substrate so as to overlap one of the first and second gate lines and the cutting pattern. To provide.

More specifically, the blocking layer is formed so as to float above the first and second gate lines and below the cutting pattern.

Here, the blocking layer is formed on the same plane as the data line with the same metal as the data line.

In addition, the blocking layer is formed on the same plane as the black matrix of the same material as the black matrix.

The blocking layer may include a first blocking layer formed on the same plane as the data line and made of the same metal as the data line, and a second blocking layer formed on the same plane as the black matrix and made of the same material as the black matrix. It includes.

Other objects and features of the present invention in addition to the above object will become apparent from the description with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 7B.

1 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating cut planes of lines II ′ and II ′ of FIG. 1. 3A is a cross-sectional view illustrating an electric field between a pixel electrode and a gate line according to an exemplary embodiment of the present invention, and FIG. 3B is a cross-sectional view illustrating an electric field between a blocking layer and a gate line according to an exemplary embodiment of the present invention.

1 to 3B, a liquid crystal display panel according to an exemplary embodiment of the present invention includes a black matrix 215 formed on the upper substrate 200 to separate sub pixel regions, a color filter 221 formed on a sub pixel region, The color filter substrate 20 including the black matrix 215 and the common electrode 251 formed to cover the color filter 221 and the color filter substrate 20 and the liquid crystal 50 are faced with each other. A data line 121 and a first gate line 111 intersecting with the first and second gate lines 111 and 113 and the first and second gate lines 111 and 113 formed on the substrate 100 to form a sub-pixel region. And the first thin film transistor 151 connected to the data line 121, the second gate line 113, and the second thin film transistor 152 connected to the data line 121, and are formed in the sub pixel area. And first and second pixel units 173 and 175 connected to the second thin film transistors 151 and 152, respectively. And a thin film transistor substrate 10 including a cutting pattern 171 formed between the pixel electrode 170 and the first and second pixel units 173 and 175 to control the alignment direction of the liquid crystal 50. Any one of the color filter substrate 20 and the thin film transistor substrate 10 may overlap the upper substrate 200 and the lower substrate 100 to overlap one of the first and second gate lines 111 and 113 and the cutout pattern 171. ) And blocking layers 191 and 210 formed on at least one of the substrates.

Specifically, the liquid crystal 50 is a difference between the common voltage from the common electrode 251 of the color filter substrate 20 and the data voltage from the first and second pixel portions 173 and 175 of the thin film transistor substrate 10. It rotates by adjusting the transmittance of light supplied from the backlight assembly (not shown).

The color filter substrate 20 includes a black matrix 215 formed to prevent light leakage, a color filter 221 formed to implement color, and a step generated in a crossover region of the black matrix 215 and the color filter 221. And an overcoat 241 for removing a common electrode and a common electrode 251 for applying a common voltage to the liquid crystal 50.

The black matrix 215 is formed of an opaque organic material or an opaque metal to prevent light from being emitted through a region in which the liquid crystal 50 cannot be controlled. The color filter 221 is formed under the black matrix 215 and includes red, green, and blue color filters to implement color. The overcoat 241 is formed of a transparent organic material and protects the color filter 221 and the black matrix 215 and is formed for good step coverage and insulation of the common electrode 251. The common electrode 251 is formed of a transparent metal such as indium tin oxide (ITO) or indium zinc oxide (IZO). In addition, the common electrode 251 uses an electric field formed by a voltage difference between a common voltage supplied from the common voltage generator and a data voltage of the first and second pixel units 173 and 175 formed on the thin film transistor substrate 10 to be described later. 50). Here, the common electrode 251 includes a pattern formed by protrusions or grooves to provide a wide viewing angle of the liquid crystal display panel. The pattern is formed to correspond to each of the first and second pixel units 173 and 175. The common electrode 251 having the pattern and the first and second pixel units 173 and 175 each form a fringe electric field due to a voltage difference.

The thin film transistor substrate 10 includes first and second gate lines 111 and 113, a data line 121 crossing the first and second gate lines 111 and 113 to form a sub pixel region, and a first gate line. A first thin film transistor 151 connected to the 111 and the data line 121, a second thin film transistor 152 connected to the second gate line 113 and the data line 121, and a first thin film transistor 152 connected to the data line 121. And is formed between the first pixel portion 173 connected to the thin film transistor 151, the second pixel portion 175 connected to the second thin film transistor 152, and the first and second pixel portions 173 and 175. It includes a cutting pattern 171 for adjusting the alignment direction of the liquid crystal 50.

The first and second gate lines 111 and 113 may be formed in a single layer or multiple layers, and may be formed in parallel with each other. In addition, gate electrodes 114 are formed in the first and second gate lines 111 and 113, respectively.

The data line 121 is formed of a single layer or multiple layers and vertically crosses the first and second gate lines 111 and 113.

The first and second thin film transistors 151 and 152 include a gate electrode 114, a gate insulating layer 153, an active layer 154, an ohmic contact layer 155, a source electrode 157, and a drain electrode 159. Here, as illustrated in FIG. 2, the second thin film transistor 152 will be described as a reference.

The gate electrode 114 is formed on the second gate line 113 and protrudes from the second gate line 113. The gate electrode 114 turns on / turns off the second thin film transistor 152 using the gate on / off voltage from the second gate line 113. The gate insulating layer 153 is formed on the second gate line 113 and the gate electrode 114 to insulate the second gate line 113 and the gate electrode 114. The active layer 154 is formed of amorphous silicon to form a channel of the second thin film transistor 152. The ohmic contact layer 155 is formed for ohmic contact between the source electrode 157 and the drain electrode 159 and the active layer 154. The source electrode 157 supplies the data voltage from the data line 121 to the drain electrode 159 via the channel of the second thin film transistor 152 when the second thin film transistor 152 is turned on. The drain electrode 159 supplies the data voltage transferred from the source electrode 157 to the second pixel portion 175.

The passivation layer 183 is formed to cover the second thin film transistor 152 and the gate insulating layer 153, and insulates the second thin film transistor 152 from the first and second pixel units 173 and 175.

The first and second pixel units 173 and 175 are formed of a transparent metal such as indium zinc oxide (IZO) or indium tin oxide (ITO), and are connected to the drain electrode 159. The first and second pixel units 173 and 175 form an electric field with the common electrode 251 through the data voltage supplied from the drain electrode 159 to drive the liquid crystal 50.

The cutout patterns 171 formed between the second gate line 113 and the first and second pixel units 173 and 175 overlap each other, as illustrated in FIGS. 3A and 3B. In this case, when the gate-off voltage is applied to the second gate line 113 when the liquid crystal display panel is driven, an electric field is formed between the second gate line 113 and the first and second pixel electrodes 170.

For example, in the liquid crystal display panel, 6V is applied to the common electrode 251 and 6V is applied to the second pixel electrode 170 to display black, so that the liquid crystal 50 is vertically aligned. In this case, when a gate-off voltage of −7 V is applied to the second gate line 113, an electric field is formed between the second gate line 113 and the first and second pixel electrodes 170, and the electric field is a vertically aligned liquid crystal. It is applied to 50 to make it impossible to control the behavior of the liquid crystal 50.

In this case, the light source supplied to the liquid crystal display panel is transmitted to the first and second pixel electrodes 170 while passing through the liquid crystal display panel except for the light blocked by the second gate line 113. Therefore, the light sources passing through the first and second pixel electrodes 170 are supplied to the uncontrolled liquid crystal 50 to generate light leakage. In addition, since the brightness of black increases due to light leakage in the contrast ratio represented by Equation 1, the contrast ratio is lowered.

Here, in the liquid crystal display panel according to the present invention, as shown in FIGS. 2 and 3B, the blocking layer 191 is formed on the upper side of the second gate line 113 and the lower side of the cutout pattern 171. In this case, the blocking layer 191 is formed to float. The blocking layer 191 is formed on the same plane as the data line 121 and made of the same metal as the data line 121. The blocking layer 191 is formed by patterning an upper side of the gate insulating layer 153 when the source and drain electrodes 159 are formed, and forms an electric field with the second gate line 113 to form the first and second pixel portions 173 and 175. And the electric field between the second gate line 113 is prevented. Accordingly, the blocking layer 191 prevents light leakage caused by failure to control the liquid crystal 50 by an electric field between the second gate line 113 and the first and second pixel units 173 and 175, and the contrast ratio of the liquid crystal display panel. To prevent the fall.

4 is a plan view illustrating a liquid crystal display panel according to a second exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view illustrating cut planes of lines II ′ and II ′ of FIG. 4.

4 and 5, the liquid crystal display panel according to the present invention except that the blocking layer 210 is formed on the color filter substrate 20 as compared to the liquid crystal display panel shown in FIGS. 1 and 2. With the same components. Therefore, detailed description of the same components will be omitted.

The blocking layer 210 may block light leakage generated at a portion where the first and second gate lines 111 and 113 and the cutting pattern 171 overlap the thin film transistor substrate 10. It is formed on the color filter substrate 20 provided above the 111,113 and the cutting pattern 171. Here, the blocking layer 210 is formed on the same plane as the black matrix and made of the same material as the black matrix 215. The black matrix 215 is formed in at least one of a circle, an ellipse, and a polygon.

6 is a cross-sectional view of a liquid crystal display panel according to a third exemplary embodiment of the present invention, taken along the line I-I 'and II-II' of FIG. 4.

Referring to FIG. 6, in the liquid crystal display panel according to the present invention, the blocking layer may have a thin film transistor substrate 10 and a color filter substrate 20 as compared with the liquid crystal display panel shown in FIGS. 1 and 2, respectively. The same components are provided except that the barrier layers 191 and 210 are formed. Therefore, detailed description of the same components will be omitted.

The first blocking layer 191 overlaps the first and second gate lines 111 and 113 in the thin film transistor substrate 10, and is disposed above the first and second gate lines 111 and 113 and below the cut pattern 171. It is formed by floating. In this case, the first blocking layer 191 is formed on the same plane as the data line 121 and made of the same metal as the data line 121. In addition, the first blocking layer 191 prevents an electric field from being generated between the first and second gate lines 111 and 113 and the first and second pixel units 173 and 175.

In addition, the second blocking layer 210 is the same material as the black matrix 215 on the upper side of the first and second gate lines 111 and 113 and the cutout pattern 171 in the color filter substrate 20 and is coplanar with the black matrix. It is formed in at least one of the shape of a circle, oval, polygon. The second blocking layer 210 blocks light leakage caused by poorly controlled liquid crystal.

7A and 7B are cross-sectional views illustrating a method of manufacturing a liquid crystal display panel according to an exemplary embodiment of the present invention through the cut planes of lines II ′ and II-II ′ of FIG. 4.

Referring to FIG. 7A, a first step of a method of manufacturing a liquid crystal display panel according to an exemplary embodiment of the present invention may include first and second gate lines 111 and 113 and first and second gate lines formed on the lower substrate 100. A data line 121, a first gate line 111, a first thin film transistor 151, a second gate line 113 connected to the data line 121 to cross the 111 and 113, respectively, and provide a sub pixel area; A pixel including the second thin film transistor 152 connected to the data line 121 and the first and second pixel parts 173 and 175 formed in the sub pixel area and connected to the first and second thin film transistors 151 and 152, respectively. A cutting pattern 171 formed between the electrode 170 and the first and second pixel units 173 and 175 to separate the first and second pixel portions 173 and 175, and overlaps the first and second gate lines 111 and 113 and the cutting pattern 171, respectively. The blocking layer 191 is formed above the second gate lines 111 and 113 and below the cutting pattern 171. To prepare a thin film transistor substrate 10 comprising a.

Specifically, the metal deposited on the lower substrate 100 is patterned to form first and second gate lines 111 and 113. The gate electrodes 114 protruding from the first and second gate lines 111 and 113 are formed to define the first and second thin film transistors 151 and 152.

Next, SiNx or the like is deposited on the entire lower substrate 100 of the thin film transistor substrate 10 on which the gate pattern is formed by plasma chemical vapor deposition to form the gate insulating layer 153, the active layer 154, and the ohmic contact layer 155. The metal is deposited to form the source electrode 157, the drain electrode 159, and the first blocking layer 191.

The gate insulating layer 153 is formed on the gate pattern layer. An amorphous silicon film is formed on the gate insulating film 153, and an active layer 154 and an ohmic contact layer 155 are formed to form the first and second thin film transistors 151 and 152. A metal is deposited on the gate insulating layer 153, the active layer 154, and the ohmic contact layer 155, and then patterned to form a source electrode 157 and a drain electrode 159. In this case, the first blocking layer 191 is patterned and floated on the same plane using the same material as the source electrode 157 and the drain electrode 159.

Next, the first and second thin film transistors 151 and 152 and the first blocking layer 191 are protected and insulated by the spin coating method on top of the first and second thin film transistors 151 and 152 and the first blocking layer 191. A protective film 161 is formed. A portion of the passivation layer 161 is removed to form a contact hole exposing a portion of the drain electrode 159.

The pixel electrode is formed on the passivation layer 161. Here, the pixel electrode forms a cutout pattern 171 to divide the pixel electrode into the first and second pixel units 173 and 175. The first and second pixel units 173 and 175 are connected to the drain electrode 159 through the contact hole.

Next, a second step of the manufacturing method of the liquid crystal display panel will be described with reference to FIG. 7B.

The second step is a black matrix 215 formed on the upper substrate 200 facing the lower substrate 100 to separate the sub pixel regions, a color filter 221 formed on the sub pixel region, and a pixel electrode 170. A color filter substrate including a common electrode 251 forming an electric field is prepared.

The color filter substrate is formed from the top to the bottom of the color filter substrate shown in FIG. 6 in the manufacturing process.

An opaque organic material or an opaque metal is coated on the upper substrate 200 and then photolithography or patterned to form the black matrix 215. Here, the second blocking layer 210 is formed on the upper substrate 200 so as to overlap the first and second gate lines 111 and 113 and the cutting pattern 171 of the lower substrate 100.

After the black matrix 215 is formed, the color filter 221 is formed to implement color. The color filter 221 is formed in the order of red, green, and blue by a photolithography method. An overcoat 241 is formed on the surface of the color filter 221 for the protection of the color filter 221 and for good step coverage in forming the common electrode 251. The overcoat 241 forms acrylic resin etc. by the spin coating method. The common electrode 251 is formed on the overcoat 241 using a transparent conductive material such as ITO or IZO.

Next, the third step of the manufacturing method of the liquid crystal display panel is injected and sealed so as to inject and seal the liquid crystal between the thin film transistor substrate and the color filter substrate provided through the first and second steps.

As described above, the liquid crystal display panel according to the present invention forms a blocking layer on the upper side of the gate line and the lower side of the pixel electrode when driving in the vertical alignment mode to prevent the fringe electric field applied to the liquid crystal. The liquid crystal display panel prevents light leakage by controlling the behavior of the liquid crystal by preventing a fringe electric field applied to the liquid crystal. In addition, the liquid crystal display panel prevents light leakage by forming a blocking layer over the gate line and the pixel electrode. The liquid crystal display panel improves display quality by preventing a decrease in contrast ratio due to light leakage at the initial stage of driving.

While the present invention described above has been described with reference to a preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the technical field described in the claims to be described later and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

A color filter substrate including a black matrix formed on an upper substrate to separate sub pixel regions, a color filter formed in the sub pixel region, and a common electrode formed to cover the black matrix and the color filters; A data line facing each other with the color filter substrate and the liquid crystal interposed therebetween, the data line crossing the first and second gate lines and the first and second gate lines formed on the lower substrate to form a sub-pixel region; A first thin film transistor connected to a gate line and a data line, a second thin film transistor connected to the second gate line and a data line, and a first thin film transistor formed in the sub-pixel region and connected to the first and second thin film transistors, respectively. And a thin film transistor substrate including a pixel electrode including a second pixel portion, and a cutting pattern formed between the first and second pixel portions to adjust an alignment direction of the liquid crystal. Any one of the color filter substrate and the thin film transistor substrate includes a blocking layer formed on at least one of the upper substrate and the lower substrate so as to overlap one of the first and second gate lines and the cutting pattern. A liquid crystal display panel characterized in that. The method of claim 1, And the blocking layer is formed so as to float above the first and second gate lines and below the cutting pattern. The method of claim 2, And wherein the blocking layer is formed of the same metal as the data line and formed on the same plane as the data line. The method of claim 1, The blocking layer is formed of the same material as the black matrix and formed on the same plane as the black matrix. The method of claim 1, And the blocking layer is formed in at least one of a circle, an ellipse, and a polygon. The method of claim 1, The blocking layer includes a first blocking layer formed of the same metal as the data line and coplanar with the data line; And a second blocking layer formed of the same material as the black matrix and formed on the same plane as the black matrix. First and second gate lines formed on a lower substrate, a data line crossing each of the first and second gate lines to form a sub pixel region, a first thin film transistor connected to the first gate line and the data line, A second thin film transistor connected to the second gate line and a data line, a pixel electrode formed in the sub pixel area and connected to the first and second thin film transistors, respectively; And a first step of providing a thin film transistor substrate formed between the second pixel portions and including a cutout pattern that separates them. Providing a color filter substrate including a black matrix formed on an upper substrate facing the lower substrate and separating a sub pixel region, a color filter formed in the sub pixel region, and a common electrode forming an electric field with the pixel electrode; Two steps; And a third step of bonding the thin film transistor substrate and the color filter substrate to each other with a liquid crystal interposed therebetween, wherein any one of the first and second steps includes any one of the first and second gate lines. And forming a blocking layer on at least one of the upper substrate and the lower substrate so as to overlap the pattern. The method of claim 7, wherein And wherein the blocking layer is formed to float above the first and second gate lines and below the cutting pattern. The method of claim 8, And the blocking layer is formed of the same metal as the data line and coplanar with the data line. The method of claim 7, wherein And wherein the blocking layer is formed of the same material as the black matrix and coplanar with the black matrix. The method of claim 7, wherein The blocking layer includes a first blocking layer formed of the same metal as the data line and coplanar with the data line; And a second blocking layer formed on the same plane as the black matrix and made of the same material as the black matrix.

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