TWI418878B - Display substrate, method of manufacturing the same and display device having the same - Google Patents

Description

Display substrate, manufacturing method thereof and display device including display substrate

The present invention relates to a display substrate, a display substrate manufacturing method, and a display device including the display substrate. More specifically, the present invention relates to a display substrate capable of reducing a rear image to improve image display quality, a display substrate manufacturing method, and a display device including the display substrate.

An electronic device such as a notebook computer, a monitor, a television receiver, or the like includes a display device for displaying an image. The display device may be a flat panel display device such as a liquid crystal display (LCD) device, an organic light emitting display (OLED) device, or the like.

The LCD device includes a lower substrate including a thin film transistor (TFT), an upper substrate including a color filter facing the lower substrate, and a liquid crystal layer interposed between the lower substrate and the upper substrate.

The lower substrate includes an insulating substrate, a signal line, a TFT, a pixel electrode, etc. to independently drive a plurality of pixels. The signal line, the TFT, and the pixel electrode are formed on the insulating substrate. The upper substrate includes a color filter layer and a common electrode. The color filter layer includes a red filter, a green filter, and a blue filter. The common electrode faces the pixel electrode.

The image display quality of the LCD device varies based on the alignment between the lower substrate and the upper substrate. That is, when the lower substrate is misaligned with respect to the upper substrate, the image display quality of the LCD device deteriorates.

In order to prevent image display quality deterioration of an LCD device, an LCD device including an array color filter (COA) structure has been designed. In an LCD device containing a COA structure, a color filter layer containing red, green, and blue filters is generally formed on the lower substrate.

The color filter layer of the LCD device including the COA structure contacts an alignment layer via an opening between adjacent pixel electrodes. The ionic particles in the color filter layer may migrate into the liquid crystal layer via the alignment layer, thereby deteriorating the electrical and optical characteristics of the liquid crystal in the liquid crystal layer. This can lead to undesirable phenomena.

The present invention provides a display substrate having improved image display quality and reduced image problems.

The present invention provides a method of manufacturing the above display substrate.

The present invention provides a display device including the above display substrate.

A display substrate according to an aspect of the present invention comprises a thin film transistor layer, a color filter layer, a plurality of pixel electrodes, a first cover layer and a pair provided in a gap between adjacent pixel electrodes Quasi-layer. The thin film transistor layer includes a plurality of pixel regions. A color filter layer is formed on the thin film transistor layer. A pixel electrode is formed on the color filter layer. At least one gap is defined between adjacent pixel electrodes. The first cover layer covers a portion of the color filter layer that is exposed by a gap between adjacent pixel electrodes. An alignment layer is formed on the pixel electrode and the first cap layer.

A display substrate manufacturing method according to another aspect of the present invention is provided as follows. A thin film transistor layer including a plurality of pixel regions is formed on an insulating substrate. A color filter layer is formed on the thin film transistor layer. A plurality of pixel electrodes are formed on the color filter layer. A first cover layer covering a portion of the color filter layer is formed between the pixel electrodes. An alignment layer is formed on the pixel electrode and the first cap layer.

A display device according to still another aspect of the present invention includes a display substrate, an opposite substrate, and a liquid crystal layer interposed between the display substrate and the opposite substrate. The display substrate comprises a thin film transistor layer, a color filter layer, a plurality of pixel electrodes, at least one gap between adjacent pixel electrodes, a cover layer and a first alignment layer. The thin film transistor layer includes a plurality of pixel regions arranged in a matrix shape. A color filter layer is formed on the thin film transistor layer. A pixel electrode is formed on the color filter layer. A cap layer is provided in a gap between adjacent pixel electrodes and covers a portion of the color filter layer exposed by a gap between the adjacent pixel electrodes. The first alignment layer is formed on the pixel electrode and the cap layer. The opposite substrate is combined with the display substrate and faces the display substrate. The liquid crystal layer is interposed between the display substrate and the opposite substrate.

The opposite substrate may include a common electrode formed on the insulating substrate facing the display substrate, and a second alignment layer is formed on the common electrode.

According to the display substrate, the display substrate manufacturing method, and the display device including the display substrate of the present invention, the color filter layer is spaced apart from the alignment layer to reduce the rear image, thereby improving image display quality.

The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention. However, the invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete, and the scope of the invention is fully conveyed by those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to as "on" or "an" or "an" The layers may be directly connected or coupled to another element or layer or an intervening element or layer may be present. In contrast, when an element is referred to as "directly on" another element or layer, "directly connected" to another element or layer or "directly coupled" to another element or layer, there are no intervening elements or layers. The same numbers refer to the same elements throughout the text. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

It will be understood that the terms "first", "second", "third", etc. are used to describe various elements, components, regions, layers and/or sections, but such elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed hereinafter may be referred to as a second element, component, region, layer or section, without departing from the teachings of the invention.

Spatially relative terms such as "below", "under", "lower", "on", "higher" and the like may be used herein for the purpose of description. The relationship between one of the elements or features described in the formula and the other element(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation in addition to the orientation depicted in the drawings. For example, elements that are described as "under" or "below" or "an" or "an" Thus, the exemplary term "under" can encompass "upper" and "lower" orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments, and is not intended to As used herein, the singular " " " " " " It will be further understood that the term "comprising", when used in the specification, is intended to mean the presence of the recited features, integers, steps, operations, components and/or components, but does not exclude one or more other features, integers, steps, The presence or addition of operations, components, components, and/or groups thereof.

Embodiments of the present invention are described herein with reference to the cross-section illustrations of the preferred embodiments (and intermediate structures) of the invention. Also, variations in the shape of the description, for example, of the manufacturing techniques and/or tolerances are contemplated. Thus, the embodiments of the invention should not be construed as being limited to the specific shapes of the regions described herein. For example, an implanted region illustrated as a rectangle typically contains circular or curved features and/or an implant concentration gradient at its edges rather than a binary change from the implanted region to the non-implanted region. Likewise, the embedded region formed by implantation can result in some implantation in the region between the buried region and the surface through which implantation takes place. Therefore, the regions illustrated in the drawings are intended to be illustrative, and are not intended to limit the scope of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning meaning It should be further appreciated that terms such as those terms defined in the commonly used dictionary should be interpreted to include meanings consistent with their meaning in the context of the relevant art, and should not be in an idealized or overly formal sense. Interpreted unless explicitly defined as such herein.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a plan view showing a display substrate in accordance with an embodiment of the present invention. Figure 2 is a cross-sectional view taken along line I-I' shown in Figure 1.

Referring to FIGS. 1 and 2 , the substrate 100 includes a thin film transistor (TFT) layer 280 , a color filter layer 120 , a pixel electrode layer 130 , a first cap layer 141 , and a first alignment layer 150 . The TFT layer 280 includes an insulating substrate 110 and a pixel layer 200.

The insulating substrate 110 contains a transparent material and may be formed of, for example, a glass substrate.

The pixel layer 200 is formed on the insulating substrate 110. The pixel layer 200 includes a plurality of pixel regions P1 and P2 arranged in a matrix shape on the insulating substrate 110.

The pixel layer 200 includes a plurality of gate lines 220, a gate insulating layer 230, a plurality of data lines 240, a TFT 250, and a passivation layer 260. Alternatively, the pixel layer may further include a plurality of TFTs.

The gate line 220 on the insulating substrate 110 separates a first pixel region P1 from an adjacent third pixel region (not shown) under the first pixel region P1 (see a perspective view as shown in FIG. 1).

A gate insulating layer 230 is formed on the insulating layer 110 and covers the gate line 220. The gate insulating layer 230 contains an insulating material such as tantalum nitride (SiNx), yttrium oxide (SiOx), or the like. The thickness of the gate insulating layer 230 can be, for example, about 4,500 .

The data line 240 on the gate insulating layer 230 separates the adjacent first and second pixel regions P1 and P2.

One of the TFTs 250 is formed in the first pixel region P1 and is electrically connected to the gate line 220 and the data line 240. The TFT 250 applies an image signal to the first pixel electrode PE1 via the data line 240 based on a scan signal applied to the TFT 250 via the gate line 220. The other TFT (not shown) in the second pixel region P2 applies an image signal to the first via another data line (not shown) based on the scan signal applied to the TFT (not shown) via the gate line 220. Two pixel electrode PE2.

The TFT 250 includes a gate electrode 251, an active layer 252, a source electrode 253, and a drain electrode 254.

The gate electrode 251 is electrically connected to each of the gate lines 220 and serves as one of the gate terminals of the TFT 250.

The active layer 252 is formed on the gate insulating layer 230 corresponding to the gate electrode 251. The active layer 252 includes a semiconductor layer 252a and an ohmic contact layer 252b. The semiconductor layer 252a may include amorphous germanium (a-Si). The ohmic contact layer 252b can be made of n+ impurity implanted with n+ impurity at a high concentration.

The source electrode 253 is electrically connected to each of the data lines 240 and extends to an upper portion of the active layer 252. The source electrode 253 serves as one of the source terminals of the TFT 250.

The germanium electrode 254 is formed on the active layer 252 and spaced apart from the source electrode 253. The germanium electrode 254 serves as one of the TFTs 250. The germanium electrode 254 is electrically connected to the first pixel electrode PE1 via a contact hole 122 formed through the passivation layer 260 and the color filter layer 120.

A source electrode 253 and a germanium electrode 254 are formed on the active layer 252, and a region between the source electrode 253 and the germanium electrode 254 defines a channel of the TFT in the semiconductor layer 252a.

A passivation layer 260 is formed on the gate insulating layer 230 and covers the data line 240 and the TFT 250. The passivation layer 260 contains an insulating material such as tantalum nitride (SiNx), yttrium oxide (SiOx), or the like. The thickness of the passivation layer 260 can be about 2,000 .

The pixel layer 200 can further include a storage line 270 and a storage electrode 272. A storage line 270 is formed between the gate lines 220 and extends generally parallel to the gate lines 220. The storage electrode 272 is electrically connected to the storage line 270. A storage electrode 272 is formed in each of the first pixel regions P1. The storage line 270 and the storage electrode 272 may be formed of the same layer as the gate line 220. The storage electrode 272 is formed opposite to the gate electrode 254 with respect to the gate insulating layer 230 to form a storage capacitor Cst. The storage capacitor Cst holds the image signal applied to the first pixel electrode PE1 via the TFT 250 during a frame.

The color filter layer 120 is formed on the pixel layer 200. The color filter layer 120 includes a red (R) color filter, a green (G) color filter, and a blue (B) color filter. In detail, a first color filter 120a is formed in the first pixel region P1, and a second color filter 120b is formed in the second pixel region P2. The color filter layer 120 disposed on the pixel layer 200 has a predetermined pattern such that the R, G, and B color filters are uniformly arranged. Alternatively, the color filter layer 120 may further include a transparent color filter for displaying white light.

The pixel electrode layer 130 includes a first pixel electrode PE1 and a second pixel electrode PE2 formed in the first pixel region P1 and the second pixel region P2, respectively. In detail, the first pixel electrode PE1 is formed on the first color filter 120a in the first pixel region P1. The first pixel electrode PE1 is electrically connected to the drain electrode 254 of the TFT 250 via a contact hole 122 formed through the passivation layer 260 and the first color filter 120a.

The pixel electrode layer 130 contains a transparent conductive material such as indium zinc oxide (IZO), indium tin oxide (ITO), or the like.

A gap is formed in the pixel electrode layer 130 at a boundary between the adjacent pixel electrodes PE1 and PE2. That is, the pixel electrodes PE1 and PE2 in the pixel electrode layer 130 are electrically and physically disconnected at portions corresponding to the gate line 220 and the data line 240. Therefore, the color filter layer 120 between the pixel electrodes PE1 and PE2 is exposed via a space corresponding to the gate line 220 and the data line 240.

The first cover layer 141 covers a portion of the color filter layer 120 exposed between the pixel electrodes PE1 and PE2. That is, the first capping layer 141 is formed on the portion of the color filter layer 120 corresponding to the gate line 220 and the data line 240. The first cover layer 141 prevents direct contact between the color filter layer 120 and the alignment layer 150 via the gap between the pixel electrodes PE1 and PE2.

The first cover layer 141 substantially covers the entire exposed area between the pixel electrodes PE1 and PE2. The first cover layer 141 may have a thickness of about 0.4 μm to about 0.6 μm, and the first cover layer 141 may have a width of about 5 μm to about 8 μm.

The first cover layer 141 may include a photocurable resin or a thermosetting resin. When the first cover layer 141 contains a photocurable resin, the first cover layer 141 may be formed using a photolithography process. In this case, the photocurable resin may comprise a negative photoresist and a positive photoresist. In addition, when the first cover layer 141 contains a thermosetting resin, the first cover layer 141 may be formed using an inkjet deposition process or a lithography process. In the inkjet deposition process, a thermosetting resin is deposited on the color filter layer 120 between the pixel electrodes PE1 and PE2. In the lithography process, a thermosetting resin is printed on the color filter layer 120 between the pixel electrodes PE1 and PE2.

The alignment layer 150 is formed on the pixel electrode layer 130 and the first cap layer 141. The alignment layer 150 is aligned with the liquid crystal molecules disposed on the upper surface of the alignment layer 150.

The display substrate 100 may further include a pillar spacer 142 to maintain a cell gap between the display substrate 100 and an opposite substrate (not shown). The pillar spacer 142 protrudes from the display substrate 100 in a region where the gate line 220 intersects the data line 240 and has a height greater than that of the first cover layer 141. A pillar spacer 142 may be formed on the TFT 250. For example, the pillar spacers 142 can have a height of from about 1.0 μm to about 1.5 μm and a width of from about 10 μm to about 15 μm.

The pillar spacers 142 may be formed generally of the same layer as the first cap layer 141 and may comprise a material substantially the same as the first cap layer 141 such as a negative photoresist, a positive photoresist, or the like. In other embodiments, other types of structures, such as spherical structures, may be used to maintain the gap between the display substrate 100 and the opposing substrate.

Figure 3 is a plan view showing a display substrate in accordance with another embodiment of the present invention. The display substrate of FIG. 3 is substantially the same as the display substrate of FIGS. 1 and 2 except for the pixel electrodes. Therefore, the same reference numerals will be used to refer to the same or similar parts as those described in FIGS. 1 and 2, and any further description about the above elements will be omitted.

Referring to FIGS. 2 and 3, the first pixel electrode PE1 includes an opening 132 that divides the first pixel region P1 into a plurality of domains. Alternatively, the first pixel electrode PE1 may further include a plurality of openings 132 dividing the first pixel region P1 into a plurality of domains. The liquid crystals in each of the domains are arranged in different directions from each other by the opening 132 of the first pixel electrode PE1, thereby increasing the viewing angle of the display device.

The display substrate 100 can further include a color filter layer 120 (shown in FIG. 2) and a second cover layer 144. The second cover layer 144 covers a portion of the color filter layer 120 that is exposed through the opening 132 in the first pixel electrode PE1. The second cap layer 144 prevents direct contact between the color filter layer 120 and the alignment layer 150 via the opening 132 in the first pixel electrode PE1.

The second cover layer 144 may be formed of substantially the same layer as the first cover layer 141 and the pillar spacers 142, and may include substantially the same material as the first cover layer 141 and the pillar spacers 142.

4 to 7 are cross-sectional views illustrating a method of manufacturing the display substrate shown in Figs. 1 and 2.

Referring to FIGS. 1 and 4, a pixel layer 200 having a plurality of pixel regions P1 and P2 arranged in a matrix shape is formed on an insulating substrate 110.

More specifically, a first metal layer is deposited on the insulating substrate 110. The first metal layer is partially etched through a photolithography process to form a gate line 220 and a gate electrode 251. A plurality of gate lines 220 and a plurality of gate electrodes 251 may be formed from the first metal layer.

The gate line 220 defines a boundary between a first pixel region P1 and a third pixel region (not shown) under the first pixel region P1 (see a perspective view as shown in FIG. 1). The gate electrode 251 is electrically connected to the gate line 220 to serve as one of the gate terminals of the TFT 250. The storage line 270 and the storage electrode 272 may be formed on the insulating substrate 110 by a layer substantially the same as the gate line 220 and the gate electrode 251. Alternatively, the storage line and the storage electrode including the transparent conductive material may be formed through an additional process to improve the aperture ratio of each of the pixel regions P1 and P2.

A gate insulating layer 230 may be formed on the insulating substrate 110 to cover the gate lines 220 and the gate electrodes 251 formed on the insulating substrate 110. The gate insulating layer 230 may include, for example, tantalum nitride (SiNx) or hafnium oxide (SiOx), and may have about 4,500 The thickness.

Referring to FIGS. 1 and 5, a semiconductor layer 252a and an ohmic contact layer 252b are sequentially formed on the gate insulating layer 230. The semiconductor layer 252a includes amorphous germanium (a-Si), and the ohmic contact layer contains n+ amorphous germanium (n+a-Si). The semiconductor layer 252a and the ohmic contact layer 252b are partially etched via a photolithography process to form an active layer 252 corresponding to the gate electrode 251.

A second metal layer is deposited on the gate insulating layer 230 and the active layer 252. The second metal layer is partially etched through the photolithography process to form a drain line 240, a source electrode 253, and a drain electrode 254. Alternatively, a plurality of drain lines 240, a plurality of source electrodes 253, and a plurality of germanium electrodes 254 may be formed from the second metal layer.

The data line 240 defines a boundary between the first pixel region P1 and a second pixel region P2 adjacent to a side portion of the first pixel region P1. The source electrode 253 is spaced apart from the data line 240 and serves as one of the source terminals of the TFT 250. The germanium electrode 254 is spaced apart from the source electrode 253 and serves as one of the TFTs 250. The drain electrode 254, the storage electrode 272, and the gate insulating layer 230 form a storage capacitor Cst.

The ohmic contact layer 252b between the source electrode 253 and the drain electrode 254 is etched to expose a portion of the semiconductor layer 252a between the source electrode 253 and the drain electrode 254.

Referring to FIGS. 1 and 6, a passivation layer 260 is formed on the gate insulating layer 230, the data line 240, the source line 253, and the drain electrode 254. The passivation layer 260 contains an insulating material such as tantalum nitride (SiNx), yttrium oxide (SiOx), or the like. The thickness of the passivation layer 260 can be about 2,000 .

A color filter layer 120 is formed on the passivation layer 260. The color filter layer 120 includes a red (R) color filter, a green (G) color filter, and a blue (B) color filter. Each of the R, G, and B color filters corresponds to each of the pixel regions P1 and P2.

A contact hole 122 is formed through the color filter layer 120 and the passivation layer 260, and the drain electrode 254 is partially exposed via the contact hole 122. Alternatively, a plurality of contact holes may be formed through the color filter layer 120 and the passivation layer 260.

Referring to FIGS. 1 and 7, a transparent conductive layer is formed on the color filter layer 120. The transparent conductive layer is partially etched to form a first pixel electrode PE1 and a second pixel electrode PE2 corresponding to the pixel regions P1 and P2, respectively. Thus, the pixel electrode layer 130 is formed.

The pixel electrode layer 130 contains a transparent conductive material such as indium zinc oxide (IZO), indium tin oxide (ITO), or the like.

The first pixel electrode PE1 is electrically connected to the drain electrode 254 via a contact hole 122 formed through the color filter layer 120 and the passivation layer 260.

The first cap layer 141 may be formed in a region between the pixel electrodes PE1 and PE2, and the pillar spacers 142 may be formed in a region corresponding to the TFT 250. The first cover layer 141 covers an exposed portion of the color filter layer 120 between the pixel electrodes PE1 and PE2.

The first capping layer 141 is formed on the color filter layer 120 on a portion corresponding to the gate line 220 and the data line 240 between the adjacent pixel electrodes PE1 and PE2. The first cover layer 141 substantially covers the entire exposed portion of the color filter layer 120 between the pixel electrodes PE1 and PE2. For example, the first cover layer 141 may have a thickness of about 0.4 μm to about 0.6 μm and a width of about 5 μm to about 8 μm.

The pillar spacers 142 protrude from the display substrate 100 in a region where the gate lines 220 and the data lines 240 intersect, and include a height greater than that of the first cladding layer 141. A pillar spacer 142 may be formed on the TFT 250. For example, column spacers 142 can comprise a height of from about 1.0 μm to about 1.5 μm and a maximum width of from about 10 μm to about 15 μm.

Applying a photocurable resin layer containing a negative photoresist or a positive photoresist characteristic to the color filter layer 120 including the pixel electrodes PE1 and PE2 formed thereon, and the photocurable resin The layers are partially removed via a light process to form a first cover layer 141 and column spacers 142. Alternatively, the first cover layer 141 comprising a thermosetting resin may be formed via an inkjet deposition process or a lithography process. The first cover layer containing various materials may be formed through various methods to prevent impurities of the color filter layer 120 from migrating via the alignment layer 150.

Referring again to FIGS. 1 and 2, an alignment layer 150 is formed on the pixel electrode layer 130 including the first cladding layer 141 and the pillar spacers 142 formed thereon. The pixel electrode layer 130 and the first cap layer 141 are interposed between the alignment layer 150 and the color filter layer 120 to prevent direct contact between the alignment layer 150 and the color filter layer 120.

Referring again to FIG. 3, an opening 132 is formed in the pixel electrode layer 130 that divides each of the pixel regions into a plurality of domains, thereby increasing the viewing angle. Alternatively, a plurality of openings 132 may be formed in each of the pixel electrodes PE1 and PE2.

When the opening 132 is formed in the first pixel electrode PE1, a second capping layer 144 is formed on the opening 132 to cover a portion of the color filter layer 120 exposed through the opening 132. The second cap layer 144 prevents direct contact between the color filter layer 120 and the alignment layer 150 via the opening 132 of the first pixel electrode PE1. The second cover layer 144 may be formed of substantially the same layer as the first cover layer 141 and the pillar spacers 142, and may include substantially the same material as the first cover layer 141 and the pillar spacers 142. The second cover layer 144 may be formed simultaneously with the first cover layer 141 and the column spacers 142.

Figure 8 is a cross-sectional view showing a display substrate in accordance with another embodiment of the present invention. In detail, Fig. 8 is a cross-sectional view showing the line II-II' shown in Fig. 3. Therefore, the same reference numerals will be used to refer to the same or similar parts to those described in FIG. 3, and any further description about the above elements will be omitted.

Referring to FIG. 3 and FIG. 8 , the display substrate comprises a thin film transistor layer 280 , a color filter layer 120 , a pixel electrode layer 130 , a first cover pattern 141 a and a second cover pattern 141 b , and a second cover layer 144 . And an alignment layer 150.

The thin film transistor layer 280 includes an insulating substrate 110 and a pixel layer 200 formed on the insulating substrate 110. The pixel layer 200 includes a plurality of gate lines 220, a gate insulating layer 230, a plurality of data lines 240, a thin film transistor 250, and a passivation layer 260. The thin film transistor layer 280 of FIG. 8 is substantially identical to the thin film transistor layer of FIG. Therefore, any further description about the above elements will be omitted.

The color filter layer 120 is formed on the pixel layer 200. The color filter layer 120 includes a plurality of color filters 120a and 120b. In FIGS. 3 and 8, the first color filter 120a formed in the first pixel region P1 includes a second pixel region P2 adjacent to the first pixel region P1 on the opposite side of the data line 240. The second color filter 120b has a different color.

The first color filter 120a formed in the first pixel region P1 and the third color filter 120a' formed in the third pixel region P3 adjacent to the first pixel region P1 on the opposite side of the gate line 220 color[? , different colors] are roughly the same. That is, the first color filter 120a and the third color filter 120a' are formed in the first pixel region P1 and the third pixel region P3, respectively, and the second color filter 120b is formed in the second pixel region P2. in.

The portion of the color filter layer 120 corresponding to the boundary between the pixel regions P1, P2 and P3 is removed to form a recess. In detail, the portion of the first color filter 120a corresponding to the first boundary region B1 between the first pixel region P1 and the third pixel region P3 is removed to form the first groove H1, and the color filter The layer 120 is overlapped between the first color filter 120a and the second color filter 120b in the second boundary region B2 (which is located between the first pixel region P1 and the second pixel region P2). Remove to form the second groove H2. In addition, the first color filter 120a is corresponding to the portion of the opening 132 that divides each of the pixel regions P1, P2, and P3 into a plurality of domains to form a third recess on the third boundary region B3. Slot H3.

When the first cover pattern 141a and the second cover pattern 141b and the second cover layer 144 are not formed on the color filter layer 120, impurities may pass through the first boundary region B1, the second boundary region B2, and the third boundary region B3. The color filter layer 120 is discharged. However, in FIG. 8, portions of the color filter layer 120 corresponding to the first boundary region B1, the second boundary region B2, and the third boundary region B3 are removed, and the first cover pattern 141a and the second cover pattern 141b and The second cover layer 144 covers the regions such that the image phenomenon can be reduced by the impurities.

Alternatively, only the first groove H1 and the second groove H2 may be formed in the first boundary region B1 and the second boundary region B2. Only the second groove H2 may also be formed in the second boundary region B2. Alternatively, the depth of each of the grooves H1, H2, and H3 may be substantially the same as the depth of the color filter layer 120. The depth of each of the grooves H1, H2, and H3 may also be less than the thickness of the color filter layer 120.

The pixel electrode layer 130 is patterned to form pixel electrodes PE1, PE2, and PE3 corresponding to the pixel regions P1, P2, and P3. In detail, the first pixel electrode PE1 is located in the first pixel region P1, and the second pixel electrode PE2 is located in the second pixel region P2. The third pixel electrode PE3 is located in the third pixel region P3. An opening 132 is formed in each of the pixel electrodes PE1, PE2, and PE3 to form a domain in each of the pixel regions P1, P2, and P3. The germanium electrode 254 of the thin film transistor 250 is electrically connected to each of the pixel electrodes PE1, PE2, and PE3 via the contact hole 122.

The first cover layer includes a first cover pattern 141a and a second cover pattern 141b. The first cover pattern 141a is formed in the first boundary region B1 to fill the first recess H1 and cover the end portions of the first pixel electrode PE1 and the third pixel electrode PE3 adjacent to each other. The second cover pattern 141b is formed in the second boundary region B2 to fill the second recess H2 and cover the end portions of the first pixel electrode PE1 and the second pixel electrode PE2 adjacent to each other. The first cover pattern 141a and the second cover pattern 141b prevent the color filter layer 120 from being exposed.

Each of the first cover pattern 141a and the second cover pattern 141b may have a height on the pixel electrode layer 130 of about 0.4 μm to about 0.6 μm, and each of the first cover pattern 141a and the second cover pattern 141b The width can be from about 5 μm to about 8 μm. Each of the first cover pattern 141a and the second cover pattern 141b may include a substantially flat upper surface. In FIG. 8, the first cover pattern 141a and the second cover pattern 141b do not affect the operation of the liquid crystal. That is, the first cover pattern 141a and the second cover pattern 141b are located in the area of the non-controllable liquid crystal. Each of the first cover pattern 141a and the second cover pattern 141b may include a substantially flat surface. Alternatively, each of the first and second overlay patterns can have a variety of shapes.

The pillar spacers 142 may be substantially formed of the same layer as the first and second capping patterns 141a, 141b and may include substantially the same material as the first and second capping patterns 141a, 141b. The column spacers 142 may have a height of from about 1.0 μm to about 1.5 μm, and the column spacers 142 may have a maximum width of from about 10 μm to about 15 μm.

The second cap layer 144 is formed in the third boundary region B3 to fill the third recess H3 and cover a portion of the first pixel electrode PE1 adjacent to the opening 132. The second cover layer 144 prevents the color filter layer 120 from being exposed.

In FIG. 8, a second capping layer 144 is formed in each of the pixel regions P1, P2, and P3 (where the operation of the liquid crystal is controlled). The second cover layer 144 may have a substantially peak shape including a side surface formed at an angle of about 12 to 15 degrees with respect to the upper surface of the color filter layer 120 (as illustrated in FIG. 8). The perspective is shown). The two side surfaces meet at a peak in the middle of the second cover layer 144. The height and width of the second cover layer 144 can be determined by the depth, width and angle of inclination of the opening 132. For example, the height of the second cap layer 144 on the pixel electrode layer 130 may be about 0.4 μm to about 0.6 μm, and the width of the second cap layer 144 may be about 5 μm to about 10 μm.

The alignment layer 150 is formed on the pixel electrode layer 130, the pillar spacers 142, the first and second capping patterns 141a, 141b, and 144b. The alignment layer 150 is aligned with the liquid crystal to form a predetermined direction. The first cover pattern 141a and the second cover pattern 141b and the second cover layer 144 prevent impurities from the color filter layer 120 from reaching the alignment layer 150.

9 to 13 are cross-sectional views illustrating a method of manufacturing the display substrate shown in Fig. 8.

Referring to FIGS. 3 and 9, a pixel layer 200 including a plurality of pixel regions arranged in a matrix shape is formed on an insulating substrate 110. The process for forming the pixel layer 200 of FIG. 9 is substantially the same as the process of FIG. Therefore, the same reference numerals will be used to refer to the same or the same parts as those described in FIG. 7, and any further description about the above elements will be omitted.

A color filter layer 120 is formed on the insulating substrate 110 including the passivation layer 260. In detail, a plurality of color filters are formed on the insulating substrate 110 to form the color filter layer 120.

In detail, a red color filter layer is formed on the insulating substrate 110 and patterned to form a red color filter in one of the pixel regions. A green color filter layer is formed on the insulating substrate 110 and patterned to form a green color filter in the other of the pixel regions. A blue color filter layer is formed on the insulating substrate 110 and patterned to form a blue color filter in the other of the pixel regions.

In FIG. 9, a monochrome color filter 120a is formed in the first boundary region B1 on the gate line 220, and color filters 120a and 120b having colors different from each other are formed on the data line 240. In the second boundary area B2.

Referring to Figures 3 and 10, a contact hole 122 is formed to expose an electrode 254 of a thin film transistor. In addition, the color filters 120a and 120b located on the first boundary region B1, the second boundary region B2, and the third boundary region B3 are partially removed to form a first groove H1, a second groove H2, and a third recess. Slot H3. The first groove H1, the second groove H2, and the third groove H3 may be formed in contact with the hole 122.

For example, the color filters 120a and 120b may be partially removed such that the passivation layer 260 is exposed via the first recess H1, the second recess H2, and the third recess H3. The pixel electrode layer 130 is deposited on the insulating substrate 110. The insulating substrate 110 is formed with a contact hole 122 and a first groove H1, a second groove H2 and a third groove H3. The pixel electrode layer 130 is electrically connected to the germanium electrode 254 via the contact hole 122.

In FIG. 10, the first groove H1, the second groove H2, and the third groove H3 are formed during the same process steps as forming the contact holes. Alternatively, the first recess H1 and the third recess H3 are formed during the same process steps as the formation of the color filters 120a and 120b, and only the second recess H2 is formed in the same process step as the contact hole. of.

Referring to FIGS. 3 and 11, the pixel electrode layer 130 is patterned to form a first pixel electrode PE1, a second pixel electrode PE2, and a third pixel electrode PE3. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are formed in a first pixel region P1, a second pixel region P2, and a third pixel region P3, respectively. That is, the pixel electrode layers 130 corresponding to the first boundary region B1, the second boundary region B2, and the third boundary region B3 are partially removed to form the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode. PE3. For example, a protrusion having a substantially meandering shape is formed in the opening 132 of the pixel electrode layer 130, and the width of the opening 132 may be about 1 μm to about 5 μm, thereby increasing the aperture of the pixel regions P1, P2, and P3. ratio.

Referring to FIGS. 3 and 12, a photocurable resin layer 140 is formed on the insulating substrate 110 including the patterned pixel electrode layer 130. The photocurable resin formed on the insulating substrate 110 may include a negative photoresist or a positive photoresist. The photocurable resin layer 140 fills the first recess H1, the second recess H2, and the third recess H3, and covers the color filter layer 120.

The photocurable resin layer 140 is patterned using the mask 400 to form a first cover pattern 141a and a second cover pattern 141b, a pillar spacer 142, and a second cover layer 144. The first cover pattern 141a and the second cover pattern 141b are formed in the first boundary region B1 and the second boundary region B2 between the pixel electrodes PE1, PE2, and PE3. A pillar spacer 142 is formed on the thin film transistor 250. The second cover layer 144 is formed in the third boundary region B3 corresponding to the opening 132.

In detail, the mask 400 includes a slit portion 421, a first transmissive portion 422, and a second transmissive portion 424. The slit portion 421 corresponds to the first boundary region B1 and the second boundary region B2. The first transmissive portion 422 corresponds to the column spacer 142. The second transmissive portion 424 corresponds to the second cover layer 144 and is smaller than the first transmissive portion 422.

Referring to FIG. 3, FIG. 12 and FIG. 13, a first cover pattern 141a and a second cover pattern 141b are formed in the first boundary region B1 and the second boundary region B2 by the slot portion 421. The first cover pattern 141a and the second cover pattern 141b cover the first recess H1 and the second recess H2. Each of the first cover pattern 141a and the second cover pattern 141b protrudes from the upper surface of the color filter layer 120 and has a substantially flat upper surface. In FIG. 13, the first cover pattern 141a and the second cover pattern 141b do not affect the operation of the liquid crystal. That is, the first cover pattern 141a and the second cover pattern 141b are located in the area of the non-controllable liquid crystal. Each of the first cover pattern 141a and the second cover pattern 141b may have a substantially flat between the first pixel electrode PE1 and the third pixel electrode PE3 and between the first pixel electrode PE1 and the second pixel electrode PE2. The surface. For example, the height of each of the first cover pattern 141a and the second cover pattern 141b on the pixel electrode layer 130 may be about 0.4 μm to about 0.6 μm, and the first cover pattern 141a and the second cover pattern 141b Each of the maximum widths may range from about 5 μm to about 10 μm.

The pillar spacer 142 is formed by the first transmissive portion 442, and the second cap layer 144 is formed by the second transmissive portion 444 in the third border region B3. For example, column spacers 142 can comprise a height of from about 1.0 μm to about 1.5 μm and a maximum width of from about 10 μm to about 15 μm.

The second cover layer 144 fills the third groove H3 and protrudes from the color filter layer 120. The second cover layer 144 can have a generally meandering shape. The second cap layer 144 is formed in the first pixel region P1 to control the operation of the liquid crystal. For example, the second cover layer 144 has a generally meandering shape that includes an inclined surface that forms an angle θ of from about 12 degrees to about 15 degrees.

The second cover layer 144 covers the opening 132 having a predetermined width L to increase the response speed of the liquid crystal and increase the aperture ratio of the pixel regions P1, P2, and P3. The width L of the opening 132 and the angle θ of the 稜鏡 shape determine the height h and the width L' of the second cover layer 144. For example, the height h of the second cap layer 144 on the pixel electrode layer 130 may be about 0.4 μm to about 0.6 μm, and the maximum width L′ of the second cap layer 144 may be about 5 μm to about 10 μm.

In FIG. 13, the first cover pattern 141a and the second cover pattern 141b, the second cover layer 144, and the pillar spacer 142 may comprise substantially the same material, may be formed on substantially the same layer, and may use substantially the same optical process. And formed. Alternatively, the first cover pattern 141a and the second cover pattern 141b may be formed through an inkjet process or a lithography process using a thermosetting resin.

An alignment layer 150 (shown in FIG. 8) is formed over substantially the entire surface of the insulating substrate 110.

Figure 14 is a plan view showing a display substrate in accordance with another embodiment of the present invention. Figure 15 is a cross-sectional view taken along line III-III' of Figure 14.

Referring to FIG. 14 and FIG. 15, the display substrate comprises a thin film transistor layer 280, a color filter layer 120, a pixel electrode 130, a first cover pattern 341a and 341b, a second cover layer 344 and an alignment layer. 150.

The thin film transistor layers of Figures 14 and 15 are substantially identical to the thin film transistor layers of Figures 1 and 2. Therefore, the same reference numerals will be used to refer to the same or similar parts as those described in FIGS. 1 and 2, and any further description about the above elements will be omitted. The thin film transistor layer 280 includes an insulating substrate 110 and a pixel layer 200 on the insulating substrate 110. The pixel layer 200 includes a gate line 220, a gate insulating layer 230, a data line 240, a thin film transistor 250, and a passivation layer 260. Alternatively, the pixel layer 200 may further include a plurality of gate lines 220, a plurality of data lines 240, and a plurality of thin film transistors 250. Gate line 220 and data line 240 define a plurality of pixel regions P1, P2, and P3.

In detail, the data line 240 defines a boundary between the first pixel region P1 and an adjacent second pixel region P2, and the gate line 220 defines between the first pixel region P1 and an adjacent third pixel region P3. a boundary. A thin film transistor 250 and a storage capacitor electrode 272 electrically connected to the storage line 270 are formed in the first pixel region P1. The thin film transistor 250 includes a gate electrode 251, an active layer 252, a source electrode 253, and a germanium electrode 254.

The color filter layer 120 includes a plurality of color filters 120a and 120b respectively formed in a plurality of pixel regions. The first color filter 120a of the color filter layer 120 (when viewed from the schematic diagram illustrated in FIG. 14) is curved to have a meander shape and is located in a portion of the first pixel region P1 and the second pixel region P2. Part of it. The second color filter 120b of the color filter layer 120 (when viewed from the schematic illustrated in FIG. 14) is curved to have a meander shape and is located on a portion of the second pixel region P2. That is, the first color filter 120a and the second color filter 120b are at least partially formed in the second pixel region P2. In other words, it is possible to have several color filters in a pixel area.

A third color filter 120a' having a meander shape is formed in the third pixel region P3 when viewed from the schematic diagram illustrated in FIG. 14, and the third pixel region P3 and the first pixel region P1 are at the gate line 220. Adjacent on the opposite side. The third color filter 120a' has substantially the same shape as the first color filter 120a.

The color filter layer 120 includes a first recess H1 and a second recess H2. A portion of the first color filter layer 120a in the first boundary region B1 corresponding to the gate line 220 is removed to form a first recess H1. The first color filter 120a and the second color filter 120b are in the second boundary region B2 (the first color filter 120a and the second color filter 120b partially overlap in the second boundary region B2) A portion thereof is removed to form a second groove H2. In addition, a portion of the second color filter 120b in the third boundary region B3 corresponding to the opening 133 of the second pixel electrode P2 is removed to form a third groove H3. The second pixel electrode PE2 is formed on the second color filter 120b. In other embodiments, fewer grooves may be formed. For example, only the first groove H1 and the second groove H2 may be formed. In FIG. 15, portions of the color filter layer 120 corresponding to the first groove H1, the second groove H2, and the third groove H3 are completely removed to make the first groove H1 and the second groove H2 and Each of the third recesses H3 extends through the color filter layer 120 far enough to contact the structure below the color filter layer 120. Alternatively, portions of the color filter layer 120 corresponding to the first groove H1, the second groove H2, and the third groove H3 may be partially removed such that the first groove H1, the second groove H2, and the first The depth of each of the three grooves H3 is smaller than the thickness of the color filter layer 120.

The pixel electrode layer 130 includes a plurality of pixel electrodes PE1 and PE2 corresponding to the color filters 120a and 120b, respectively. The first pixel electrode PE1 includes an opening 133 that divides the first pixel region P1 into a plurality of domains.

In detail, the first pixel electrode PE1 is formed to have a meander shape to correspond to the meander shape of the first color filter 120a. The first pixel electrode PE1 may have substantially the same shape as the first color filter 102a (as viewed from a perspective view shown in FIG. 14). That is, the first pixel electrode PE1 is formed in the first pixel region P1 and the second pixel region P2. The second pixel electrode PE2 is formed in the second pixel region P2. The third pixel electrode PE3 is adjacent to the first pixel electrode PE1 on the opposite side of the gate line 220.

Each of the pixel electrodes PE1 and PE2 is electrically connected to the drain electrode 254 of the thin film transistor 250 via a contact hole 122.

The first cover layer includes a first cover pattern 341a and a second cover pattern 341b. The first cover pattern 341a is formed in the first boundary region B1 to fill the first groove H1 located intermediate the end portions of the adjacent first pixel electrode PE1 and the third pixel electrode PE3. For example, the height of the first cover pattern 341a on the pixel electrode layer 130 may be about 0.4 μm to about 0.6 μm, and the maximum width of the first cover pattern 341a may be about 5 μm to about 8 μm. The upper surface of the first cover pattern 341a is substantially flat. The first cover pattern 341a is formed in a region that does not affect the driving of the liquid crystal, and thus the first cover pattern 341a may include a substantially flat upper surface.

The second cover pattern 341b is formed in the second boundary region B2 to fill the second groove H2 located intermediate the end portions of the adjacent first pixel electrode PE1 and the second pixel electrode PE2. The second cover pattern 341b is formed in the second pixel region P2 (the liquid crystal is controlled in the second pixel region P2), and has a substantially 稜鏡 inclined surface including an angle of about 12 degrees to about 15 degrees. shape. For example, the height of the second cover pattern 341b on the pixel electrode layer 130 may be about 0.4 μm to about 0.6 μm, and the maximum width of the second cover pattern 341b may be about 5 μm to about 10 μm.

The pillar spacers 342 may be formed of substantially the same layers as the first cladding layers 341a and 341b, and may comprise substantially the same material. For example, the height of the column spacers 342 can be from about 1.0 μm to about 1.5 μm, and one of the column spacers 342 can have a maximum width of from about 10 μm to about 15 μm.

The second cap layer 344 is formed in the third boundary region B3 to fill the third recess H3 and cover a portion of the first pixel electrode PE1 adjacent to the opening 133.

The second cover layer 344 is formed in the second pixel region P2 (the liquid crystal is controlled therein) and has a substantially meander shape. For example, the second cover layer 344 is combined to form an inclined surface with an angle of about 12 degrees to about 15 degrees with respect to the upper surface of the color filter layer 120. The height and width of the second cover layer 344 are determined by the width of the opening 133 and the angle of the inclined surface of the opening 133. For example, the height of the second cap layer 344 on the pixel electrode layer 130 may be about 0.4 μm to about 0.6 μm, and the maximum width of the second cap layer 344 may be about 5 μm to about 10 μm.

The alignment layer 150 is formed on the pixel electrode layer 130, the pillar spacers 342, the first cladding layers 341a and 341b, and the second cladding layer 344. The alignment layer 150 aligns the liquid crystals on the alignment layer 150 in a predetermined direction. The alignment layer 150 is separated from the color filter layer 120 by the first and second cladding layers 341a, 341b and 344 and the pixel electrode layer 130. Therefore, since the cover layers 341a, 341b, and 344 are interposed between the color filter layer 120 and the alignment layer 150, such impurities do not migrate into the liquid crystal layer via the alignment layer 150.

The display substrate manufacturing method of FIGS. 14 and 15 is substantially the same as the display substrate manufacturing method of FIGS. 9 to 13 except for the second cover pattern 341b. Thus, the same reference numerals may be used to refer to the same or similar parts as those described in FIGS. 9-13, and any further description of the above elements will be omitted.

The second cover pattern 141b of Figure 13 contains a generally flat surface. However, the second cover pattern 341b of FIG. 15 has a substantially meander shape. In FIGS. 14 and 15, a second cover pattern 341b is formed between the pixel electrodes PE1 and PE2 having a meander shape so that the second cover pattern 341b is formed in the second pixel region P2. That is, the second cover pattern 341b is formed in the second pixel region P2 (the liquid crystal is controlled in the second pixel region P2) to have a shape including about 12 to about 15 with respect to the upper surface of the color filter layer 120. The substantially 稜鏡 shape of the sloping surface of the angle of the degree.

The second cover pattern 341b of FIGS. 14 and 15 is patterned via a process substantially the same as that used to pattern the second cover layer 144 of FIG. Therefore, any further description about the above elements will be omitted.

Figure 16 is a cross-sectional view showing a display device in accordance with another embodiment of the present invention.

Referring to FIG. 16, the display device 300 includes a display substrate 100, an opposite substrate 500, and a liquid crystal layer 600. The opposite substrate 500 faces the display substrate 100 and is coupled to the display substrate 100. The liquid crystal layer 600 is inserted between the display substrate 100 and the opposite substrate 500.

The display substrate 100 of FIG. 16 can be identical to the display substrate 100 described above with respect to FIGS. 1 and 2. Thus, the same reference numerals may be used to refer to the parts that are the same or similar to the parts described in FIGS. 1 and 2, and any further description of the above elements will be omitted.

The opposite substrate 500 includes an insulating substrate 510 , a common electrode 520 , and an alignment layer 530 . The common electrode 520 is formed on the insulating substrate 510. The alignment layer 530 is formed on the common electrode 520.

The common electrode 520 is formed on one surface of the insulating substrate 510 corresponding to the display substrate 100. The common electrode 520 includes a transparent conductive material to enable light to be transmitted through the opposing substrate 500. The transparent electrode 520 may include substantially the same material as the pixel electrode layer 130. Examples of the transparent conductive material that can be used for the common electrode 520 include indium zinc oxide (IZO), indium tin oxide (ITO), and the like.

The liquid crystal layer 600 includes a plurality of liquid crystals that can be disposed in a predetermined direction. The liquid crystal of the liquid crystal layer 600 contains optical characteristics such as refractive index anisotropy and electrical characteristics such as dielectric anisotropy. The configuration of the liquid crystal changes in response to an electric field applied between the pixel electrode 130 and the common electrode 520. As a result, the light transmission of the liquid crystal layer 600 can be controlled.

According to the display substrate, the display substrate manufacturing method, and the display device including the display substrate, the color filter layer formed on the display substrate is not in direct contact with the alignment layer via a gap between adjacent pixel electrodes, thereby preventing attribution due to The liquid crystal is deteriorated due to contaminants from the color filter layer. Therefore, the subsequent image is reduced by the deterioration of the liquid crystal, thereby improving the image display quality.

Further, the cover layer formed in the region of the non-controllable liquid crystal has a substantially flat shape, and the cover layer formed in the region where the liquid crystal can be controlled has a substantially meander shape. In addition, the cover layer can also control the configuration of the liquid crystal to improve the response speed of the liquid crystal.

The invention has been described with reference to example embodiments. However, it will be apparent that many alternative modifications and variations will be readily apparent to those skilled in the art from this description. Accordingly, the present invention is intended to embrace all such alternatives and modifications

100. . . Display substrate

110. . . Insulating substrate

120. . . Color filter layer

120a. . . First color filter

120a'. . . Third color filter

120b. . . Second color filter

122. . . Contact hole

130. . . Pixel electrode layer

132. . . Opening

133. . . Opening

140. . . Photocurable resin layer

141. . . First cover

141a. . . First cover pattern

141b. . . Second cover pattern

142. . . Column spacer

144. . . Second cover

150. . . First alignment layer

200. . . Pixel layer

220. . . Gate line

230. . . Gate insulation

240. . . Data line

250. . . Thin film transistor (TFT)

251. . . Gate electrode

252. . . Working layer

252a. . . Semiconductor layer

252b. . . Ohmic contact layer

253. . . Source electrode

254. . . Helium electrode

260. . . Passivation layer

270. . . Storage line

272. . . Storage electrode

280. . . Thin film transistor (TFT) layer

341a. . . First cover pattern

341b. . . Second cover pattern

342. . . Column spacer

344. . . Second cover

400. . . Mask

421. . . Slot portion

422. . . First transmissive part

424. . . Second transmission part

500. . . Relative substrate

510. . . Insulating substrate

520. . . Common electrode

530. . . Alignment layer

600. . . Liquid crystal layer

B1. . . Boundary area

B2. . . Boundary area

B3. . . Boundary area

h. . . height

H1. . . Groove

H2. . . Groove

H3. . . Groove

I-I'. . . line

II-II'. . . line

III-III'. . . line

L. . . width

L'. . . width

P1. . . Pixel area

P2. . . Pixel area

P3. . . Pixel area

PE1. . . Pixel electrode

PE2. . . Pixel electrode

PE3. . . Pixel electrode

θ. . . angle

1 is a plan view showing a display substrate according to an embodiment of the present invention; FIG. 2 is a cross-sectional view taken along line II' of FIG. 1, and FIG. 3 is a view showing another embodiment of the present invention. FIG. 4 to FIG. 7 are cross-sectional views showing a method of manufacturing the display substrate shown in FIGS. 1 and 2; FIG. 8 is a cross-sectional view taken along line II-II'. A cross-sectional view of a display substrate of an embodiment; FIGS. 9 to 13 are cross-sectional views illustrating a method of fabricating the display substrate illustrated in FIG. 8; and FIG. 14 is a view showing a display substrate according to another embodiment of the present invention. Figure 15 is a cross-sectional view taken along line III-III' of Figure 14; and Figure 16 is a cross-sectional view of a display device in accordance with another embodiment of the present invention.

122. . . Contact hole

141. . . First cover

142. . . Column spacer

220. . . Gate line

240. . . Data line

250. . . Thin film transistor (TFT)

251. . . Gate electrode

253. . . Source electrode

254. . . Helium electrode

270. . . Storage line

272. . . Storage electrode

I-I'. . . line

P1. . . Pixel area

P2. . . Pixel area

PE1. . . Pixel electrode

PE2. . . Pixel electrode

Claims (7)

A display substrate comprising: a thin film transistor layer comprising a plurality of pixel regions; a color filter layer formed on the thin film transistor layer, the color filter layer being included in the color filter layer a first recess; a plurality of pixel electrodes formed on the color filter layer, the pixel electrodes defining at least one gap between adjacent pixel electrodes corresponding to the first recess; a first cover layer in the gap between the pixel electrodes, the first cover layer covering the first groove of the color filter layer and the gap between the adjacent pixel electrodes; a pixel electrode and an alignment layer on the first cover layer; and a column spacer disposed on the color filter layer, wherein an upper end of the column spacer is higher than an upper end of the first cover layer, wherein The first cover layer comprises substantially the same material as the pillar spacer, wherein the pillar spacer is substantially formed from the same layer as the first cover layer, wherein each pixel region in the thin film transistor layer comprises: a gate on an insulating substrate Line; an intersection of the gate line and data line; and a thin film transistor is electrically connected to the gate line and the data lines of which the first covering layer includes: a first cover pattern formed in the non-controllable region corresponding to the gate lines and the data lines; and a second one of the pixel regions formed between the gate lines and the data lines a cover pattern, and wherein the first cover pattern has a substantially flat surface and the second cover pattern has a meander shape. The display substrate of claim 1, wherein the first cover layer has a height of 0.4 μm to 0.6 μm on the pixel electrodes and a width of one of the first cover layers is 5 μm to 8 μm. The display substrate of claim 2, wherein the color filter layer has a meander shape and the pixel electrode has the same shape as the color filter layer. The display substrate of claim 1, further comprising a second cover layer covering the color filter layer to expose an exposed portion via the opening, wherein each of the pixel electrodes comprises a plurality of domains separated by at least one opening, the color filter layer having a second recess corresponding to the opening, and the second cover layer being formed on the second recess to cover the exposure through the opening An exposed portion of the color filter layer. The display substrate of claim 4, wherein the second cover layer has a substantially meander shape. A display device comprising: a display substrate comprising: a thin film transistor layer comprising a plurality of pixel regions; a color filter layer formed on the thin film transistor layer, the color filter layer comprising one of the first grooves in the color filter layer; and a plurality of the plurality of color filter layers formed on the color filter layer a pixel electrode, the pixel electrode defining at least one gap between the adjacent pixel electrodes corresponding to the first groove; a cover layer provided in the gap between adjacent pixel electrodes, the cover layer covering the color filter a gap between the first groove of the photo sheet layer and the adjacent pixel electrodes; a first alignment layer formed on the pixel electrodes and the cover layer; and a color filter disposed on the color filter a column spacer on the layer, the upper end of the column spacer is higher than an upper end of the first cover layer, an opposite substrate combined with the display substrate, the opposite substrate faces the display substrate; and a display is inserted in the display a liquid crystal layer between the substrate and the opposite substrate, wherein the first cover layer comprises substantially the same material as the pillar spacer, wherein the pillar spacer is substantially formed from the same layer as the first cover layer, wherein the Each of the thin film transistor layers The prime region includes: a gate line on an insulating substrate; a data line intersecting the gate line; and a thin film transistor electrically connected to the gate line and the data line, wherein the first cover layer contain: a first cover pattern formed in the non-controllable region corresponding to the gate lines and the data lines; and a second one of the pixel regions formed between the gate lines and the data lines a cover pattern, and wherein the first cover pattern has a substantially flat surface and the second cover pattern has a meander shape. The display device of claim 6, wherein the opposite substrate comprises: a common electrode formed on an insulating substrate facing the display substrate; and a second alignment layer formed on the common electrode.