KR20080006133A - Method of manufacturing display cell - Google Patents

Abstract

A method for manufacturing a display cell is provided to minimize a misaligned margin between upper and lower plates by selectively forming the second bonding mark, which corresponds to the first bonding mark formed on a lower mother substrate, only on a local region of an upper mother substrate with a chemical vapor deposition repair equipment, forming a light shielding layer on the upper mother substrate, and omitting a patterning process for the light shielding layer. A lower mother substrate(100), which comprises a TFT(Thin Film Transistor) layer formed on the display cell area(DA) of the first base substrate(110), a color filter layer(CF) and a light shielding pattern(190) formed on the TFT layer, and the first bonding mark(122) formed on the second peripheral display area(DA2) of the display cell area(DA), is formed. An upper mother substrate(200), which comprises the second bonding mark(232) formed using a chemical vapor deposition repair equipment, is formed on the second base substrate(210). The lower mother substrate(100) and the upper mother substrate(200), attached to each other through the first bonding mark(122) and the second bonding mark(232), are cut in units of a display cell.

Description

Manufacturing method of display cell {METHOD OF MANUFACTURING DISPLAY CELL}

1 is a plan view of a display cell on a mother substrate according to a first embodiment of the present invention.

2 is a cross-sectional view of a second peripheral area and a display area according to a first embodiment of the present invention.

3 is a cross-sectional view of a second peripheral area and a display area according to a second exemplary embodiment of the present invention.

It is a schematic diagram of a chemical vapor deposition repair apparatus.

5A and 5B are views illustrating a step of forming a second cementation mark using a chemical vapor deposition repair apparatus.

<Explanation of symbols for the main parts of the drawings>

500 and 502: first and second display cells 100 and 102: first and second lower mother substrates

200, 202: first and second upper mother substrate 110: first base substrate

122, 152: first bonding mark CF: color filter layer

190: Light blocking pattern PE1, PE2: First and second pixel electrode layers

210: second base substrate 222, 224: first and second common electrode layers

232, 234: Second cementation mark 225: Second groove

226 guide mark 182: first groove

CL: cutting line DA: display area

PA1: first peripheral region PA2: second peripheral region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a display cell, and more particularly, to a method for manufacturing a display cell in which reliability of a product is improved, a process is simplified, and manufacturing cost is reduced.

In general, the display panel includes a first substrate including a switching element, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. The second substrate includes a black matrix pattern, color filters, a planarization layer and a common electrode to protect and flatten the black matrix pattern and the color filters.

The display panel bonds the first mother substrate of the first substrate and the second mother substrate of the second substrate, and cuts the bonded first and second mother substrates to form a plurality of display cells. Liquid crystal is injected into display cells of to manufacture a plurality of display panels including the liquid crystal layer.

When the first and second mother substrates are bonded, there is a problem in that light leakage defects due to the bonding error of the first and second mother substrates are very likely to occur. In order to solve this problem, a color filter on array substrate (COA) structure for forming color filters on a first substrate has been proposed, and further, a structure in which a black matrix pattern is formed on the first substrate by omitting the planarization layer for cost reduction. Also proposed.

However, even when the black matrix pattern is formed on the first substrate, a patterning process using an additional mask for forming a bonding key on the second substrate is required, which does not contribute to cost reduction and simplification.

Accordingly, the technical problem of the present invention has been devised in view of the above, and an object of the present invention is to provide a method for manufacturing a display cell with improved productivity and improved reliability of a manufacturing process.

A method of manufacturing a display cell according to an embodiment for realizing the above object includes a thin film transistor layer formed on a display cell region of a first base substrate, a color filter layer and a light shielding pattern formed on the thin film transistor layer. And forming a lower mother substrate including a first bonding mark formed on a peripheral area of the display cell region, and a chemical vapor deposition repair apparatus on a second base substrate corresponding to the first bonding mark. Forming an upper mother substrate including a second cementation mark using repair equipment; and cutting the lower and upper mother substrates bonded in units of display cells using the first and second bonding marks. do.

According to the method of manufacturing the display cell, the light blocking pattern may be formed only on the first base substrate by forming the second bonding mark only in the local region of the second base substrate, thereby minimizing upper and lower misalignment margins. The aperture ratio and transmittance can be improved. Furthermore, by omitting the process of forming the light shielding layer on the second base substrate, the process of forming the overcoating layer may be omitted, thereby improving productivity due to reduction of manufacturing cost and simplification of the process.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a plan view of a display cell on a mother substrate according to a first embodiment of the present invention.

2 is a cross-sectional view of a second peripheral area and a display area according to a first embodiment of the present invention.

1 and 2, the first lower mother substrate 100 and the first upper mother substrate 200 are disposed to face each other. The first lower mother substrate 100 and the first upper mother substrate 200 are bonded in a state in which they are disposed to face each other by a sealing member (not shown).

The first lower mother substrate 100 includes a thin film transistor layer including a switching element TFT formed on the first base substrate 110, a first bonding mark 122, and a color filter layer formed on the thin film transistor layer. (CF), the organic layer 170, the first pixel electrode layer PE1, and the light blocking pattern 190.

The first base substrate 110 includes a display area DA, a first peripheral area PA1 adjacent to the display area DA, and an outer edge of the first peripheral area PA1 based on the cutting line CL. Is divided into a second peripheral area PA2.

The thin film transistor layer is formed on the display area DA, and the light blocking pattern 190 is formed at an edge of the display area DA of the switching element TFT and the first peripheral area PA1 of the display area DA. do. The display area DA and the first peripheral area PA1 defined by the cutting line CL are defined as one display cell area, and the first base substrate 110 includes a plurality of display cell areas.

In the first peripheral area PA1, a driver that provides a driving signal for displaying an image by a plurality of pixel parts of the display area DA as a peripheral area adjacent to the display area DA among the outer parts of the display area DA. Is formed. The second peripheral area PA2 is an outer portion of the first peripheral area PA1, which is spaced apart from the display area DA and then separated by a process of cutting the display cell units along the cutting line CL. Corresponding.

In the display area DA, a plurality of pixel parts P are formed to display an image through the display area DA. The plurality of pixel units P extend in the first direction D1 of the first base substrate 110 of the thin film transistor layer, and the second direction D2 perpendicular to the gate line GL. The source wiring DL, which extends in the cross-sectional view, crosses each other.

The switching element TFT of the thin film transistor layer is formed in each pixel portion P of the display area DA, and includes a gate electrode G connected to the gate line GL and a source electrode connected to the source line DL. S) and the drain electrode D formed to be spaced apart from the source electrode S by a predetermined interval. One end connected to the drain electrode D is exposed to contact the first pixel electrode layer PE1, and the switching element TFT and the first pixel electrode layer PE1 are electrically connected to each other.

The thin film transistor layer forms the gate metal layer on the first base substrate 110, and patterns the gate metal layer into a gate wiring GL, a gate electrode G, and a first bonding mark 122, and then gate wiring. The gate insulating layer 130 is formed on the GL, the gate electrode G, and the first bonding mark 122. Subsequently, the semiconductor layer 142 and the ohmic contact layer 144 are sequentially stacked on the gate insulating layer 130. The switching electrode TFT is formed by forming the source electrode S and the drain electrode D on the ohmic contact layer 144.

The first bonding marks 122 are formed in the second peripheral area PA2 and are simultaneously formed in the process of forming the switching element TFT. For example, the first bonding marks 122 may be formed at corners of the first peripheral area PA1 of the second peripheral area PA1 and may be formed at each corner. The first bonding mark 122 is formed of the same gate metal layer as the gate line GL, and is formed on the second peripheral area PA2 in the process of patterning the gate metal layer into the gate line GL of the display area DA. 1 is patterned and formed by the bonding mark 122. FIG.

The first cementation mark 122 corresponds to the second cementation mark 232 formed on the first upper mother substrate 200. For example, the first cementation mark 122 and the second cementation mark 232 may be formed to overlap each other. Alternatively, the first bonding mark 122 may be formed in a shape that is combined with the second bonding mark 232. The first lower mother substrate 100 and the first upper mother substrate 200 may be normally bonded by the first bonding mark 122 and the second bonding mark 232.

In the process of cutting the first and second adhesion marks 122 and 232 in the display cell unit along the cutting line CL, the second peripheral area PA2 is separated from the display cells. Is removed from.

The passivation layer 160 is formed on the thin film transistor layer, and the passivation layer 160 includes a first hole exposing one end of the drain electrode D, and the first pixel electrode layer PE1 through the first hole. And the switching element TFT are electrically connected. The color filter layer CF is formed on the passivation layer 160. The color filter layer CF includes red (R), green (not shown), and blue (B) color filters.

The organic layer 170 is formed on the color filter layer CF, and the first pixel electrode PE1 is formed on the organic layer 170 of the display area DA. The organic layer 170 includes a second hole corresponding to the first hole of the passivation layer 160, and one end of the drain electrode is exposed through the first and second holes. One end of the exposed drain electrode and the first pixel electrode PE1 are electrically connected to each other. The first pixel electrode PE1 is formed of a transparent conductive material, for example, indium tin oxide (ITO) and indium zinc oxide (IZO).

The light blocking pattern 190 is formed on the first pixel electrode PE1 of the display area DA. Referring to FIG. 1, the light blocking pattern 190 is formed on the first peripheral area PA1 to block the external light from passing through the first peripheral area PA1. Although not illustrated, the light blocking pattern 190 is formed on the gate line GL and the source line DL to partition the pixel units P. Referring to FIG. Referring to FIG. 2, the light blocking pattern 190 is formed on the switching element TFT to block external light from moving to the switching element TFT.

The first upper mother substrate 200 includes a first common electrode layer 222 formed on the second base substrate 210 and a second bonding mark 232 formed on the first common electrode layer 222. The first common electrode layer 222 is formed on the display area DA, the first peripheral area PA1, and the second peripheral area PA2, and the second bonding mark 232 is formed on the second peripheral area PA2. Is formed. The first common electrode layer 222 is made of a transparent conductive material, for example, indium tin oxide (ITO) and indium zinc oxide (IZO).

The second bonding mark 232 is formed on the first common electrode layer 222 in correspondence with the first bonding mark 122. Alternatively, the second bonding mark 232 may be directly formed on the second base substrate 210. In this case, the first common electrode layer 222 is formed on the second bonding mark 232.

3 is a cross-sectional view of a second peripheral area and a display area according to a second exemplary embodiment of the present invention.

Referring to FIG. 3, the second lower mother substrate 102 and the second upper mother substrate 202 are disposed to face each other. The second lower mother substrate 102 and the second upper mother substrate 202 are joined in a state in which they are disposed to face each other by a sealing member (not shown).

The thin film transistor layer including the switching element TFT and the first bonding mark 152 are formed on the first base substrate 110 of the second lower mother substrate 102. The first bonding mark 152 is formed on the second peripheral area PA2 by patterning the source metal layer forming the source electrode S and the drain electrode D of the switching element TFT. The first coalescence mark 152 is formed to correspond to the second coalescence mark 234.

The second pixel electrode layer PE2 is formed on the color filter layer CF formed on the thin film transistor layer. The light blocking pattern 190 is formed on the second pixel electrode layer PE2 and the first peripheral area PA1 of the display area DA.

The second upper mother substrate 202 includes a second common electrode layer 224 formed on the second base substrate 210 and a second bonding mark 234. The second cementation mark 234 is formed on the second display area PA2 in correspondence with the first cementation mark 152, and the guide mark 226 is formed under the second cementation mark 234. The guide mark 226 is formed of the same material as the second common electrode layer 224 and is formed simultaneously with the second common electrode layer 224.

The second pixel electrode layer PE2 includes a first groove 182, and the second common electrode layer 224 includes second grooves 225. The first groove 182 is formed to correspond to an area between the second groove 225 and the second groove 225 adjacent to the second groove 225. When the liquid crystal molecules are later injected between the display cells, the liquid crystal molecules implement a printed vertical alignment mode (PVA) mode having a pretilt angle in a state where no voltage is applied.

Hereinafter, a method of forming the second cementation mark 232 of the first embodiment and the second cementation mark 234 formed on the guide mark 226 of the second embodiment using the chemical vapor deposition repair apparatus will be described in detail. It will be described later.

It is a schematic diagram of a chemical vapor deposition repair apparatus.

Referring to FIG. 4, a chemical vapor deposition repair equipment generally includes a gas supply part, an optical part, and a window unit.

The gas supply unit supplies a metal for repair, for example, tungsten (W) metal, to the window unit in gas form. The optical part is a first laser, which is a CVD laser that irradiates to photoly decompose a tungsten and argon (Ar) mixed gas injected from the gas supply part, and a shot laser that controls the path and focus of the laser light generated from the first laser. Phosphorus second laser. The window unit performs photolysis with the laser light emitted from the optical unit and the gas supplied from the gas supply unit.

The gas supply unit may further include a removal unit for removing surplus gases discharged from the window unit, and may remove the surplus gases discharged to the removal unit through an external pump unit.

The chemical vapor deposition repair apparatus is a device for repairing defects by disconnection on a substrate, wherein the laser light directed to the window port deposits tungsten on the substrate while photolyzing the tungsten and argon mixed gas.

By using the principle of the chemical vapor deposition repair as described above, the second bonding marks 232 and 234 are directly formed on the second base substrate 210 or the first and second common electrodes 222 and 224 are formed on the second base substrate 210. 2, the adhesion marks 232 and 234 can be formed.

5A and 5B are views illustrating a step of forming a second cementation mark using a chemical vapor deposition repair apparatus.

Referring to FIG. 5A, a guide mark 224 is formed on the second base substrate 210. Alternatively, after forming the common electrode layer without a pattern on the second base substrate 210, the second bonding mark 232 may be formed or the second bonding mark may be directly formed on the second base substrate 210. Can be.

The independent guide mark 224 formed on the second base substrate 210 may not recognize the bonding key when the upper and lower plates are attached to the display panel. However, the guide mark 224 may be formed after the guide mark 224 is formed. When the second cementation mark 236 is formed on the 224, the guide mark 224 serves to guide the region where the second cementation mark 236 is to be formed. The guide mark 224 is formed in the process of patterning the common electrode layer.

The second base substrate 210 including the guide mark 224 is placed inside the chamber of the chemical vapor deposition repair apparatus, and when the laser light is irradiated, the tungsten gas ((W (CO) 6) ) Is photolysed.

Referring to FIG. 5B, when the laser light is irradiated in one direction on the second base substrate 210 including the guide mark 224, tungsten gas (W (CO) 6) is photolyzed by the laser light. Tungsten is deposited on the guide mark 224 to form the second coalescence mark 236.

The second adhesion marks 232 and 234 may be formed only on a part of the second peripheral area PA2 at the local position by using the chemical vapor deposition repair apparatus, and then the light blocking layer may be formed after forming the light blocking layer, which is a conventional process. The process of patterning can be omitted. Further, when the light shielding layer is formed by omitting the light shielding layer, the formation of an overcoating layer which must be formed in order to prevent the inflow of foreign substances into the common electrode layer may be omitted.

According to the manufacturing method of such a display cell, the second bonding mark corresponding to the first bonding mark formed on the lower mother substrate including the color filter layer and the light blocking pattern is locally formed on the upper mother substrate using the chemical vapor deposition repair apparatus. It can be selectively formed only in the phosphorus region. Accordingly, a process of forming a light blocking layer on the upper mother substrate and patterning the light blocking layer may be omitted, thereby minimizing upper and lower misalignment margins of the upper and lower substrates, and improving aperture ratio and transmittance.

Furthermore, the process of forming the overcoat layer on the upper mother substrate may be omitted by omitting the process of forming the light blocking layer on the upper mother substrate. Accordingly, productivity can be improved by reducing manufacturing costs and simplifying processes.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (5)

A lower portion including a thin film transistor layer formed on the display cell region of the first base substrate, a color filter layer and a light shielding pattern formed on the thin film transistor layer, and a first bonding mark formed on the peripheral region of the display cell region. Forming a mother substrate; Forming an upper mother substrate on the second base substrate corresponding to the first adhesion mark, the upper mother substrate including a second adhesion mark formed by using a chemical vapor deposition repair equipment; And And cutting the lower and upper mother substrates bonded by the first and second bonding marks in display cell units. The method of claim 1, wherein the forming of the upper mother substrate And forming a common electrode layer on the second base substrate. The method of claim 1, wherein the forming of the upper mother substrate Forming a common electrode layer formed on the second base substrate and including a guide mark corresponding to the first bonding mark and a plurality of grooves formed in the display cell region; The second joining mark is formed on the guide mark. The thin film transistor layer of claim 1, wherein the thin film transistor layer includes a switching element. And a pixel electrode layer electrically connected to the switching element on the color filter layer. The method of claim 4, wherein the light blocking pattern is Formed on the switching element formed in the display cell area, the gate line and the source line connected to the switching element, And a display cell formed at an edge of the display cell region.

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