KR20080004948A - Plasma display, and driving device thereof - Google Patents

Abstract

A plasma display apparatus and a driving method thereof are provided to decrease manufacturing costs for a driver by reducing the number of transistors in the driver for driving a scan driver. A plasma display apparatus includes first, second, third, fourth, and fifth transistors, and first and second paths. The first transistor(Yset), whose first end is connected to a first source voltage for supplying a first voltage, increases gradually the voltage of first electrodes. A first end of the second transistor is connected to a second end of the first transistor and a second end thereof is connected to first electrodes. The first path is formed to flow current from a second source voltage to the first end of the second transistor. A first end of the third transistor is connected to a third source voltage for turning on cells during an address period. A first end of the fourth transistor is connected to a second end of the third transistor and a second end thereof is connected to the first electrodes. The second path is formed to flow current from the first end of the fourth transistor to a fourth source voltage. The fifth transistor(Ynf), which is connected between the fourth source voltage and first electrodes, decreases gradually the voltage of first electrodes.

Description

Plasma display device and driving device thereof {PLASMA DISPLAY, AND DRIVING DEVICE THEREOF}

1 is a view showing a driving circuit of a conventional plasma display device.

2 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

3 is a view schematically illustrating a driving circuit 410 of the scan electrode driver 400 according to an exemplary embodiment of the present invention.

4 illustrates a driving waveform of the plasma display device according to an exemplary embodiment of the present invention.

5A to 5C are diagrams illustrating an operation process of the driving circuit 410 for generating the driving waveform of FIG. 4.

The present invention relates to a plasma display device and a driving device thereof.

The plasma display device is a device that displays characters or images using plasma generated by gas discharge. In the plasma display panel, dozens to millions or more of discharge cells are arranged in a matrix form according to their size.

In general, in a plasma display device, one frame is divided into a plurality of subfields to be driven, and a gray level is displayed by a combination of weights of subfields in which a display operation occurs among the plurality of subfields. To initialize the discharge cells by applying a gradually increasing waveform and a gradually decreasing waveform to the plurality of scan electrodes to stably perform the address discharge during the reset period of each subfield, and to select a cell to emit light during the address period. Scan pulses are sequentially applied to the plurality of scan electrodes. In order to actually display an image during the sustain period, sustain discharge is performed on a cell to be turned on by applying a sustain discharge pulse having a high level voltage and a low level voltage to the scan electrode and the sustain electrode in a reverse phase.

For this operation, as shown in Fig. 1, the driving circuit for driving the scan electrode includes transistors Ys and Yg for applying the high level voltage and the low level voltage to the scan electrode in the sustain period, and in the reset period. Transistors Yrr and Yfr for gradually increasing / decreasing the voltage of the scan electrodes and transistors YscL for sequentially applying scan pulses to the plurality of scan electrodes in the address period are formed. In addition, a path formed through the body diode of the transistor Yg for applying the low level voltage of the sustain discharge pulse when the transistor YscL for sequentially applying the scan pulse to the plurality of scan electrodes in the address period is turned on. The transistor Ynp for blocking and the transistor Ypp for separating the path for gradually increasing the voltage of the scan electrode in the reset period and the path for applying a high level voltage to the scan electrode in the sustain period are formed. In addition, transistors Yr and Yf constituting an energy recovery circuit for recovering and reusing power for applying a high level voltage and a low level voltage to the scan electrode, and transistors Sch and Scl constituting a scanning circuit for an address period. The use of many transistors increases the cost of the driving circuit.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device and a driving device for reducing the unit cost of a driving circuit of the plasma display device.

According to an aspect of the present invention, a plasma display device includes a plurality of first electrodes and a first terminal connected to a first power supply for supplying a first voltage to operate to gradually increase voltages of the plurality of first electrodes. A first transistor, a second transistor connected to a second end of the first transistor and having a second end connected to the plurality of first electrodes, and supplying a second voltage lower than the first voltage A first path is connected to a first path through which a current flows from a second power supply to the first end of the second transistor, and a third power supply supplying a third voltage applied to the first electrode of the cell to be turned on in the address period. A third transistor, a fourth transistor having a first end connected to a second end of the third transistor, and a second end connected to the plurality of first electrodes, wherein the first transistor is connected to the first end of the fourth transistor. Fourth charge lower than the second voltage A second path through which a current flows to a fourth power supply for supplying a second voltage; and a fifth transistor connected between the fourth power supply and the plurality of first electrodes to operate to gradually decrease voltages of the plurality of first electrodes. It includes.

According to another aspect of the present invention, an apparatus for driving a plasma display device including a plurality of first electrodes is provided. The driving device includes a first transistor connected to a first power supply for supplying a first voltage, the first transistor gradually increasing voltages of the plurality of first electrodes, a second end of the first transistor, and a plurality of first electrodes. At least one second transistor connected in series between the electrodes, an anode connected to a second power supply for supplying a second voltage lower than the first voltage, and a cathode connected to a second end of the first transistor A first diode, a third transistor having a first end connected to a third power supply for supplying a third voltage applied to a first electrode of a cell to be turned on in an address period, a second end of the third transistor and the plurality of first At least one fourth transistor connected in series between the electrodes, an anode connected to the second terminal of the third transistor, and a cathode connected to a fourth power supply for supplying a fourth voltage lower than the second voltage. And a fifth transistor connected between the second diode and the third power supply and the plurality of first electrodes to gradually reduce voltages of the plurality of first electrodes.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless otherwise stated.

In addition, the expression that the voltage is maintained throughout the specification indicates that even if the potential difference between two specific points changes over time, the change is within an allowable range in the design or the cause of the change is due to parasitic components that are ignored in the design practice of those skilled in the art. Include cases by. In addition, since the threshold voltage of a semiconductor device (transistor, diode, etc.) is very low compared to the discharge voltage, the threshold voltage is regarded as 0V and approximated.

First, a plasma display device and a driving device thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a scan electrode driver 400, and a sustain electrode driver 500. It includes.

The plasma display panel 100 includes a plurality of address electrodes (hereinafter referred to as "A electrodes") A1-Am extending in the column direction, and a plurality of sustain electrodes extending in pairs with each other in the row direction (hereinafter, " X electrodes "(X1-Xn) and scan electrodes (hereinafter referred to as" Y electrodes ") (Y1-Yn). In general, the X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn, and the X and Y electrodes perform a display operation for displaying an image in the sustain period. The Y electrodes Y1-Yn and the X electrodes X1-Xn are arranged to be orthogonal to the A electrodes A1-Am. At this time, the discharge space at the intersection of the A electrodes (A1-Am) and the X and Y electrodes (X1-Xn, Y1-Yn) forms a cell (110). The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield includes an address period and a sustain period.

The address electrode driver 300 applies a driving voltage to the A electrodes A1-Am according to the driving control signal from the controller 200.

 The scan electrode driver 400 applies a driving voltage to the Y electrodes Y1-Yn according to the driving control signal from the controller 200.

The sustain electrode driver 500 applies a driving voltage to the X electrodes X1-Xn according to the drive control signal from the controller 200.

3 is a view schematically illustrating a driving circuit 410 of the scan electrode driver 400 according to an exemplary embodiment of the present invention. In FIG. 3, only the driving circuit 410 connected to the plurality of Y electrodes Y1 to Yn is illustrated, and only one X electrode X and one Y electrode Y are illustrated for convenience of description. In addition, the capacitive component formed by the X electrode X and the Y electrode Y is illustrated as a panel capacitor Cp. In addition, the driving circuit 410 may be formed in the scan electrode driver 500 of FIG. 1, and the driving circuit 510 connected to the plurality of X electrodes X1 to Xn may be partially connected to the driving circuit 410 of FIG. 3. It may have a similar structure and may have another structure.

As shown in FIG. 3, the driving circuit 410 of the scan electrode driver 400 includes transistors Yset, Ys1, Ys2, Ys3, Ys4, YscL, and Ynf, a scanning circuit 411, capacitors Cs1, Cs2, Cs3, Cs4, CscH), inductor L and diodes D1, D2, Dr, Df, DscH. In FIG. 3, the transistors Yset, Ys1, Ys2, Ys3, Ys4, YscL, and Ynf are illustrated as n-channel field effect transistors, in particular, n-channel metal oxide semiconductor (NMOS) transistors. These transistors (Yset, Ys1, Ys2, Ys3, Ys4, YscL, and Ynf) may form a body diode in the direction from the source to the drain. And other transistors having similar functions instead of NMOS transistors may be used as these transistors (Yset, Ys1, Ys2, Ys3, Ys4, YscL, Ynf). In FIG. 2, the transistors Yset, Ys1, Ys2, Ys3, Ys4, YscL, and Ynf are shown as one transistor, but the transistors Yset, Ys1, Ys2, Ys3, Ys4, YscL, and Ynf are connected in parallel. It may be formed of a plurality of transistors.

3, a source of a transistor Ys2 having a drain connected to the node N1 is connected to a plurality of Y electrodes. A source of the transistor Ys1 is connected to the node N1, and a drain of the transistor Yset having a source connected to the drain of the transistor Ys1 is connected to a power supply Vset supplying a Vset voltage. The first end of the capacitor Cs3 is connected to the power supply Vset, and the voltage of the capacitor Vs3-Vs is charged to the capacitor Cs3. An anode of the diode D1 is connected to the second end of the capacitor Cs3, and a cathode of the diode D1 is connected to the contacts of the transistors Yset and Ys1.

A drain of the transistor Ys3 having a source connected to the node N2 is connected to the plurality of Y electrodes. The drain of the transistor Ys4 is connected to the node N2, and the source of the transistor Ys4 is connected to the ground terminal 0 which supplies the 0V voltage and the drain of the transistor YscL. An anode of the diode D2 is connected to the source of the transistor Ys4, and a cathode of the diode D2 is connected to the ground terminal 0. In addition, the source of the transistor YscL is connected to a power supply VscL for supplying a VscL voltage. The second end of the capacitor Cs4 having the first end connected to the ground terminal 0 is connected to the power supply VscL, the drain of the transistor Ynf is connected to the plurality of Y electrodes, and the transistor Ynf. ) Is connected to a power supply (VscL). At this time, the capacitor Cs4 is charged to the voltage VscL when the transistors Ys3 or Ys3 and Ys4 are turned on. The transistor Yset operates so that a minute current flows from the drain to the source so as to gradually increase the voltage of the Y electrode to the Vset voltage in the form of a lamp at turn-on, and the transistor Ynf is turned on at the turn-on of the Y electrode.

A small current flows from drain to source to gradually reduce the voltage to the Vnf (see FIG. 4) voltage. The diode D1 blocks a current path formed from the Vset voltage to the Vs voltage at the turn-on of the transistor Yset, and the diode D2 turns off the transistors Ys3 and Ys4 at the turn-on of the transistor Ynf. The body diode blocks the current path from the ground terminal to the VscL power supply. In addition, the diode D2 blocks a current path formed to the VscL voltage at the ground terminal when the transistor YscL is turned on.

Meanwhile, in FIG. 3, between the plurality of Y electrodes and the node N1, between the node N1 and the transistor Yst, between the plurality of Y electrodes and the node N2, and between the node N2 and the transistor Yset, respectively. Although one transistor Ys2, Ys1, Ys3, Ys4 is illustrated as being connected, two or more transistors may be connected in series.

The scanning circuit 411 has a first input terminal and a second input terminal, the output terminal is connected to the Y electrode, and the Y electrode corresponding to the voltage of the first input terminal and the voltage of the second input terminal to select a cell to be turned on in the address period. Is optionally applied. Although FIG. 3 illustrates one scan circuit 411 connected to one Y electrode, there are a plurality of scan circuits 431 respectively connected to the plurality of Y electrodes Y1-Yn. In addition, a predetermined number of scan circuits may be formed as one integrated circuit (IC), so that a plurality of output terminals of the scan integrated circuit may be connected to a predetermined number of Y electrodes, respectively. The scanning circuit 411 includes transistors Sch and Scl. The source of the transistor Sch and the drain of the transistor Scl are respectively connected to the Y electrode. An anode of the diode DscH is connected to a power supply VscH for supplying a VscH voltage, and a cathode of the diode DscH is connected to a first input terminal of the scan circuit 431. The first end of the capacitor CscH is connected to the cathode of the diode DscH, and the second end of the capacitor CscH is connected to the second input terminal of the scanning circuit 431. At this time, the transistors Ys3, Ys4, and YscL are turned on, and the capacitor CscH is charged with the voltage (VscH-VscL).

In addition, capacitors Cs1 and Cs2 are connected in series between the ground terminal 0 and the second terminal of the capacitor Cs3. That is, the first end of the capacitor Cs1 is connected to the ground terminal 0, the first end of the capacitor Cs2 is connected to the second end of the capacitor Cs1, and the second end of the capacitor Cs2 is connected. The stage is connected to the second stage of the capacitor Cs3. At this time, when the voltage of Vs is supplied to the second end of the capacitor Cs3 by the second end of the capacitor Cs2, and the capacitances of the capacitors Cs1 and Cs2 are approximately equal, the two capacitors Cs1 and Cs2 are respectively provided. Vs / 2 voltage is charged. An anode of the diode Dr and a cathode of the diode Df are respectively connected to a second end of the inductor L having the first end connected to the contacts of the capacitors Cs1 and Cs2. The cathode of the diode Dr is connected to the contacts of the transistors Ys1 and Ys2, and the anode of the diode Df is connected to the contacts of the transistors Ys3 and Ys4. At this time, the diode Dr is used to set the rising path for increasing the voltage of the Y electrode through the transistor Ys2, and the diode Df sets the falling path for decreasing the voltage of the Y electrode through the transistor Ys3. It is to. Here, the inductor L, the diodes Dr and Df and the transistors Ys2 and Ys3 operate as power recovery means for recovering and reusing reactive power formed by the sustain discharge pulse in the sustain period, and the capacitor Cs1. Operates as a power recovery power supply Vs / 2.

Next, an operation process of applying a driving waveform to the Y electrode by using the driving circuit 410 of FIG. 2 will be described with reference to FIGS. 4 and 5A to 5C.

4 is a diagram illustrating a driving waveform of the plasma display device according to an exemplary embodiment of the present invention, and FIGS. 5A to 5C are diagrams illustrating an operation process of the driving circuit 410 for generating the driving waveform of FIG. 3.

As shown in FIGS. 4 and 5A, the driving circuit 410 of the scan electrode driving unit 400 turns on the transistors Ys1, Ys2, and Scl in the rising period of the reset period to supply the power supply Vset and the capacitor Cs3. After applying the voltage Vs to the Y electrode through the path of the diode D1, the transistors Ys1, Ys2, Scl and the panel capacitor Cp, the transistor Yset is turned on to turn on the power supply Vset, the transistor. The voltage of the Y electrode is gradually increased from the voltage of Vs to the voltage of Vset through the paths of (Yset, Ys1, Ys2, Scl) and the Y electrode of the panel capacitor Cp. In the rising period of the reset period, the driving circuit 510 of the sustain electrode driver 500 applies a reference voltage (0 V in FIG. 4) to the X electrode. Then, while the voltage of the Y electrode is increased, a weak reset discharge occurs between the Y electrode and the X electrode, and wall charges are formed in the discharge cell.

Next, in the falling period of the reset period, the driving circuit 410 of the scan electrode driver 400 turns off the transistors Yset, Ys1, and Ys2 and turns on the transistor Ys3. Then, resonance occurs through the paths of the Y electrode, the transistors Scl and Ys3, the diode Df, the inductor L, the capacitor Cs1, and the ground terminal 0, whereby the energy stored in the Y electrode is transferred to the inductor. Recovering to the capacitor Cs1 through L, the voltage of the Y electrode is reduced from the voltage of Vset to the voltage of Vs. That is, the resonance reduces the voltage of the Y electrode from the voltage Vset to the voltage (-Vset + Vs), and turns off the transistor Yf at the instant the voltage of the Y electrode becomes the voltage Vs. Then, the transistor Ynf is turned on to gradually decrease the voltage of the Y electrode from the voltage Vs to the voltage Vnf through the paths of the Y electrode, the transistors Scl, Ynf, and the power supply VscL. In FIG. 4, the voltage Vnf and the voltage VscL are shown at the same level, but the voltage Vnf may be higher than the voltage VscL. The driving circuit 510 of the sustain electrode driver 500 applies the Ve voltage to the X electrode during the falling period of the reset period. Then, while a weak reset discharge occurs between the Y electrode and the X electrode while the voltage of the Y electrode decreases, the wall charges formed in the plurality of discharge cells are erased and initialized to the non-light emitting cell. In general, the magnitude of the (Vnf-Ve) voltage is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, thereby preventing the non-light emitting cell in which the address discharge has not occurred in the address period from being misdischarged in the sustain period.

Next, as shown in FIGS. 4 and 5B, in the address period, the driving circuit 410 of the scan electrode driver 400 turns off the transistor Ynf and turns on the transistors Ys3, Ys4, and YscL to turn on the panel capacitor. The voltage VscL is applied to the Y electrode of the cell to be turned on through the path of the Y electrode (Cp), the transistors Scl, s3, Ys4, YscL, and the power supply VscL. Meanwhile, a VscH voltage higher than the VscL voltage may be applied to the Y electrode to which the VscL voltage is not applied. The address electrode driver 300 applies an address pulse having a positive voltage to the A electrode of a cell to be turned on among discharge cells formed by the Y electrode to which the scan pulse is applied. Then, an address discharge occurs in a cell to which the VscL voltage of the scan pulse and the positive voltage of the address pulse are applied, thereby forming a wall voltage on the X electrode and the Y electrode to turn on the cell.

4 and 5C, in the sustain period, the driving circuit 410 of the scan electrode driver 400 turns off the transistor YscL to turn off the Y electrode, the transistor Scl, of the panel capacitor Cp, and the like. A 0V voltage is applied to the Y electrode through the paths of Ys3 and Ys4, the diode D2, and the ground terminal 0. At this time, the driving circuit 510 of the sustain electrode driver 500 also applies a 0V voltage to the X electrode.

Next, the transistors Ys3 and Ys4 are turned off and the transistor Ys2 is turned on. Then, resonance occurs in the path of the Y electrode of the ground terminal 0, the capacitor Cs1, the inductor L, the diode Dr, the transistors Ys1, Scl, and the panel capacitor Cp. Then, the energy charged in the capacitor Cs1 is injected into the Y electrode through the inductor L so that the voltage of the Y electrode increases from the 0V voltage to the Vs voltage. In this case, the driving circuit of the sustain electrode driver 500 reduces the voltage of the X electrode from the Vs voltage to the 0V voltage.

Subsequently, the driving circuit 410 of the scan electrode driver 400 turns on the transistor Ys1 to turn on the power supply Vset, the capacitor Cs3, the diode D1, the transistors Ys1, Ys2, Scl, and the panel capacitor Cp. Vs voltage is applied to the Y electrode through the path of the Y electrode. At this time, the driving circuit of the sustain electrode driver 500 applies a 0V voltage to the X electrode.

Next, the driving circuit 410 of the scan electrode driver 400 turns off the transistors Ys1 and Ys2 and turns on the transistor Ys3. Then, resonance occurs in the path of the Y electrode, the transistors Scl and Ys3, the diode Df, the inductor L, the capacitor Cs1, and the ground terminal 0 of the panel capacitor Cp. Then, the energy stored in the Y electrode is recovered to the ground terminal 0 through the inductor (L), the voltage of the Y electrode is reduced from the Vs voltage to 0V voltage. At this time, the driving circuit of the sustain electrode driver 500 increases the voltage of the X electrode from the voltage of 0V to the voltage of Vs.

Subsequently, the driving circuit 410 of the scan electrode driver 410 turns on the transistor Ys4 to turn on the Y electrode of the panel capacitor Cp, the transistors Scl, Ys3, Ys4, the diode D2, and the ground terminal 0. A 0V voltage is applied to the Y electrode through the path of. At this time, the driving circuit of the sustain electrode driver 500 applies the Vs voltage to the X electrode.

In the sustain period, the driving circuit 410 of the scan electrode driver 400 may repeat the above-described operation and apply the sustain discharge pulse having the Vs voltage and the 0V voltage to the Y electrode as many times as the weight of the corresponding subfield. have. The driving circuit 510 of the sustain electrode driver 500 may apply a sustain discharge pulse to the X electrode in a phase opposite to that of the sustain discharge pulse applied to the Y electrode.

As described above, in the driving circuit 410 of the scan electrode driver 400 according to an exemplary embodiment of the present invention, instead of the transistor for separating the path for applying the Vset voltage to the Y electrode and the path for applying the Vs voltage to the Y electrode. Since the diode D1 is used and the diode D2 is used instead of the transistor for blocking the current path formed through the body diode of the transistor for applying the low level voltage of the sustain discharge pulse, the transistor in the driving circuit 410 is used. The number of can be reduced.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the number of transistors can be reduced in the driving circuit for driving the scan electrodes, the unit cost of the driving circuit of the plasma display device is reduced.

Claims (11)

A plurality of first electrodes, A first transistor connected to a first power supply for supplying a first voltage, the first transistor operable to gradually increase voltages of the plurality of first electrodes, A second transistor having a first end connected to a second end of the first transistor and a second end connected to the plurality of first electrodes; A first path through which a current flows from the second power supply for supplying a second voltage lower than the first voltage to the first terminal of the second transistor, A third transistor having a first end connected to a third power supply for supplying a third voltage applied to a first electrode of a cell to be turned on in an address period; A fourth transistor having a first end connected to a second end of the third transistor and a second end connected to the plurality of first electrodes, A second path through which a current flows from a first end of the fourth transistor to a fourth power supply for supplying a fourth voltage lower than the second voltage, and A fifth transistor connected between the fourth power supply and the plurality of first electrodes and operative to gradually decrease voltages of the plurality of first electrodes Plasma display device comprising a. The method of claim 1, A sixth transistor having a first end connected to a second end of the second transistor and a second end connected to the plurality of second electrodes; A seventh transistor having a first end connected to a second end of the fourth transistor, and a second end connected to the plurality of first electrodes; An inductor having a first end connected to a fifth power supply for supplying a fifth voltage between the second voltage and the fourth voltage; A rising path connected between a second end of the inductor and a first end of the sixth transistor to increase voltages of the plurality of first electrodes, A falling path connected between a second end of the inductor and a first end of the seventh transistor to reduce voltages of the plurality of first electrodes, and In a reset period, the first and second transistors are turned on for a first period, the seventh transistor is turned on for a second period, and the fifth transistor is turned on for a third period. Control unit Plasma display device further comprising. The method of claim 2, The control unit, In the sustaining period, the sixth transistor is turned on for a fourth period, the second and sixth transistors are turned on for a fifth period, and the seventh transistor is turned on for a sixth period. And turn on the third and seventh transistors during the seventh period. The method of claim 3, The first path includes a first diode having an anode connected to a second power supply and a cathode connected to a first end of the second transistor, The second path includes a second diode having an anode connected to a first end of the fourth transistor and a cathode connected to the fourth power supply. The method according to any one of claims 1 to 4, A plurality of scanning circuits connected to the plurality of first electrodes, respectively, having a first input terminal and a second input terminal, respectively, for applying a voltage of the first input terminal or a voltage of the second input terminal to a corresponding first electrode; Include, And the third, fourth, and seventh transistors are turned on in an address period so that the third voltage is sequentially applied to each second input terminal of the plurality of scan circuits. In the apparatus for driving a plasma display device including a plurality of first electrodes, A first transistor connected to a first power supply for supplying a first voltage to gradually increase voltages of the plurality of first electrodes, At least one second transistor connected in series between a second end of the first transistor and a plurality of first electrodes, A first diode having an anode connected to a second power supply for supplying a second voltage lower than the first voltage, and having a cathode connected to a second end of the first transistor; A third transistor having a first end connected to a third power supply for supplying a third voltage applied to a first electrode of a cell to be turned on in an address period; At least one fourth transistor connected in series between a second end of the third transistor and the plurality of first electrodes, A second diode having an anode connected to a second end of the third transistor and a cathode connected to a fourth power supply for supplying a fourth voltage lower than the second voltage; and A fifth transistor connected between the third power supply and the plurality of first electrodes to gradually reduce voltages of the plurality of first electrodes Driving device comprising a. The method of claim 6, A capacitor connected to the fourth power source and charging a voltage between the second voltage and the fourth voltage, and And an inductor having a first end connected to a second end of the first capacitor, and further comprising power recovery means for changing voltages of the plurality of first electrodes through the inductor. And a driving device for turning on the fifth transistor after changing the voltages of the plurality of first electrodes through the power recovery means. The method of claim 7, wherein The power recovery means, A sixth transistor connected between the plurality of first electrodes and the at least one second transistor, A seventh transistor connected between the plurality of first electrodes and the at least one fourth transistor, A third diode having an anode connected to the second end of the inductor and a cathode connected to the sixth transistor, and A fourth diode having a cathode connected to a second end of the inductor and an anode connected to the seventh transistor, The seventh transistor is turned on in the reset period to change the voltage of the plurality of first electrodes. The method of claim 8, In the retention period, During the first period, the sixth transistor is turned on to increase the voltage of the plurality of first electrodes, During the second period, the second and sixth transistors are turned on to apply the second voltage to the plurality of first electrodes, During the third period, the seventh transistor is turned on to decrease the voltage of the plurality of first electrodes, And driving the fourth and seventh transistors to apply the fourth voltage to the plurality of first electrodes during the fourth period. The method of claim 9, The plasma display device, And a plurality of second electrodes performing a display operation together with the plurality of first electrodes. And reducing the voltage of the plurality of second electrodes during the first period and increasing the voltage of the plurality of second electrodes during the third period. The method according to any one of claims 6 to 10, And a plurality of output terminals are respectively connected to the plurality of first electrodes, wherein the voltage of the second input terminal is selectively connected to a corresponding first electrode of the plurality of first electrodes during an address period. Further comprising a scanning integrated circuit for applying, And turning on the third and fourth transistors in an address period to apply the third voltage to the second input terminal of the scan integrated circuit.

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