KR20080002219A - Liquid crystal display device - Google Patents

Abstract

An LCD(Liquid Crystal Display) is provided to reduce widths of storage capacitors formed in both sides of a pixel area and form a special storage capacitor in an area where a rib is formed, thereby ensuring sufficient storage capacity and preventing deterioration of an aperture ratio. An LCD(Liquid Crystal Display) comprises a first substrate, a gate line formed on the first substrate, a data line crossing the gate line to define a pixel area, a first storage capacitor formed in both sides of the pixel area, a second storage capacitor connected with the first storage capacitor as crossing the pixel area, a TFT(Thin Film Transistor) connected with the gate line and data line and formed in the pixel area, a pixel electrode(124) connected to the TFT and formed in the pixel area, a second substrate spaced from the substrate as facing the first substrate, a color filter formed in the second substrate in correspondence to the pixel area, a common electrode formed in an upper part of the color filter, a rib(140) protruded from the common electrode, and an LC layer interposed between the pixel electrode and the common electrode. The rib corresponds to the second storage capacitor.

Description

Liquid crystal display device

1 is a cross-sectional view schematically showing a VA mode liquid crystal display device according to the prior art.

2 is an enlarged plan view of a pixel area of a VA mode liquid crystal display device according to the prior art;

3 is an enlarged plan view of one pixel area of an array substrate for a liquid crystal display device according to an embodiment of the present invention;

4 is a cross-sectional view taken along the line IV-IV of FIG. 3.

<Brief description of the main parts of the drawing>

110: first substrate 132: first metal pattern

134: second metal pattern 136: third metal pattern

138: storage contact hole 140: rib

Cst1: first storage capacitor Cst2: second storage capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a VA mode liquid crystal display device capable of improving the aperture ratio by forming a storage capacitor corresponding to a region where ribs are formed.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal. Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and the polarization state of light is changed in the molecular arrangement direction of the liquid crystal due to optical anisotropy, thereby representing image information.

In general, the VA mode liquid crystal display device has an effect of increasing the viewing angle by using a vertical alignment layer and a liquid crystal having a negative dielectric anisotropy and a negative phase difference plate.

1 is a schematic cross-sectional view of a VA mode liquid crystal display device according to the related art.

As shown in the drawing, a general VA mode liquid crystal display device is provided between a first substrate 10, a second substrate 30 on the first substrate 10, and the first and second substrates 10 and 20. It consists of the liquid crystal layer 40 interposed.

A gate line (not shown) and a data line (not shown) intersect each other on the first substrate 10 to define a pixel region P. The pixel region P includes the gate line (not shown) and The thin film transistor T is connected to the data line (not shown).

The thin film transistor T extends from the gate line (not shown) to the pixel region P, and includes a gate electrode 12 formed on the first substrate 10 and an upper portion of the gate electrode 12. A gate insulating film 14, an active layer 16a and an ohmic contact layer 16b, and a semiconductor layer 16 formed on the gate insulating film 14 and spaced apart from each other on the semiconductor layer 16. And a protective layer 22 having a source electrode 18 and a drain electrode 20 formed therein, and a drain contact hole 23 exposing a part of the drain electrode 20. Here, the gate electrode 12 is made of the same material and the same layer as the gate wiring (not shown), the source electrode 18 and the drain electrode 20 is the same layer as the data wiring (not shown) To the same material.

In the pixel region, the pixel electrode 24 contacting the drain electrode 20 through the drain contact hole 23 is formed. The pixel electrode 24 is made of indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), which is a transparent conductive material.

In addition, a storage capacitor Cst is formed at a side of the pixel region P. FIG. The storage capacitor Cst is formed on the same layer as the gate wiring (not shown), and includes a first storage electrode 26 made of the same material, the gate insulating layer 14, the protective layer 22, and the pixel. The second storage electrode 28 extending from the electrode 24 is laminated. The gate insulating layer 14 and the protective layer 22 between the first storage electrode 26 and the second storage electrode 28 serve as a dielectric.

In addition, the second substrate 30 includes a black matrix 32 which blocks an area where the thin film transistor T and the storage capacitor Cst are formed on the first substrate 10, and red and green corresponding to the pixel area. The blue color filters 34a, 34b, 34c and the common electrode 36 are sequentially stacked, and a rib 38 is formed on the common electrode 36. The common electrode 36 forms an electric field with the pixel region. In addition, the rib 38 is formed in the center of the pixel region and distorts the electric field E to form a multi-domain.

In addition, the liquid crystal layer 40 is formed between the first and second substrates 10 and 30, more specifically, the pixel electrode 24 and the common electrode 36.

2 is an enlarged plan view of a pixel area of a VA mode liquid crystal display according to the related art.

As shown in the drawing, the gate line GL and the data line DL intersect to define the pixel area P. As shown in FIG. In addition, the thin film transistor T connected to the gate line GL and the data line DL is formed. The thin film transistor T extends from the gate line GL to protrude into the pixel region P, the semiconductor layer 16 on the gate electrode 12, and the semiconductor layer. 16, the source and drain electrodes 18 and 20 are spaced apart from each other. The source electrode 18 extends from the data line DL, and the drain electrode 20 is connected to the pixel electrode 24 through the drain contact hole 23.

The storage capacitor Cst is formed on both side surfaces of the pixel region P. The storage capacitor Cst includes the first storage electrode 26 formed on the same layer as the gate line GL, the second storage electrode 28 above the first storage electrode 26, and the first storage electrode Cst. And the gate insulating layer 14 and the protective layer 22 between the second storage electrodes 26 and 28.

The storage capacitor Cst corresponds to an overlapping portion of the first storage electrode 26 and the second storage electrode 28, and has a first width w1. The first width w1 needs to be large to secure sufficient storage capacity, but this results in a decrease in the aperture ratio.

In addition, since the pixel area P has a rectangular shape in which the vertical length is larger than the horizontal length, the pixel area P is divided into a first region D1 and a second region D2 having a square shape for symmetrical liquid crystal arrangement. In addition, as shown in FIG. 1, ribs 38 are formed at the center of each of the first and second regions D1 and D2 to secure a viewing angle. The first and second regions D1 and D2 have a square shape, and since the ribs 38 are formed at the center thereof, the liquid crystals are symmetrically disposed in the first and second regions D1 and D2. Is arranged. As described above, the rib 38 is formed in the first and second regions D1 and D2 to secure the viewing angle, thereby causing a problem that the aperture ratio is lowered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and by reducing the width of the storage capacitor formed on both sides of the pixel region, and by forming a separate storage capacitor in the region where the rib is formed, while also ensuring sufficient storage capacity It is intended to solve the problem of lowering the aperture ratio.

In order to achieve the object as described above, the present invention comprises a first substrate; A gate wiring formed on the first substrate; A data line crossing the gate line and defining a pixel area; First storage capacitors formed at both sides of the pixel region; A second storage capacitor connected to the first storage capacitor and formed to cross the pixel area; A thin film transistor connected to the gate line and the data line and formed in the pixel area; A pixel electrode connected to the thin film transistor and formed in the pixel region; A second substrate facing and spaced apart from the first substrate; A color filter corresponding to the pixel region and formed on the second substrate; A common electrode on the color filter; Ribs protruding from the common electrode; A liquid crystal display device including a liquid crystal layer interposed between the pixel electrode and the common electrode is provided.

The rib corresponds to the second storage capacitor, wherein the pixel area is defined as a first area and a second area, and the second storage capacitor is formed by dividing the second pixel area into two parts. do.

The rib is formed corresponding to the center of each of the first region and the second region.

The second storage capacitor may include a first metal pattern, a gate insulating layer, a second metal pattern, a protective layer, and a third metal pattern, which are sequentially stacked. And the same layer, characterized in that made of the same material.

The second metal pattern may be formed of the same material as the data line, and the protective layer may include a storage contact hole exposing the second metal pattern, and the third metal pattern may include the storage material. In contact with the second metal pattern through a contact hole.

The storage contact hole is formed corresponding to the rib.

The thin film transistor may include a gate electrode extending from the gate wiring, a gate insulating film on the gate electrode, a semiconductor layer on the gate insulating film, a source electrode and a drain electrode spaced apart from each other on the semiconductor layer, And a drain contact hole exposing a portion of the drain electrode, wherein the drain electrode includes a protective layer formed on the source electrode and the drain electrode, and the pixel electrode contacts the drain electrode through the drain contact hole. .

Hereinafter, with reference to the drawings will be described a preferred embodiment according to the present invention.

3 is an enlarged plan view of an array substrate of an LCD according to the present invention, particularly one pixel region of the array substrate.

As shown in the drawing, the gate line GL and the data line DL intersect on the first substrate 110 to define the pixel area P. Referring to FIG. The pixel area P has a rectangular shape in which the vertical length is longer than the horizontal length. The pixel electrode 124 is formed in the pixel region P. The pixel electrode 124 is provided with a groove to form a symmetrical liquid crystal array in the pixel region P. D1, D2).

A thin film transistor T connected to the gate line GL and the data line DL is formed in the pixel area P. The thin film transistor T includes a gate electrode 112, a semiconductor layer 116, a source electrode 118, a drain electrode 120, and the like, and applies an image signal to the pixel electrode 124. . To this end, a drain contact hole 123 is formed in the drain electrode 120, and the thin film transistor T and the pixel electrode 124 are connected through the drain contact hole 123.

Although not shown, the liquid crystal display according to the present invention includes a second substrate facing each other in addition to the first substrate 110, and a liquid crystal layer is formed between the first and second substrates. A color filter is formed in each of the pixel regions P on the second substrate, and a common electrode is formed on the color filter. An electric field is formed between the common electrode and the pixel electrode 124, thereby realizing an image by changing the transmittance of the liquid crystal layer. In the VA mode liquid crystal display, the viewing angle is improved by a symmetrical arrangement of liquid crystals. To this end, a rib 140 is formed on the common electrode. The ribs 140 are shown in dashed lines in FIG. 3.

As described above, the pixel region P is divided into first and second regions D1 and D2 having a square shape, and the rib 140 also has a center of the first and second regions D1 and D2. Correspondingly, first and second ribs 140a and 140b are formed.

The first storage capacitor Cst1 is formed in the pixel region P. The first storage capacitor Cst1 includes a first storage electrode 126 formed on the first substrate 110, a gate insulating layer (not shown) on the first storage electrode 126, and an upper portion of the gate insulating layer. A protective layer (not shown) and a second storage electrode 128 on the protective layer (not shown). The second storage electrode 128 corresponds to a portion of the pixel electrode 124 overlapping with the first storage electrode 126. The gate insulating layer (not shown) and the protective layer (not shown) serve as a dielectric layer between the first and second storage electrodes 126 and 128. In addition, the first storage electrode 126 is formed of the same material on the same layer as the gate line GL. In the liquid crystal display according to the embodiment of the present invention, the first storage capacitor Cst1 has a second width w2, and the second width w2 is a storage capacitor (FIG. 2 of FIG. 2). Cst) is smaller than the width (w1 in FIG. 2). The periphery of the rib 140 is not considered in the calculation of the aperture ratio, and by forming the second storage capacitor Cst2 in this portion, the aperture ratio is improved while maintaining the entire area of the storage capacitor.

Considering that the storage capacitor is formed to overlap the pixel electrode, it can be seen that according to the present invention, the aperture ratio is improved as compared with the prior art.

A large feature of the present invention is to form the second storage capacitor capacitor Cst2 corresponding to the region where the rib 140 is formed. The second storage Cst2 may include a gate insulating layer (not shown), a second metal pattern 134, a protective layer (not shown), and a third metal on the first metal pattern 132 formed on the first substrate. The pattern 138 has a stacked structure sequentially. The gate insulating film (not shown) functions as a dielectric layer. The first metal pattern 132 is formed simultaneously with the gate line GL, and the gate insulating layer (not shown) is formed on the first metal pattern 132. In addition, the second metal pattern 134 formed of the same material is positioned on the gate insulating layer (not shown) and on the same layer as the data line DL, and the protection is formed on the second metal pattern 134. A layer (not shown) is formed. A storage contact hole 138 exposing the second metal pattern 134 is formed in the passivation layer (not shown). The third metal pattern 136 formed on the passivation layer (not shown) is a portion overlapped with the first and second metal patterns 132 and 134 of the pixel electrode 124 and the third metal pattern 136. The metal pattern 136 contacts the second metal pattern 134 through the storage contact hole 138. Accordingly, the first metal pattern 132 has a function of a first electrode in the second storage capacitor Cst2, and the second and third metal patterns 134 contacting through the storage contact hole 138. , 138 has the function of a second electrode.

The second storage capacitor Cst2 is formed to cross the central portion of the second region D2. That is, it corresponds to the second rib 140b formed on the second substrate (not shown). Since the area where the second rib 140b is formed is an area that is originally excluded from the calculation of the opening rate, the opening rate does not decrease by the formation of the second storage capacitor Cst2. Although not shown, light may be blocked by forming a black matrix corresponding to the second story capacitor Cst2 on the second substrate.

Since the transmittance of the liquid crystal is distorted, even if the second storage capacitor Cst2 is formed here, the opening ratio of the liquid crystal display device is not lowered. In the present exemplary embodiment, the second storage capacitor Cst2 is formed only in the second region D2, but the present invention is not limited thereto. The second storage capacitor Cst2 may also correspond to the first rib 140a in the first region D1. Of course it can be formed.

Therefore, according to the embodiment of the present invention, the aperture ratio is improved by reducing the width w1 of the first storage capacitor Cst1 formed on the side surface of the pixel region P. FIG. In addition, the storage capacity may be prevented from falling by forming the second storage capacitor Cst2 corresponding to an area that does not affect the opening ratio, that is, an area in which the rib 140a is formed.

4 is a cross-sectional view taken along the line IV-IV of FIG. 3.

As illustrated, a first metal material is deposited and patterned on the first substrate 110 to form the gate electrode 112 and the first metal pattern 132. At the same time, a first storage electrode 126 of the gate line GL (see FIG. 3) and the first storage capacitor (Cst1 of FIG. 3) is formed. The gate electrode 112 extends from the gate wiring (GL in FIG. 3) to the pixel region P. As shown in FIG.

The gate insulating layer 114 is formed on the gate electrode 112 and the first metal pattern 132. The semiconductor layer 116 is formed on the gate insulating layer 114 to correspond to the gate electrode 112. The semiconductor layer 116 includes an active layer 116a and an ohmic contact layer 116b thereon, and the ohmic contact layer 116b exposes a portion of the lower active layer 116a. It includes.

Next, a second metal material is deposited and patterned to form the source electrode 118 and the drain electrode 120 spaced apart from each other on the semiconductor layer 116. At the same time, a second metal pattern 134 is formed on the first metal pattern 132. The gate insulating layer 114 is formed between the first and second metal patterns 132 and 134. The source and drain electrodes 118 and 120 and the second metal pattern 134 are made of the same material on the same layer as the data line (DL of FIG. 3).

Next, the passivation layer 122 is formed on the source and drain electrodes 118 and 120 and the second metal pattern 134. The protective layer 122 includes a drain contact hole 123 and a storage contact hole 138 exposing the drain electrode 120 and the second metal pattern 134, respectively.

The pixel electrode 124 is formed on the passivation layer 122 to contact the drain electrode 120 through the drain contact hole 123. The pixel electrode 124 is made of indium-tin-oxide (ITO), indium-zinc-oxide (IZO), or the like, which is a transparent conductive metal material. At the same time, a third metal pattern 136 is formed on the passivation layer 122 to correspond to the second metal pattern 134. The third metal pattern 136 is integral with the pixel electrode 124, and a portion overlapping with the second metal pattern 134 corresponds to the third metal pattern 136. The third metal pattern 136 contacts the second metal pattern 134 through the storage contact hole 138.

In the second storage capacitor Cst2 having the above configuration, the first metal pattern 132 functions as a first electrode, and the second and third metal patterns 134 and 136 in contact with each other are made of a first electrode. It functions as a two electrode. In addition, the gate insulating layer 114 between the first and second metal patterns 132 and 134 functions as an insulating layer.

The present embodiment includes a second metal pattern 134 formed at the same time as the source and drain electrodes 118 and 120, but may be omitted. It is natural that a storage capacitor can be formed by forming a first electrode simultaneously with the gate wiring, stacking a gate insulating film and a protective layer thereon, and forming a second electrode simultaneously with the pixel electrode.

In the liquid crystal display according to the embodiment of the present invention, a first substrate having the above-described configuration is laminated to face a second substrate (not shown), and a liquid crystal layer (not shown) is injected between the first and second substrates. It is manufactured by.

Although not shown, the thin film transistor and the like, and a black matrix to cover the non-display area are formed on the second substrate, and red, green, and blue color filters are formed on the second substrate to correspond to the pixel area of the first substrate. In addition, a common electrode is formed to cover the color filter. In addition, ribs are formed at the center of the pixel region to form a multi-domain by symmetrical arrangement of liquid crystals. The ribs are formed corresponding to the first and second regions, respectively.

According to the present invention, it is possible to improve the aperture ratio while securing the storage capacity.

That is, in the related art, the width of the storage capacitor, which is formed on both sides of the pixel region by overlapping with the pixel region, reduces the aperture ratio, and forms a separate storage capacitor in the region where the rib is formed, so that the storage capacity is not reduced. The aperture ratio is improved.

Claims (10)

A first substrate; A gate wiring formed on the first substrate; A data line crossing the gate line and defining a pixel area; First storage capacitors formed at both sides of the pixel region; A second storage capacitor connected to the first storage capacitor and formed to cross the pixel area; A thin film transistor connected to the gate line and the data line and formed in the pixel area; A pixel electrode connected to the thin film transistor and formed in the pixel region; A second substrate facing and spaced apart from the first substrate; A color filter corresponding to the pixel region and formed on the second substrate; A common electrode on the color filter; Ribs protruding from the common electrode; A liquid crystal layer interposed between the pixel electrode and the common electrode Liquid crystal display comprising a. The method of claim 1, And the ribs correspond to the second storage capacitors. The method of claim 1, The pixel area is defined as a first area and a second area, and the second storage capacitor is formed by dividing the second pixel area into two parts. The method of claim 3, wherein And the ribs are formed corresponding to the centers of each of the first region and the second region. The method of claim 1, The second storage capacitor includes a first metal pattern, a gate insulating film, a second metal pattern, a protective layer, and a third metal pattern, which are sequentially stacked. The method of claim 5, And the first metal pattern and the same layer on the same layer as the gate wiring. The method of claim 5, And the second metal pattern is formed of the same material on the same layer as the data line. The method of claim 7, wherein The protective layer includes a storage contact hole exposing the second metal pattern, wherein the third metal pattern is in contact with the second metal pattern through the storage contact hole. The method of claim 8, And the storage contact hole is formed corresponding to the rib. The method of claim 1, The thin film transistor may include a gate electrode extending from the gate wiring, a gate insulating film on the gate electrode, a semiconductor layer on the gate insulating film, a source electrode and a drain electrode spaced apart from each other on the semiconductor layer, and the drain. A drain contact hole exposing a part of the electrode, the protective layer formed on the source electrode and the drain electrode, And the pixel electrode is in contact with the drain electrode through the drain contact hole.

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