JP2006201344A - Substrate for liquid crystal display device, and liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for a liquid crystal display device, with which bright and excellent display characteristics with high transmittance are obtained and a high manufacturing yield is obtained in relation to the substrate for the liquid crystal display device used for a display portion etc. of electronic equipment, and the liquid crystal display device, and to provide the liquid crystal display device. <P>SOLUTION: The liquid crystal display device is constructed so as to have: a storage capacitance bus line 3 formed nearly in parallel to a gate bus line 1; a first pixel electrode 6 electrically connected to a source electrode S of a TFT 4; a second pixel electrode 7 placed opposite to the source electrode S of the TFT 4 via an insulating film, and formed while being separated from the first pixel electrode 6; and a slit portion 13 of which the slit width (a) between respective adjacent edge portions of the first pixel electrode 6 and the second pixel electrode 7 is formed to be wider than the shortest slit width (b) on the storage capacitance bus line 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a substrate for a liquid crystal display device and a liquid crystal display device used for a display unit of an electronic device.

  In recent years, liquid crystal display devices have been used as television receivers, personal computer monitor devices, and the like. In these applications, a high viewing angle characteristic that allows a display screen to be viewed with high quality from all directions is required. As a liquid crystal display device capable of obtaining a high viewing angle characteristic, an MVA (Multi-domain Vertical Alignment) type liquid crystal display device is known. In an MVA type liquid crystal display device, when no voltage is applied, liquid crystal molecules are aligned perpendicularly to the substrate, and when a voltage is applied to the liquid crystal, the liquid crystal is projected by a protrusion formed on the substrate or a slit provided in a transparent electrode (ITO). The molecular orientation is defined.

  In the vertical alignment method in which liquid crystal molecules are aligned perpendicularly to the substrate as in the MVA method, the transmittance characteristic (TV characteristic) with respect to the voltage applied to the liquid crystal is generally oblique to the normal direction (front direction) of the display screen. It depends on the direction. For this reason, even when the TV characteristic in the normal direction of the screen is optimally adjusted, the TV characteristic is distorted and the color of the image changes whitish when the screen is viewed from an oblique direction. In order to solve this problem, one pixel is divided into two sub-pixels A and B, and the pixel electrode α of the sub-pixel A is electrically connected to the source electrode of a thin film transistor (TFT) for driving a pixel. A pixel structure in which the pixel electrode β of the pixel B is in a floating state by being insulated from the source electrode of the TFT is known.

In the pixel structure, the control capacitor Cc is formed by the pixel electrode β of the sub-pixel B and the source electrode of the TFT and the insulating film sandwiched between both electrodes. A voltage lower than the voltage applied to the pixel electrode α of the subpixel A is applied to the pixel electrode β of the subpixel B due to the capacitive coupling by the control capacitor Cc. As a result, a region having different TV characteristics is formed in two regions in one pixel so as to alleviate distortion of the TV characteristics in the oblique direction, and the color of the image when viewed from the oblique direction becomes whitish. Can be suppressed and the viewing angle characteristics can be improved.
Japanese Patent Laid-Open No. 2-12 U.S. Pat. No. 4,840,460 Japanese Patent No. 3076938

  By the way, the width of the slit portion between the adjacent ends of the pixel electrodes α and β separating the subpixel A and the subpixel B is usually only about several μm. For this reason, if a patterning defect occurs when the pixel electrodes α and β are formed, the pixel electrode material remains in the slit and the pixel electrodes α and β are short-circuited, which may reduce the manufacturing yield of the liquid crystal display device. ing. In addition, if the pixel electrodes α and β are short-circuited, the same voltage is applied to both the sub-pixels A and B, so that the effect of reducing the distortion of the TV characteristic in the oblique direction is lost and good display characteristics are obtained. The problem arises that it becomes difficult to obtain.

  An object of the present invention is to provide a substrate for a liquid crystal display device and a liquid crystal display device which can obtain bright and good display characteristics with a high transmittance and a high production yield.

  The object is to provide a gate bus line formed on an insulating substrate, a drain bus line formed intersecting the gate bus line through an insulating film, and a storage capacitor formed substantially parallel to the gate bus line. A transistor having a bus line, a gate electrode electrically connected to the gate bus line, a drain electrode electrically connected to the drain bus line, and a transistor electrically connected to a source electrode of the transistor A first pixel electrode, a second pixel electrode formed opposite to the source electrode of the transistor with an insulating film interposed therebetween, and formed separately from the first pixel electrode, and the first pixel electrode, The slit width between adjacent end portions to the second pixel electrode has a slit portion formed wider than the shortest slit width on the storage capacitor bus line. It is achieved by a liquid crystal display device substrate according to.

  According to the present invention, it is possible to realize a liquid crystal display device capable of obtaining bright and good display characteristics with high transmittance and high production yield.

  A substrate for a liquid crystal display device and a liquid crystal display device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a schematic configuration of a liquid crystal display device according to the present embodiment. FIG. 2 shows an equivalent circuit of the configuration of one pixel of the liquid crystal display device according to this embodiment. As shown in FIGS. 1 and 2, the liquid crystal display device includes a gate bus line 1 and a drain bus line (data bus line) 2 which are formed to cross each other through an insulating film, and a TFT 4 which is formed for each pixel. And a TFT substrate 20 having first and second pixel electrodes 6 and 7. In the liquid crystal display device, a counter substrate 40 facing the TFT substrate 20 with a predetermined cell gap is disposed. For example, a liquid crystal having negative dielectric anisotropy is sealed between the TFT substrate 20 and the counter substrate 40. A color filter (CF) and a common electrode 43 are formed on the liquid crystal side surface of the counter substrate 40.

  On the TFT substrate 20, a gate bus line driving circuit 80 on which driver ICs for driving a plurality of gate bus lines 1 are mounted, and a drain bus line driving circuit 82 on which driver ICs for driving a plurality of drain bus lines 2 are mounted. And are connected. These drive circuits 80 and 82 output a scanning signal to a predetermined gate bus line 1 based on a control signal output from the control circuit 84, and output a gradation signal to a plurality of drain bus lines 2. ing. A polarizing plate 87 is disposed on the surface opposite to the liquid crystal side surface of the TFT substrate 20, and a polarizing plate 86 is disposed on the surface opposite to the liquid crystal side surface of the counter substrate 40 in crossed Nicols. Yes. A backlight unit 88 is disposed on the surface of the polarizing plate 87 opposite to the TFT substrate 2.

  As shown in FIG. 2, the gate electrode G of the TFT 4 is connected to the gate bus line 1, and the drain electrode D is connected to the drain bus line 2. The source electrode S of the TFT 4 is electrically connected to the first pixel electrode 6, the storage capacitor electrode 8, and the connection electrode 10. The first pixel electrode 6, the common electrode 43 on the counter substrate 40 facing the first pixel electrode 6, and the liquid crystal sandwiched between the first pixel electrode 6 and the common electrode 43 are first. Liquid crystal capacitance Clc1 is formed. The storage capacitor Cs is formed by the storage capacitor electrode 8, the storage capacitor bus line 3 facing the storage capacitor electrode 8, and an insulating film sandwiched between the storage capacitor electrode 8 and the storage capacitor bus line 3. . A control capacitor Cc is formed by the connection electrode 10, the second pixel electrode 7 facing the connection electrode 10, and an insulating film sandwiched between the connection electrode 10 and the second pixel electrode 7. Further, the second pixel electrode 7, the common electrode 43 on the counter substrate 40 facing the second pixel electrode 7, and the liquid crystal sandwiched between the second pixel electrode 7 and the common electrode 43. A second liquid crystal capacitor Clc2 is formed. In this example, the same potential is applied to the storage capacitor bus line 3 and the common electrode 43.

  As described above, in the pixel according to the present embodiment, the second liquid crystal capacitor Clc2 and the control capacitor Cc are connected in series, and the first liquid crystal capacitor Clc1 and the storage capacitor Cs are connected in parallel. It has a configuration. When the TFT 4 is turned on, the gradation signal supplied to the drain bus line 2 is applied to the first pixel electrode 6, the common electrode 8, and the connection electrode 10, while the storage capacitor bus line and the common electrode 43 have a common potential. Is applied. As a result, the second pixel electrode 7 is maintained at a potential lower than the potential of the gradation signal applied to the first pixel electrode 6 by a predetermined amount.

  FIG. 3 is a plan view showing a configuration of one pixel of the TFT substrate 20 which is a substrate for a liquid crystal display device according to the present embodiment. FIG. 4 shows a cross-sectional configuration of the TFT substrate 20 cut along the line a-a ′ of FIG. 3. As shown in FIGS. 3 and 4, the TFT substrate 20 intersects the gate bus line 1 through a gate bus line 1 formed on a glass substrate (insulating substrate) 21 and an insulating film 22 made of a SiN film or the like. And a drain bus line 2 formed in this manner. In the vicinity of the intersection of the gate bus line 1 and the drain bus line 2, a TFT 4 is arranged as a switching element. A part of the gate bus line 1 functions as a gate electrode (G) of the TFT 4. An operating semiconductor layer of the TFT 4 is formed on the gate bus line 1 via an insulating film (gate insulating film) 22, and a drain electrode (D) and a source electrode (S) are predetermined on the operating semiconductor layer. Are formed to face each other with a gap therebetween. A final protective film 23 made of a SiN film or the like is formed on the entire surface of the substrate on the drain electrode (D) and the source electrode (S).

  A storage capacitor bus line 3 extending in parallel to the gate bus line 1 is formed across the pixel region defined by the gate bus line 1 and the drain bus line 2. On the storage capacitor bus line 3, a storage capacitor electrode 8 is formed for each pixel via an insulating film 22. The storage capacitor electrode 8 is electrically connected to the source electrode (S) of the TFT 4 via the connection electrode 10. The storage capacitor Cs is formed by the insulating film 22 and the storage capacitor bus line 3 and the storage capacitor electrode 8 facing each other through the insulating film 22.

  A pixel region defined by the gate bus line 1 and the drain bus line 2 is divided into a first subpixel A and a second subpixel B. In FIG. 3, for example, the trapezoidal first sub-pixel A is arranged on the left side of the center of the pixel area, and the second sub-pixel B is an upper part and a lower part of the pixel area excluding the first sub-pixel A area. And it is arrange | positioned at the center part right end part. The arrangement of the first and second subpixels A and B in the pixel region is substantially line-symmetric with respect to the storage capacitor bus line 3, for example. A first pixel electrode 6 is formed on the first subpixel A, and a second pixel electrode 7 is formed on the second subpixel B. Both the first and second pixel electrodes 6 and 7 are formed of a transparent conductive film such as ITO.

  Between the adjacent end portions of the first pixel electrode 6 and the second pixel electrode 7 is a slit portion 13 in which ITO is not formed. Since the shapes of the first pixel electrode 6 and the second pixel electrode 7 are defined as described above, the slit portion 13 extends substantially orthogonally from the right side of the pixel with respect to the storage capacitor bus line 3, and then It has a shape that extends diagonally up and down toward the left side of the pixel.

  The slit width between the adjacent end portions of the first pixel electrode 6 and the second pixel electrode 7 in the slit portion 13 is formed to be different depending on the position. The oblique region of the slit portion 13 has a function as a separation slit for separating the first and second pixel electrodes 6 and 7 and also a function as an alignment control structure for controlling the alignment direction of the liquid crystal. . Further, if the slit width of the slit portion 13 is too wide, the electrode areas of the first and second pixel electrodes 6 and 7 are narrowed, the transmittance is lowered, and the luminance is lowered. Taking these conditions into consideration, the slit width c of the region extending vertically to the left side of the pixel of the slit portion 13 is about 10 μm.

  On the other hand, as shown in the imaginary circle 12, the region extending almost orthogonally from the right side of the pixel to the storage capacitor bus line 3 in the slit portion 13 does not contribute to the alignment control of the liquid crystal, and is simply the first and the first. It exists only to separate the two pixel electrodes 6 and 7. For this reason, it is sufficient to secure the shortest slit width c in consideration of the patterning margin in the photolithography technique for the current liquid crystal display device. In this example, the shortest slit width c is 7 μm. This can reduce the possibility that the first and second pixel electrodes 6 and 7 are connected when the pixel electrode is manufactured.

  Further, as shown in the virtual circle 11, the light from the backlight unit is blocked on the storage capacitor bus line 3, so that the transmittance is not affected. Therefore, the slit width a on the storage capacitor bus line 3 is wider than the shortest slit width b in order to further reduce the possibility that the first and second pixel electrodes 6 and 7 are connected at the time of manufacturing the pixel electrode. Forming. In this example, the slit width a on the storage capacitor bus line 3 is about 10 μm and the same as the slit width c. However, the slit width a is not limited to this, and the slit width c is larger than the shortest slit width b. It can be narrower or wider. Thereby, it is possible to reduce the occurrence rate of the short circuit between the first and second pixel electrodes 6 and 7 at the time of manufacturing the pixel electrode without reducing the transmittance of the liquid crystal display device.

  The first pixel electrode 6 is connected to the storage capacitor electrode 8 through the contact hole 9 having the final protective film 23 opened. The storage capacitor electrode 8 is electrically connected to the source electrode (S) of the TFT 4 through the connection electrode 10. As a result, the first pixel electrode 6 is directly connected to the source electrode (S) of the TFT 4 so that the gradation signal on the drain bus line 2 is supplied when the TFT 4 is in the ON state. A part of the second pixel electrode 7 is disposed so as to overlap a part of the connection electrode 10 and the storage capacitor electrode 8 with a final protective film 23 in the normal direction of the substrate surface. The connection electrode 10 and the storage capacitor electrode 8 in the region arranged so as to overlap the second pixel electrode 7 function as a control capacitor electrode, and the final protective film sandwiched between the control capacitor electrode and the second pixel electrode 7. 23 forms a control capacitor (second storage capacitor) Cc. Thereby, the second pixel electrode 7 is indirectly connected to the source electrode (S) of the TFT 4 by capacitive coupling via the control capacitor Cc.

  The counter substrate 40 has a CF resin layer (not shown) formed on the glass substrate and a common electrode 43 formed on the CF resin layer. A liquid crystal capacitor Clc1 is formed between the first pixel electrode 6 of the first subpixel A and the common electrode 43 facing each other through the liquid crystal, and is common to the second pixel electrode 7 of the second subpixel B. A liquid crystal capacitance Clc2 is formed between the electrodes 43. A vertical alignment film (not shown) is formed on the interface of the TFT substrate 20 with the liquid crystal, and a vertical alignment film (not shown) is formed on the interface of the counter substrate 40 with the liquid crystal. Thereby, the liquid crystal molecules when no voltage is applied are aligned substantially perpendicular to the substrate surface.

  When the TFT 4 is turned on and a gradation signal is supplied, a gradation signal potential is applied to the first pixel electrode 6, and the second pixel electrode 7 is connected from the connection electrode 10 through the final protective film 23. Thus, a predetermined potential lower than the gradation signal potential is supplied. As a result, a phenomenon in which regions having different TV characteristics are formed in two regions in one pixel so as to alleviate the distortion of the TV characteristics in the oblique direction, and the color of the image when viewed from the oblique direction becomes whitish. And the viewing angle characteristics can be improved.

  According to the present embodiment, the width of the slit portion 13 is 7 μm at the shortest, and the slit width of the region that does not contribute to the display characteristics is further increased, so that the patterning of the first and second pixel electrodes 6, 7 is performed. Since it is possible to prevent the pixel electrode material from remaining in the slit portion 13 and short circuit between the first and second pixel electrodes 6 and 7, sometimes the manufacturing yield of the liquid crystal display device can be improved. In addition, since a short circuit failure between the first and second pixel electrodes 6 and 7 can be reliably prevented, it is possible to obtain good display characteristics in which distortion of the TV characteristic in the oblique direction is reduced.

  Further, as shown in FIG. 3, the storage capacitor lead line 5 drawn from the storage capacitor bus line 3 is formed along substantially the center of the slit portion 13. By providing the storage capacitor lead line 5, the electric field on the slit portion 13 can be flattened even when a voltage is applied to the liquid crystal, so that no singular point of the alignment vector of liquid crystal molecules is generated on the slit portion 13. can do.

  Further, as shown in FIG. 3, a part of the storage capacitor lead line 5 and a part of the first pixel electrode 6 overlap each other when viewed in the normal direction of the substrate surface. As a result, the aperture ratio of the sub-pixel A can be improved while increasing the electrode area constituting the storage capacitor Cs.

The present invention is not limited to the above embodiment, and various modifications can be made.
For example, in the above embodiment, the VA mode liquid crystal display device using the MVA method has been described as an example. However, the present invention is not limited to this and can be applied to other liquid crystal display devices such as a TN mode.

  Although the transmissive liquid crystal display device has been described as an example in the above embodiment, the present invention is not limited to this, and can be applied to a reflective or transflective liquid crystal display device.

  Further, in the above embodiment, the liquid crystal display device in which CF is formed on the counter substrate disposed to face the TFT substrate is taken as an example. However, the present invention is not limited to this, and CF is formed on the TFT substrate. The present invention can also be applied to a liquid crystal display device having a so-called CF-on-TFT structure.

The substrate for a liquid crystal display device and the liquid crystal display device according to the embodiments described above are summarized as follows.
(Appendix 1)
A gate bus line formed on an insulating substrate;
A drain bus line formed to intersect the gate bus line through an insulating film;
A storage capacitor bus line formed substantially parallel to the gate bus line;
A transistor comprising a gate electrode electrically connected to the gate bus line; and a drain electrode electrically connected to the drain bus line;
A first pixel electrode electrically connected to a source electrode of the transistor;
A second pixel electrode disposed opposite to the source electrode of the transistor via an insulating film and formed separately from the first pixel electrode;
The slit width between adjacent end portions of the first pixel electrode and the second pixel electrode has a slit portion formed wider than the shortest slit width on the storage capacitor bus line. A substrate for a liquid crystal display device.
(Appendix 2)
In the substrate for a liquid crystal display device according to appendix 1,
A substrate for a liquid crystal display device, further comprising a storage capacitor lead line drawn from the storage capacitor bus line and extending to the slit portion.
(Appendix 3)
In the substrate for a liquid crystal display device according to appendix 2,
A substrate for a liquid crystal display device, wherein at least a part of the storage capacitor lead line overlaps the first pixel electrode when viewed in the normal direction of the substrate surface.
(Appendix 4)
In the liquid crystal display substrate according to any one of appendices 1 to 3,
The shortest slit width is 7 μm or more. A substrate for a liquid crystal display device.
(Appendix 5)
A liquid crystal display device comprising a pair of substrates disposed opposite to each other and a liquid crystal sealed between the pair of substrates,
5. A liquid crystal display device according to any one of appendices 1 to 4, wherein one of the pair of substrates is used.

It is a figure which shows schematic structure of the liquid crystal display device by one embodiment of this invention. It is an equivalent circuit diagram which shows the structure of 1 pixel of the liquid crystal display device by one embodiment of this invention. It is a top view which shows the structure of 1 pixel of the board | substrate for liquid crystal display devices by one embodiment of this invention. It is sectional drawing which shows the structure of 1 pixel of the board | substrate for liquid crystal display devices by one embodiment of this invention.

Explanation of symbols

1 Gate bus line 2 Drain bus line 3 Storage capacitor bus line 4 TFT
5 Storage Capacitor Lead Line 6 First Pixel Electrode 7 Second Pixel Electrode 8 Storage Capacitance Electrode 9 Contact Hole 10 Connection Electrode 11, 12 Virtual Circle 13 Slit 20 TFT Substrate 22 Insulating Film 23 Final Protective Film 40 Counter Substrate 43 Common Electrode 80 Gate bus line driving circuit 82 Drain bus line driving circuit 84 Control circuit 86, 87 Polarizing plate 88 Backlight unit

Claims (5)

A gate bus line formed on an insulating substrate;
A drain bus line formed to intersect the gate bus line through an insulating film;
A storage capacitor bus line formed substantially parallel to the gate bus line;
A transistor comprising a gate electrode electrically connected to the gate bus line; and a drain electrode electrically connected to the drain bus line;
A first pixel electrode electrically connected to a source electrode of the transistor;
A second pixel electrode disposed opposite to the source electrode of the transistor via an insulating film and formed separately from the first pixel electrode;
The slit width between adjacent end portions of the first pixel electrode and the second pixel electrode has a slit portion formed wider than the shortest slit width on the storage capacitor bus line. A substrate for a liquid crystal display device. The substrate for a liquid crystal display device according to claim 1,
A substrate for a liquid crystal display device, further comprising a storage capacitor lead line drawn from the storage capacitor bus line and extending to the slit portion. The substrate for a liquid crystal display device according to claim 2,
A substrate for a liquid crystal display device, wherein at least a part of the storage capacitor lead line overlaps the first pixel electrode when viewed in the normal direction of the substrate surface. The substrate for a liquid crystal display device according to any one of claims 1 to 3,
The shortest slit width is 7 μm or more. A substrate for a liquid crystal display device. A liquid crystal display device comprising a pair of substrates disposed opposite to each other and a liquid crystal sealed between the pair of substrates,
5. The liquid crystal display device according to claim 1, wherein the substrate for a liquid crystal display device according to claim 1 is used on one of the pair of substrates.

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